forked from ~ljy/RK356X_SDK_RELEASE
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hc
2024-10-09 244b2c5ca8b14627e4a17755e5922221e121c771 
 kernel/drivers/clk/rockchip/clk-rk3568.c
....@@ -1068,13 +1068,13 @@
10681068 			RK3568_CLKGATE_CON(20), 8, GFLAGS),
10691069 	GATE(HCLK_VOP, "hclk_vop", "hclk_vo", 0,
10701070 			RK3568_CLKGATE_CON(20), 9, GFLAGS),
1071
-	COMPOSITE(DCLK_VOP0, "dclk_vop0", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
1071
+	COMPOSITE(DCLK_VOP0, "dclk_vop0", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_NO_REPARENT,
10721072 			RK3568_CLKSEL_CON(39), 10, 2, MFLAGS, 0, 8, DFLAGS,
10731073 			RK3568_CLKGATE_CON(20), 10, GFLAGS),
1074
-	COMPOSITE(DCLK_VOP1, "dclk_vop1", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
1074
+	COMPOSITE(DCLK_VOP1, "dclk_vop1", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_NO_REPARENT,
10751075 			RK3568_CLKSEL_CON(40), 10, 2, MFLAGS, 0, 8, DFLAGS,
10761076 			RK3568_CLKGATE_CON(20), 11, GFLAGS),
1077
-	COMPOSITE(DCLK_VOP2, "dclk_vop2", hpll_vpll_gpll_cpll_p, 0,
1077
+	COMPOSITE(DCLK_VOP2, "dclk_vop2", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_NO_REPARENT,
10781078 			RK3568_CLKSEL_CON(41), 10, 2, MFLAGS, 0, 8, DFLAGS,
10791079 			RK3568_CLKGATE_CON(20), 12, GFLAGS),
10801080 	GATE(CLK_VOP_PWM, "clk_vop_pwm", "xin24m", 0,