forked from ~ljy/RK356X_SDK_RELEASE
blame | history | patch | commit | commitdiff
hc
2024-10-09 244b2c5ca8b14627e4a17755e5922221e121c771 
 kernel/drivers/clk/rockchip/clk-rk3308.c
....@@ -1,33 +1,21 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
2
- * Copyright (c) 2017 Rockchip Electronics Co. Ltd.
3
+ * Copyright (c) 2019 Rockchip Electronics Co. Ltd.
34  * Author: Finley Xiao <finley.xiao@rock-chips.com>
4
- *
5
- * This program is free software; you can redistribute it and/or modify
6
- * it under the terms of the GNU General Public License as published by
7
- * the Free Software Foundation; either version 2 of the License, or
8
- * (at your option) any later version.
9
- *
10
- * This program is distributed in the hope that it will be useful,
11
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
12
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13
- * GNU General Public License for more details.
145  */
156 
167 #include <linux/clk-provider.h>
8
+#include <linux/io.h>
179 #include <linux/of.h>
1810 #include <linux/of_address.h>
11
+#include <linux/module.h>
12
+#include <linux/of_device.h>
1913 #include <linux/rockchip/cpu.h>
2014 #include <linux/syscore_ops.h>
2115 #include <dt-bindings/clock/rk3308-cru.h>
2216 #include "clk.h"
2317 
2418 #define RK3308_GRF_SOC_STATUS0		0x380
25
-#define RK3308_VOP_FRAC_MAX_PRATE	270000000
26
-#define RK3308B_VOP_FRAC_MAX_PRATE	800000000
27
-#define RK3308_UART_FRAC_MAX_PRATE	800000000
28
-#define RK3308_PDM_FRAC_MAX_PRATE	800000000
29
-#define RK3308_SPDIF_FRAC_MAX_PRATE	800000000
30
-#define RK3308_I2S_FRAC_MAX_PRATE	800000000
3119 
3220 enum rk3308_plls {
3321 	apll, dpll, vpll0, vpll1,
....@@ -136,7 +124,6 @@
136124 
137125 PNAME(mux_pll_p)		= { "xin24m" };
138126 PNAME(mux_usb480m_p)		= { "xin24m", "usb480m_phy", "clk_rtc32k" };
139
-PNAME(mux_armclk_p)		= { "apll_core", "vpll0_core", "vpll1_core" };
140127 PNAME(mux_dpll_vpll0_p)		= { "dpll", "vpll0" };
141128 PNAME(mux_dpll_vpll0_xin24m_p)	= { "dpll", "vpll0", "xin24m" };
142129 PNAME(mux_dpll_vpll0_vpll1_p)	= { "dpll", "vpll0", "vpll1" };
....@@ -149,7 +136,6 @@
149136 PNAME(mux_uart2_p)		= { "clk_uart2_src", "dummy", "clk_uart2_frac" };
150137 PNAME(mux_uart3_p)		= { "clk_uart3_src", "dummy", "clk_uart3_frac" };
151138 PNAME(mux_uart4_p)		= { "clk_uart4_src", "dummy", "clk_uart4_frac" };
152
-PNAME(mux_timer_src_p)		= { "xin24m", "clk_rtc32k" };
153139 PNAME(mux_dclk_vop_p)		= { "dclk_vop_src", "dclk_vop_frac", "xin24m" };
154140 PNAME(mux_nandc_p)		= { "clk_nandc_div", "clk_nandc_div50" };
155141 PNAME(mux_sdmmc_p)		= { "clk_sdmmc_div", "clk_sdmmc_div50" };
....@@ -191,8 +177,8 @@
191177 PNAME(mux_spdif_tx_p)		= { "clk_spdif_tx_src", "clk_spdif_tx_frac", "mclk_i2s0_2ch_in" };
192178 PNAME(mux_spdif_rx_src_p)	= { "clk_spdif_rx_div", "clk_spdif_rx_div50" };
193179 PNAME(mux_spdif_rx_p)		= { "clk_spdif_rx_src", "clk_spdif_rx_frac" };
194
-PNAME(mux_uart_src_p)		= { "xin24m", "usb480m", "dpll", "vpll0", "vpll1" };
195
-static u32 uart_src_mux_idx[]	= { 4, 3, 0, 1, 2 };
180
+PNAME(mux_uart_src_p)		= { "usb480m", "xin24m", "dpll", "vpll0", "vpll1" };
181
+static u32 uart_src_mux_idx[]	= { 3, 4, 0, 1, 2 };
196182 
197183 static struct rockchip_pll_clock rk3308_pll_clks[] __initdata = {
198184 	[apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
....@@ -330,18 +316,18 @@
330316 	 * Clock-Architecture Diagram 3
331317 	 */
332318 
333
-	COMPOSITE_NODIV(ACLK_BUS_SRC, "clk_bus_src", mux_dpll_vpll0_vpll1_p, CLK_IGNORE_UNUSED,
319
+	COMPOSITE_NODIV(ACLK_BUS_SRC, "clk_bus_src", mux_dpll_vpll0_vpll1_p, CLK_IS_CRITICAL,
334320 			RK3308_CLKSEL_CON(5), 6, 2, MFLAGS,
335321 			RK3308_CLKGATE_CON(1), 0, GFLAGS),
336
-	COMPOSITE_NOMUX(PCLK_BUS, "pclk_bus", "clk_bus_src", CLK_IGNORE_UNUSED,
322
+	COMPOSITE_NOMUX(PCLK_BUS, "pclk_bus", "clk_bus_src", CLK_IS_CRITICAL,
337323 			RK3308_CLKSEL_CON(6), 8, 5, DFLAGS,
338324 			RK3308_CLKGATE_CON(1), 3, GFLAGS),
339325 	GATE(PCLK_DDR, "pclk_ddr", "pclk_bus", CLK_IGNORE_UNUSED,
340326 			RK3308_CLKGATE_CON(4), 15, GFLAGS),
341
-	COMPOSITE_NOMUX(HCLK_BUS, "hclk_bus", "clk_bus_src", CLK_IGNORE_UNUSED,
327
+	COMPOSITE_NOMUX(HCLK_BUS, "hclk_bus", "clk_bus_src", CLK_IS_CRITICAL,
342328 			RK3308_CLKSEL_CON(6), 0, 5, DFLAGS,
343329 			RK3308_CLKGATE_CON(1), 2, GFLAGS),
344
-	COMPOSITE_NOMUX(ACLK_BUS, "aclk_bus", "clk_bus_src", CLK_IGNORE_UNUSED,
330
+	COMPOSITE_NOMUX(ACLK_BUS, "aclk_bus", "clk_bus_src", CLK_IS_CRITICAL,
345331 			RK3308_CLKSEL_CON(5), 0, 5, DFLAGS,
346332 			RK3308_CLKGATE_CON(1), 1, GFLAGS),
347333 
....@@ -349,9 +335,9 @@
349335 			RK3308_CLKSEL_CON(10), 13, 3, MFLAGS, uart_src_mux_idx, 0, 5, DFLAGS,
350336 			RK3308_CLKGATE_CON(1), 9, GFLAGS),
351337 	COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_src", CLK_SET_RATE_PARENT,
352
-			RK3308_CLKSEL_CON(12), 0,
338
+			RK3308_CLKSEL_CON(12), CLK_FRAC_DIVIDER_NO_LIMIT,
353339 			RK3308_CLKGATE_CON(1), 11, GFLAGS,
354
-			&rk3308_uart0_fracmux, RK3308_UART_FRAC_MAX_PRATE),
340
+			&rk3308_uart0_fracmux),
355341 	GATE(SCLK_UART0, "clk_uart0", "clk_uart0_mux", 0,
356342 			RK3308_CLKGATE_CON(1), 12, GFLAGS),
357343 
....@@ -359,9 +345,9 @@
359345 			RK3308_CLKSEL_CON(13), 13, 3, MFLAGS, uart_src_mux_idx, 0, 5, DFLAGS,
360346 			RK3308_CLKGATE_CON(1), 13, GFLAGS),
361347 	COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT,
362
-			RK3308_CLKSEL_CON(15), 0,
348
+			RK3308_CLKSEL_CON(15), CLK_FRAC_DIVIDER_NO_LIMIT,
363349 			RK3308_CLKGATE_CON(1), 15, GFLAGS,
364
-			&rk3308_uart1_fracmux, RK3308_UART_FRAC_MAX_PRATE),
350
+			&rk3308_uart1_fracmux),
365351 	GATE(SCLK_UART1, "clk_uart1", "clk_uart1_mux", 0,
366352 			RK3308_CLKGATE_CON(2), 0, GFLAGS),
367353 
....@@ -369,9 +355,9 @@
369355 			RK3308_CLKSEL_CON(16), 13, 3, MFLAGS, uart_src_mux_idx, 0, 5, DFLAGS,
370356 			RK3308_CLKGATE_CON(2), 1, GFLAGS),
371357 	COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT,
372
-			RK3308_CLKSEL_CON(18), 0,
358
+			RK3308_CLKSEL_CON(18), CLK_FRAC_DIVIDER_NO_LIMIT,
373359 			RK3308_CLKGATE_CON(2), 3, GFLAGS,
374
-			&rk3308_uart2_fracmux, RK3308_UART_FRAC_MAX_PRATE),
360
+			&rk3308_uart2_fracmux),
375361 	GATE(SCLK_UART2, "clk_uart2", "clk_uart2_mux", CLK_SET_RATE_PARENT,
376362 			RK3308_CLKGATE_CON(2), 4, GFLAGS),
377363 
....@@ -379,9 +365,9 @@
379365 			RK3308_CLKSEL_CON(19), 13, 3, MFLAGS, uart_src_mux_idx, 0, 5, DFLAGS,
380366 			RK3308_CLKGATE_CON(2), 5, GFLAGS),
381367 	COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT,
382
-			RK3308_CLKSEL_CON(21), 0,
368
+			RK3308_CLKSEL_CON(21), CLK_FRAC_DIVIDER_NO_LIMIT,
383369 			RK3308_CLKGATE_CON(2), 7, GFLAGS,
384
-			&rk3308_uart3_fracmux, RK3308_UART_FRAC_MAX_PRATE),
370
+			&rk3308_uart3_fracmux),
385371 	GATE(SCLK_UART3, "clk_uart3", "clk_uart3_mux", 0,
386372 			RK3308_CLKGATE_CON(2), 8, GFLAGS),
387373 
....@@ -389,9 +375,9 @@
389375 			RK3308_CLKSEL_CON(22), 13, 3, MFLAGS, uart_src_mux_idx, 0, 5, DFLAGS,
390376 			RK3308_CLKGATE_CON(2), 9, GFLAGS),
391377 	COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT,
392
-			RK3308_CLKSEL_CON(24), 0,
378
+			RK3308_CLKSEL_CON(24), CLK_FRAC_DIVIDER_NO_LIMIT,
393379 			RK3308_CLKGATE_CON(2), 11, GFLAGS,
394
-			&rk3308_uart4_fracmux, RK3308_UART_FRAC_MAX_PRATE),
380
+			&rk3308_uart4_fracmux),
395381 	GATE(SCLK_UART4, "clk_uart4", "clk_uart4_mux", 0,
396382 			RK3308_CLKGATE_CON(2), 12, GFLAGS),
397383 
....@@ -468,6 +454,10 @@
468454 	COMPOSITE(0, "dclk_vop_src", mux_dpll_vpll0_vpll1_p, 0,
469455 			RK3308_CLKSEL_CON(8), 10, 2, MFLAGS, 0, 8, DFLAGS,
470456 			RK3308_CLKGATE_CON(1), 6, GFLAGS),
457
+	COMPOSITE_FRACMUX(0, "dclk_vop_frac", "dclk_vop_src", CLK_SET_RATE_PARENT,
458
+			RK3308_CLKSEL_CON(9), 0,
459
+			RK3308_CLKGATE_CON(1), 7, GFLAGS,
460
+			&rk3308_dclk_vop_fracmux),
471461 	GATE(DCLK_VOP, "dclk_vop", "dclk_vop_mux", 0,
472462 			RK3308_CLKGATE_CON(1), 8, GFLAGS),
473463 
....@@ -475,16 +465,16 @@
475465 	 * Clock-Architecture Diagram 4
476466 	 */
477467 
478
-	COMPOSITE_NODIV(ACLK_PERI_SRC, "clk_peri_src", mux_dpll_vpll0_vpll1_p, CLK_IGNORE_UNUSED,
468
+	COMPOSITE_NODIV(ACLK_PERI_SRC, "clk_peri_src", mux_dpll_vpll0_vpll1_p, CLK_IS_CRITICAL,
479469 			RK3308_CLKSEL_CON(36), 6, 2, MFLAGS,
480470 			RK3308_CLKGATE_CON(8), 0, GFLAGS),
481
-	COMPOSITE_NOMUX(ACLK_PERI, "aclk_peri", "clk_peri_src", CLK_IGNORE_UNUSED,
471
+	COMPOSITE_NOMUX(ACLK_PERI, "aclk_peri", "clk_peri_src", CLK_IS_CRITICAL,
482472 			RK3308_CLKSEL_CON(36), 0, 5, DFLAGS,
483473 			RK3308_CLKGATE_CON(8), 1, GFLAGS),
484
-	COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "clk_peri_src", CLK_IGNORE_UNUSED,
474
+	COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "clk_peri_src", CLK_IS_CRITICAL,
485475 			RK3308_CLKSEL_CON(37), 0, 5, DFLAGS,
486476 			RK3308_CLKGATE_CON(8), 2, GFLAGS),
487
-	COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "clk_peri_src", CLK_IGNORE_UNUSED,
477
+	COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "clk_peri_src", CLK_IS_CRITICAL,
488478 			RK3308_CLKSEL_CON(37), 8, 5, DFLAGS,
489479 			RK3308_CLKGATE_CON(8), 3, GFLAGS),
490480 
....@@ -575,12 +565,10 @@
575565 	GATE(0, "clk_ddr_msch_peribus", "clk_ddrphy1x_out", CLK_IGNORE_UNUSED,
576566 			RK3308_CLKGATE_CON(4), 13, GFLAGS),
577567 
578
-	COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_dpll_vpll0_vpll1_p, 0,
579
-			RK3308_CLKSEL_CON(1), 6, 2, 0, 0, ROCKCHIP_DDRCLK_SIP_V2),
580
-	COMPOSITE(0, "clk_ddrphy4x_src", mux_dpll_vpll0_vpll1_p, CLK_IGNORE_UNUSED,
568
+	COMPOSITE(SCLK_DDRCLK, "clk_ddrphy4x_src", mux_dpll_vpll0_vpll1_p, CLK_IS_CRITICAL,
581569 			RK3308_CLKSEL_CON(1), 6, 2, MFLAGS, 0, 3, DFLAGS,
582570 			RK3308_CLKGATE_CON(0), 10, GFLAGS),
583
-	GATE(0, "clk_ddrphy4x", "clk_ddrphy4x_src", CLK_IGNORE_UNUSED,
571
+	GATE(0, "clk_ddrphy4x", "clk_ddrphy4x_src", CLK_IS_CRITICAL,
584572 			RK3308_CLKGATE_CON(0), 11, GFLAGS),
585573 	FACTOR_GATE(0, "clk_ddr_stdby_div4", "clk_ddrphy4x", CLK_IGNORE_UNUSED, 1, 4,
586574 			RK3308_CLKGATE_CON(0), 13, GFLAGS),
....@@ -600,7 +588,7 @@
600588 	COMPOSITE_FRACMUX(0, "clk_rtc32k_frac", "xin24m", CLK_IGNORE_UNUSED,
601589 			RK3308_CLKSEL_CON(3), 0,
602590 			RK3308_CLKGATE_CON(4), 3, GFLAGS,
603
-			&rk3308_rtc32k_fracmux, 0),
591
+			&rk3308_rtc32k_fracmux),
604592 	MUX(0, "clk_rtc32k_div_src", mux_vpll0_vpll1_p, 0,
605593 			RK3308_CLKSEL_CON(2), 10, 1, MFLAGS),
606594 	COMPOSITE_NOMUX(0, "clk_rtc32k_div", "clk_rtc32k_div_src", CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT,
....@@ -634,13 +622,13 @@
634622 	 * Clock-Architecture Diagram 7
635623 	 */
636624 
637
-	COMPOSITE_NODIV(0, "clk_audio_src", mux_vpll0_vpll1_xin24m_p, 0,
625
+	COMPOSITE_NODIV(0, "clk_audio_src", mux_vpll0_vpll1_xin24m_p, CLK_IS_CRITICAL,
638626 			RK3308_CLKSEL_CON(45), 6, 2, MFLAGS,
639627 			RK3308_CLKGATE_CON(10), 0, GFLAGS),
640
-	COMPOSITE_NOMUX(HCLK_AUDIO, "hclk_audio", "clk_audio_src", 0,
628
+	COMPOSITE_NOMUX(HCLK_AUDIO, "hclk_audio", "clk_audio_src", CLK_IS_CRITICAL,
641629 			RK3308_CLKSEL_CON(45), 0, 5, DFLAGS,
642630 			RK3308_CLKGATE_CON(10), 1, GFLAGS),
643
-	COMPOSITE_NOMUX(PCLK_AUDIO, "pclk_audio", "clk_audio_src", 0,
631
+	COMPOSITE_NOMUX(PCLK_AUDIO, "pclk_audio", "clk_audio_src", CLK_IS_CRITICAL,
644632 			RK3308_CLKSEL_CON(45), 8, 5, DFLAGS,
645633 			RK3308_CLKGATE_CON(10), 2, GFLAGS),
646634 
....@@ -650,7 +638,7 @@
650638 	COMPOSITE_FRACMUX(0, "clk_pdm_frac", "clk_pdm_src", CLK_SET_RATE_PARENT,
651639 			RK3308_CLKSEL_CON(47), 0,
652640 			RK3308_CLKGATE_CON(10), 4, GFLAGS,
653
-			&rk3308_pdm_fracmux, RK3308_PDM_FRAC_MAX_PRATE),
641
+			&rk3308_pdm_fracmux),
654642 	GATE(SCLK_PDM, "clk_pdm", "clk_pdm_mux", 0,
655643 			RK3308_CLKGATE_CON(10), 5, GFLAGS),
656644 
....@@ -660,7 +648,7 @@
660648 	COMPOSITE_FRACMUX(0, "clk_i2s0_8ch_tx_frac", "clk_i2s0_8ch_tx_src", CLK_SET_RATE_PARENT,
661649 			RK3308_CLKSEL_CON(53), 0,
662650 			RK3308_CLKGATE_CON(10), 13, GFLAGS,
663
-			&rk3308_i2s0_8ch_tx_fracmux, RK3308_I2S_FRAC_MAX_PRATE),
651
+			&rk3308_i2s0_8ch_tx_fracmux),
664652 	COMPOSITE_NODIV(SCLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", mux_i2s0_8ch_tx_rx_p, CLK_SET_RATE_PARENT,
665653 			RK3308_CLKSEL_CON(52), 12, 1, MFLAGS,
666654 			RK3308_CLKGATE_CON(10), 14, GFLAGS),
....@@ -674,7 +662,7 @@
674662 	COMPOSITE_FRACMUX(0, "clk_i2s0_8ch_rx_frac", "clk_i2s0_8ch_rx_src", CLK_SET_RATE_PARENT,
675663 			RK3308_CLKSEL_CON(55), 0,
676664 			RK3308_CLKGATE_CON(11), 1, GFLAGS,
677
-			&rk3308_i2s0_8ch_rx_fracmux, RK3308_I2S_FRAC_MAX_PRATE),
665
+			&rk3308_i2s0_8ch_rx_fracmux),
678666 	COMPOSITE_NODIV(SCLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", mux_i2s0_8ch_rx_tx_p, CLK_SET_RATE_PARENT,
679667 			RK3308_CLKSEL_CON(54), 12, 1, MFLAGS,
680668 			RK3308_CLKGATE_CON(11), 2, GFLAGS),
....@@ -687,7 +675,7 @@
687675 	COMPOSITE_FRACMUX(0, "clk_i2s1_8ch_tx_frac", "clk_i2s1_8ch_tx_src", CLK_SET_RATE_PARENT,
688676 			RK3308_CLKSEL_CON(57), 0,
689677 			RK3308_CLKGATE_CON(11), 5, GFLAGS,
690
-			&rk3308_i2s1_8ch_tx_fracmux, RK3308_I2S_FRAC_MAX_PRATE),
678
+			&rk3308_i2s1_8ch_tx_fracmux),
691679 	COMPOSITE_NODIV(SCLK_I2S1_8CH_TX, "clk_i2s1_8ch_tx", mux_i2s1_8ch_tx_rx_p, CLK_SET_RATE_PARENT,
692680 			RK3308_CLKSEL_CON(56), 12, 1, MFLAGS,
693681 			RK3308_CLKGATE_CON(11), 6, GFLAGS),
....@@ -701,7 +689,7 @@
701689 	COMPOSITE_FRACMUX(0, "clk_i2s1_8ch_rx_frac", "clk_i2s1_8ch_rx_src", CLK_SET_RATE_PARENT,
702690 			RK3308_CLKSEL_CON(59), 0,
703691 			RK3308_CLKGATE_CON(11), 9, GFLAGS,
704
-			&rk3308_i2s1_8ch_rx_fracmux, RK3308_I2S_FRAC_MAX_PRATE),
692
+			&rk3308_i2s1_8ch_rx_fracmux),
705693 	COMPOSITE_NODIV(SCLK_I2S1_8CH_RX, "clk_i2s1_8ch_rx", mux_i2s1_8ch_rx_tx_p, CLK_SET_RATE_PARENT,
706694 			RK3308_CLKSEL_CON(58), 12, 1, MFLAGS,
707695 			RK3308_CLKGATE_CON(11), 10, GFLAGS),
....@@ -714,7 +702,7 @@
714702 	COMPOSITE_FRACMUX(0, "clk_i2s2_8ch_tx_frac", "clk_i2s2_8ch_tx_src", CLK_SET_RATE_PARENT,
715703 			RK3308_CLKSEL_CON(61), 0,
716704 			RK3308_CLKGATE_CON(11), 13, GFLAGS,
717
-			&rk3308_i2s2_8ch_tx_fracmux, RK3308_I2S_FRAC_MAX_PRATE),
705
+			&rk3308_i2s2_8ch_tx_fracmux),
718706 	COMPOSITE_NODIV(SCLK_I2S2_8CH_TX, "clk_i2s2_8ch_tx", mux_i2s2_8ch_tx_rx_p, CLK_SET_RATE_PARENT,
719707 			RK3308_CLKSEL_CON(60), 12, 1, MFLAGS,
720708 			RK3308_CLKGATE_CON(11), 14, GFLAGS),
....@@ -728,7 +716,7 @@
728716 	COMPOSITE_FRACMUX(0, "clk_i2s2_8ch_rx_frac", "clk_i2s2_8ch_rx_src", CLK_SET_RATE_PARENT,
729717 			RK3308_CLKSEL_CON(63), 0,
730718 			RK3308_CLKGATE_CON(12), 1, GFLAGS,
731
-			&rk3308_i2s2_8ch_rx_fracmux, RK3308_I2S_FRAC_MAX_PRATE),
719
+			&rk3308_i2s2_8ch_rx_fracmux),
732720 	COMPOSITE_NODIV(SCLK_I2S2_8CH_RX, "clk_i2s2_8ch_rx", mux_i2s2_8ch_rx_tx_p, CLK_SET_RATE_PARENT,
733721 			RK3308_CLKSEL_CON(62), 12, 1, MFLAGS,
734722 			RK3308_CLKGATE_CON(12), 2, GFLAGS),
....@@ -741,7 +729,7 @@
741729 	COMPOSITE_FRACMUX(0, "clk_i2s3_8ch_tx_frac", "clk_i2s3_8ch_tx_src", CLK_SET_RATE_PARENT,
742730 			RK3308_CLKSEL_CON(65), 0,
743731 			RK3308_CLKGATE_CON(12), 5, GFLAGS,
744
-			&rk3308_i2s3_8ch_tx_fracmux, RK3308_I2S_FRAC_MAX_PRATE),
732
+			&rk3308_i2s3_8ch_tx_fracmux),
745733 	COMPOSITE_NODIV(SCLK_I2S3_8CH_TX, "clk_i2s3_8ch_tx", mux_i2s3_8ch_tx_rx_p, CLK_SET_RATE_PARENT,
746734 			RK3308_CLKSEL_CON(64), 12, 1, MFLAGS,
747735 			RK3308_CLKGATE_CON(12), 6, GFLAGS),
....@@ -755,7 +743,7 @@
755743 	COMPOSITE_FRACMUX(0, "clk_i2s3_8ch_rx_frac", "clk_i2s3_8ch_rx_src", CLK_SET_RATE_PARENT,
756744 			RK3308_CLKSEL_CON(67), 0,
757745 			RK3308_CLKGATE_CON(12), 9, GFLAGS,
758
-			&rk3308_i2s3_8ch_rx_fracmux, RK3308_I2S_FRAC_MAX_PRATE),
746
+			&rk3308_i2s3_8ch_rx_fracmux),
759747 	COMPOSITE_NODIV(SCLK_I2S3_8CH_RX, "clk_i2s3_8ch_rx", mux_i2s3_8ch_rx_tx_p, CLK_SET_RATE_PARENT,
760748 			RK3308_CLKSEL_CON(66), 12, 1, MFLAGS,
761749 			RK3308_CLKGATE_CON(12), 10, GFLAGS),
....@@ -768,7 +756,7 @@
768756 	COMPOSITE_FRACMUX(0, "clk_i2s0_2ch_frac", "clk_i2s0_2ch_src", CLK_SET_RATE_PARENT,
769757 			RK3308_CLKSEL_CON(69), 0,
770758 			RK3308_CLKGATE_CON(12), 13, GFLAGS,
771
-			&rk3308_i2s0_2ch_fracmux, RK3308_I2S_FRAC_MAX_PRATE),
759
+			&rk3308_i2s0_2ch_fracmux),
772760 	GATE(SCLK_I2S0_2CH, "clk_i2s0_2ch", "clk_i2s0_2ch_mux", 0,
773761 			RK3308_CLKGATE_CON(12), 14, GFLAGS),
774762 	COMPOSITE_NODIV(SCLK_I2S0_2CH_OUT, "clk_i2s0_2ch_out", mux_i2s0_2ch_out_p, CLK_SET_RATE_PARENT,
....@@ -781,7 +769,7 @@
781769 	COMPOSITE_FRACMUX(0, "clk_i2s1_2ch_frac", "clk_i2s1_2ch_src", CLK_SET_RATE_PARENT,
782770 			RK3308_CLKSEL_CON(71), 0,
783771 			RK3308_CLKGATE_CON(13), 1, GFLAGS,
784
-			&rk3308_i2s1_2ch_fracmux, RK3308_I2S_FRAC_MAX_PRATE),
772
+			&rk3308_i2s1_2ch_fracmux),
785773 	GATE(SCLK_I2S1_2CH, "clk_i2s1_2ch", "clk_i2s1_2ch_mux", 0,
786774 			RK3308_CLKGATE_CON(13), 2, GFLAGS),
787775 	COMPOSITE_NODIV(SCLK_I2S1_2CH_OUT, "clk_i2s1_2ch_out", mux_i2s1_2ch_out_p, CLK_SET_RATE_PARENT,
....@@ -799,7 +787,7 @@
799787 	COMPOSITE_FRACMUX(0, "clk_spdif_tx_frac", "clk_spdif_tx_src", CLK_SET_RATE_PARENT,
800788 			RK3308_CLKSEL_CON(49), 0,
801789 			RK3308_CLKGATE_CON(10), 7, GFLAGS,
802
-			&rk3308_spdif_tx_fracmux, RK3308_SPDIF_FRAC_MAX_PRATE),
790
+			&rk3308_spdif_tx_fracmux),
803791 	GATE(SCLK_SPDIF_TX, "clk_spdif_tx", "clk_spdif_tx_mux", 0,
804792 			RK3308_CLKGATE_CON(10), 8, GFLAGS),
805793 
....@@ -814,7 +802,7 @@
814802 	COMPOSITE_FRACMUX(0, "clk_spdif_rx_frac", "clk_spdif_rx_src", CLK_SET_RATE_PARENT,
815803 			RK3308_CLKSEL_CON(51), 0,
816804 			RK3308_CLKGATE_CON(10), 10, GFLAGS,
817
-			&rk3308_spdif_rx_fracmux, RK3308_SPDIF_FRAC_MAX_PRATE),
805
+			&rk3308_spdif_rx_fracmux),
818806 	GATE(SCLK_SPDIF_RX, "clk_spdif_rx", "clk_spdif_rx_mux", 0,
819807 			RK3308_CLKGATE_CON(10), 11, GFLAGS),
820808 
....@@ -865,6 +853,12 @@
865853 	GATE(ACLK_CRYPTO, "aclk_crypto", "aclk_bus", 0, RK3308_CLKGATE_CON(5), 2, GFLAGS),
866854 	GATE(ACLK_VOP, "aclk_vop", "aclk_bus", 0, RK3308_CLKGATE_CON(5), 3, GFLAGS),
867855 	GATE(0, "aclk_gic", "aclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(5), 4, GFLAGS),
856
+	/* aclk_dmaci0 is controlled by sgrf_clkgat_con. */
857
+	SGRF_GATE(ACLK_DMAC0, "aclk_dmac0", "aclk_bus"),
858
+	/* aclk_dmac1 is controlled by sgrf_clkgat_con. */
859
+	SGRF_GATE(ACLK_DMAC1, "aclk_dmac1", "aclk_bus"),
860
+	/* watchdog pclk is controlled by sgrf_clkgat_con. */
861
+	SGRF_GATE(PCLK_WDT, "pclk_wdt", "pclk_bus"),
868862 
869863 	GATE(0, "hclk_bus_niu", "hclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(5), 5, GFLAGS),
870864 	GATE(0, "hclk_rom", "hclk_bus", CLK_IGNORE_UNUSED, RK3308_CLKGATE_CON(5), 6, GFLAGS),
....@@ -915,26 +909,14 @@
915909 	COMPOSITE_FRACMUX(0, "dclk_vop_frac", "dclk_vop_src", CLK_SET_RATE_PARENT,
916910 			RK3308_CLKSEL_CON(9), 0,
917911 			RK3308_CLKGATE_CON(1), 7, GFLAGS,
918
-			&rk3308_dclk_vop_fracmux, RK3308_VOP_FRAC_MAX_PRATE),
912
+			&rk3308_dclk_vop_fracmux),
919913 };
920914 
921915 static struct rockchip_clk_branch rk3308b_dclk_vop_frac[] __initdata = {
922916 	COMPOSITE_FRACMUX(0, "dclk_vop_frac", "dclk_vop_src", CLK_SET_RATE_PARENT,
923917 			RK3308_CLKSEL_CON(9), 0,
924918 			RK3308_CLKGATE_CON(1), 7, GFLAGS,
925
-			&rk3308_dclk_vop_fracmux, RK3308B_VOP_FRAC_MAX_PRATE),
926
-};
927
-
928
-static const char *const rk3308_critical_clocks[] __initconst = {
929
-	"aclk_bus",
930
-	"hclk_bus",
931
-	"pclk_bus",
932
-	"aclk_peri",
933
-	"hclk_peri",
934
-	"pclk_peri",
935
-	"hclk_audio",
936
-	"pclk_audio",
937
-	"sclk_ddrc",
919
+			&rk3308_dclk_vop_fracmux),
938920 };
939921 
940922 static void __iomem *rk3308_cru_base;
....@@ -948,24 +930,12 @@
948930 			       0x500, false);
949931 	}
950932 }
951
-EXPORT_SYMBOL_GPL(rk3308_dump_cru);
952
-
953
-static int rk3308_clk_panic(struct notifier_block *this,
954
-			    unsigned long ev, void *ptr)
955
-{
956
-	rk3308_dump_cru();
957
-	return NOTIFY_DONE;
958
-}
959
-
960
-static struct notifier_block rk3308_clk_panic_block = {
961
-	.notifier_call = rk3308_clk_panic,
962
-};
963933 
964934 static void __init rk3308_clk_init(struct device_node *np)
965935 {
966936 	struct rockchip_clk_provider *ctx;
967937 	void __iomem *reg_base;
968
-	struct clk *clk;
938
+	struct clk **clks;
969939 
970940 	reg_base = of_iomap(np, 0);
971941 	if (!reg_base) {
....@@ -973,38 +943,13 @@
973943 		return;
974944 	}
975945 
976
-	rk3308_cru_base = reg_base;
977
-
978946 	ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
979947 	if (IS_ERR(ctx)) {
980948 		pr_err("%s: rockchip clk init failed\n", __func__);
981949 		iounmap(reg_base);
982950 		return;
983951 	}
984
-
985
-	/* aclk_dmac0 is controlled by sgrf. */
986
-	clk = clk_register_fixed_factor(NULL, "aclk_dmac0", "aclk_bus", 0, 1, 1);
987
-	if (IS_ERR(clk))
988
-		pr_warn("%s: could not register clock aclk_dmac0: %ld\n",
989
-			__func__, PTR_ERR(clk));
990
-	else
991
-		rockchip_clk_add_lookup(ctx, clk, ACLK_DMAC0);
992
-
993
-	/* aclk_dmac1 is controlled by sgrf. */
994
-	clk = clk_register_fixed_factor(NULL, "aclk_dmac1", "aclk_bus", 0, 1, 1);
995
-	if (IS_ERR(clk))
996
-		pr_warn("%s: could not register clock aclk_dmac1: %ld\n",
997
-			__func__, PTR_ERR(clk));
998
-	else
999
-		rockchip_clk_add_lookup(ctx, clk, ACLK_DMAC1);
1000
-
1001
-	/* watchdog pclk is controlled by sgrf. */
1002
-	clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_bus", 0, 1, 1);
1003
-	if (IS_ERR(clk))
1004
-		pr_warn("%s: could not register clock pclk_wdt: %ld\n",
1005
-			__func__, PTR_ERR(clk));
1006
-	else
1007
-		rockchip_clk_add_lookup(ctx, clk, PCLK_WDT);
952
+	clks = ctx->clk_data.clks;
1008953 
1009954 	rockchip_clk_register_plls(ctx, rk3308_pll_clks,
1010955 				   ARRAY_SIZE(rk3308_pll_clks),
....@@ -1018,11 +963,9 @@
1018963 	else
1019964 		rockchip_clk_register_branches(ctx, rk3308_dclk_vop_frac,
1020965 					       ARRAY_SIZE(rk3308_dclk_vop_frac));
1021
-	rockchip_clk_protect_critical(rk3308_critical_clocks,
1022
-				      ARRAY_SIZE(rk3308_critical_clocks));
1023966 
1024967 	rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
1025
-				     mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
968
+				     3, clks[PLL_APLL], clks[PLL_VPLL0],
1026969 				     &rk3308_cpuclk_data, rk3308_cpuclk_rates,
1027970 				     ARRAY_SIZE(rk3308_cpuclk_rates));
1028971 
....@@ -1033,8 +976,38 @@
1033976 
1034977 	rockchip_clk_of_add_provider(np, ctx);
1035978 
1036
-	atomic_notifier_chain_register(&panic_notifier_list,
1037
-				       &rk3308_clk_panic_block);
979
+	if (!rk_dump_cru) {
980
+		rk3308_cru_base = reg_base;
981
+		rk_dump_cru = rk3308_dump_cru;
982
+	}
1038983 }
1039984 
1040985 CLK_OF_DECLARE(rk3308_cru, "rockchip,rk3308-cru", rk3308_clk_init);
986
+
987
+static int __init clk_rk3308_probe(struct platform_device *pdev)
988
+{
989
+	struct device_node *np = pdev->dev.of_node;
990
+
991
+	rk3308_clk_init(np);
992
+
993
+	return 0;
994
+}
995
+
996
+static const struct of_device_id clk_rk3308_match_table[] = {
997
+	{
998
+		.compatible = "rockchip,rk3308-cru",
999
+	},
1000
+	{ }
1001
+};
1002
+MODULE_DEVICE_TABLE(of, clk_rk3308_match_table);
1003
+
1004
+static struct platform_driver clk_rk3308_driver = {
1005
+	.driver		= {
1006
+		.name	= "clk-rk3308",
1007
+		.of_match_table = clk_rk3308_match_table,
1008
+	},
1009
+};
1010
+builtin_platform_driver_probe(clk_rk3308_driver, clk_rk3308_probe);
1011
+
1012
+MODULE_DESCRIPTION("Rockchip RK3308 Clock Driver");
1013
+MODULE_LICENSE("GPL");