forked from ~ljy/RK356X_SDK_RELEASE
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2024-10-09 244b2c5ca8b14627e4a17755e5922221e121c771 
 kernel/drivers/clk/rockchip/clk-rk3228.c
....@@ -1,31 +1,21 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23  * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
34  * Author: Xing Zheng <zhengxing@rock-chips.com>
45  *         Jeffy Chen <jeffy.chen@rock-chips.com>
5
- *
6
- * This program is free software; you can redistribute it and/or modify
7
- * it under the terms of the GNU General Public License as published by
8
- * the Free Software Foundation; either version 2 of the License, or
9
- * (at your option) any later version.
10
- *
11
- * This program is distributed in the hope that it will be useful,
12
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
13
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14
- * GNU General Public License for more details.
156  */
167 
178 #include <linux/clk-provider.h>
9
+#include <linux/io.h>
10
+#include <linux/module.h>
1811 #include <linux/of.h>
1912 #include <linux/of_address.h>
13
+#include <linux/of_device.h>
2014 #include <linux/syscore_ops.h>
2115 #include <dt-bindings/clock/rk3228-cru.h>
2216 #include "clk.h"
2317 
2418 #define RK3228_GRF_SOC_STATUS0	0x480
25
-
26
-#define RK3228_UART_FRAC_MAX_PRATE	600000000
27
-#define RK3228_SPDIF_FRAC_MAX_PRATE	600000000
28
-#define RK3228_I2S_FRAC_MAX_PRATE	600000000
2919 
3020 enum rk3228_plls {
3121 	apll, dpll, cpll, gpll,
....@@ -143,22 +133,23 @@
143133 
144134 PNAME(mux_pll_p)		= { "clk_24m", "xin24m" };
145135 
146
-PNAME(mux_ddrphy_p)		= { "dpll", "gpll", "apll" };
147
-PNAME(mux_armclk_p)		= { "apll_core", "gpll_core", "dpll_core" };
136
+PNAME(mux_ddrphy_p)		= { "dpll_ddr", "gpll_ddr", "apll_ddr" };
148137 PNAME(mux_usb480m_phy_p)	= { "usb480m_phy0", "usb480m_phy1" };
149138 PNAME(mux_usb480m_p)		= { "usb480m_phy", "xin24m" };
150139 PNAME(mux_hdmiphy_p)		= { "hdmiphy_phy", "xin24m" };
140
+PNAME(mux_aclk_cpu_src_p)	= { "cpll_aclk_cpu", "gpll_aclk_cpu", "hdmiphy_aclk_cpu" };
151141 
152142 PNAME(mux_pll_src_4plls_p)	= { "cpll", "gpll", "hdmiphy", "usb480m" };
153143 PNAME(mux_pll_src_3plls_p)	= { "cpll", "gpll", "hdmiphy" };
154144 PNAME(mux_pll_src_2plls_p)	= { "cpll", "gpll" };
155145 PNAME(mux_sclk_hdmi_cec_p)	= { "cpll", "gpll", "xin24m" };
146
+PNAME(mux_aclk_peri_src_p)	= { "cpll_peri", "gpll_peri", "hdmiphy_peri" };
156147 PNAME(mux_mmc_src_p)		= { "cpll", "gpll", "xin24m", "usb480m" };
157148 PNAME(mux_pll_src_cpll_gpll_usb480m_p)	= { "cpll", "gpll", "usb480m" };
158149 
159150 PNAME(mux_sclk_rga_p)		= { "gpll", "cpll", "sclk_rga_src" };
160151 
161
-PNAME(mux_sclk_vop_src_p)	= { "gpll", "cpll" };
152
+PNAME(mux_sclk_vop_src_p)	= { "gpll_vop", "cpll_vop" };
162153 PNAME(mux_dclk_vop_p)		= { "hdmiphy", "sclk_vop_pre" };
163154 
164155 PNAME(mux_i2s0_p)		= { "i2s0_src", "i2s0_frac", "ext_i2s", "xin12m" };
....@@ -183,7 +174,7 @@
183174 	[cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(6),
184175 		     RK2928_MODE_CON, 8, 8, 0, NULL),
185176 	[gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(9),
186
-		     RK2928_MODE_CON, 12, 9, 0, rk3228_pll_rates),
177
+		     RK2928_MODE_CON, 12, 9, ROCKCHIP_PLL_SYNC_RATE, rk3228_pll_rates),
187178 };
188179 
189180 #define MFLAGS CLK_MUX_HIWORD_MASK
....@@ -227,12 +218,19 @@
227218 			RK2928_CLKSEL_CON(4), 8, 5, DFLAGS),
228219 
229220 	/* PD_DDR */
230
-	COMPOSITE_DDRCLK(SCLK_DDRC, "clk_ddrc", mux_ddrphy_p, 0,
231
-			 RK2928_CLKSEL_CON(26), 8, 2, 0, 2,
232
-			 ROCKCHIP_DDRCLK_SIP_V2),
233
-	FACTOR(0, "clk_ddrphy", "clk_ddrc", 0, 1, 4),
234
-	GATE(0, "ddrphy4x", "clk_ddrc", CLK_IGNORE_UNUSED,
221
+	GATE(0, "apll_ddr", "apll", CLK_IGNORE_UNUSED,
222
+			RK2928_CLKGATE_CON(0), 2, GFLAGS),
223
+	GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
224
+			RK2928_CLKGATE_CON(0), 2, GFLAGS),
225
+	GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
226
+			RK2928_CLKGATE_CON(0), 2, GFLAGS),
227
+	COMPOSITE(0, "ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED,
228
+			RK2928_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
235229 			RK2928_CLKGATE_CON(7), 1, GFLAGS),
230
+	GATE(0, "ddrc", "ddrphy_pre", CLK_IGNORE_UNUSED,
231
+			RK2928_CLKGATE_CON(8), 5, GFLAGS),
232
+	FACTOR_GATE(0, "ddrphy", "ddrphy4x", CLK_IGNORE_UNUSED, 1, 4,
233
+			RK2928_CLKGATE_CON(7), 0, GFLAGS),
236234 
237235 	/* PD_CORE */
238236 	GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
....@@ -249,7 +247,7 @@
249247 			RK2928_CLKGATE_CON(4), 0, GFLAGS),
250248 
251249 	/* PD_MISC */
252
-	MUX(HDMIPHY, "hdmiphy", mux_hdmiphy_p, CLK_SET_RATE_PARENT,
250
+	MUX(SCLK_HDMI_PHY, "hdmiphy", mux_hdmiphy_p, CLK_SET_RATE_PARENT,
253251 			RK2928_MISC_CON, 13, 1, MFLAGS),
254252 	MUX(0, "usb480m_phy", mux_usb480m_phy_p, CLK_SET_RATE_PARENT,
255253 			RK2928_MISC_CON, 14, 1, MFLAGS),
....@@ -257,22 +255,27 @@
257255 			RK2928_MISC_CON, 15, 1, MFLAGS),
258256 
259257 	/* PD_BUS */
260
-	COMPOSITE(0, "aclk_cpu_src", mux_pll_src_3plls_p, 0,
261
-			RK2928_CLKSEL_CON(0), 13, 2, MFLAGS, 8, 5, DFLAGS,
258
+	GATE(0, "hdmiphy_aclk_cpu", "hdmiphy", CLK_IS_CRITICAL,
262259 			RK2928_CLKGATE_CON(0), 1, GFLAGS),
263
-	GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_src", 0,
260
+	GATE(0, "gpll_aclk_cpu", "gpll", CLK_IS_CRITICAL,
261
+			RK2928_CLKGATE_CON(0), 1, GFLAGS),
262
+	GATE(0, "cpll_aclk_cpu", "cpll", CLK_IS_CRITICAL,
263
+			RK2928_CLKGATE_CON(0), 1, GFLAGS),
264
+	COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, CLK_IS_CRITICAL,
265
+			RK2928_CLKSEL_CON(0), 13, 2, MFLAGS, 8, 5, DFLAGS),
266
+	GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_src", CLK_IS_CRITICAL,
264267 			RK2928_CLKGATE_CON(6), 0, GFLAGS),
265
-	COMPOSITE_NOMUX(HCLK_CPU, "hclk_cpu", "aclk_cpu_src", 0,
268
+	COMPOSITE_NOMUX(HCLK_CPU, "hclk_cpu", "aclk_cpu_src", CLK_IS_CRITICAL,
266269 			RK2928_CLKSEL_CON(1), 8, 2, DFLAGS,
267270 			RK2928_CLKGATE_CON(6), 1, GFLAGS),
268
-	COMPOSITE_NOMUX(0, "pclk_bus_src", "aclk_cpu_src", 0,
271
+	COMPOSITE_NOMUX(0, "pclk_bus_src", "aclk_cpu_src", CLK_IS_CRITICAL,
269272 			RK2928_CLKSEL_CON(1), 12, 3, DFLAGS,
270273 			RK2928_CLKGATE_CON(6), 2, GFLAGS),
271
-	GATE(PCLK_CPU, "pclk_cpu", "pclk_bus_src", 0,
274
+	GATE(PCLK_CPU, "pclk_cpu", "pclk_bus_src", CLK_IS_CRITICAL,
272275 			RK2928_CLKGATE_CON(6), 3, GFLAGS),
273
-	GATE(0, "pclk_phy_pre", "pclk_bus_src", 0,
276
+	GATE(0, "pclk_phy_pre", "pclk_bus_src", CLK_IS_CRITICAL,
274277 			RK2928_CLKGATE_CON(6), 4, GFLAGS),
275
-	GATE(0, "pclk_ddr_pre", "pclk_bus_src", 0,
278
+	GATE(0, "pclk_ddr_pre", "pclk_bus_src", CLK_IS_CRITICAL,
276279 			RK2928_CLKGATE_CON(6), 13, GFLAGS),
277280 
278281 	/* PD_VIDEO */
....@@ -307,9 +310,9 @@
307310 			RK2928_CLKSEL_CON(31), 13, 2, MFLAGS, 8, 5, DFLAGS,
308311 			RK2928_CLKGATE_CON(1), 4, GFLAGS),
309312 
310
-	MUX(0, "sclk_rga_src", mux_pll_src_4plls_p, 0,
313
+	MUX(0, "sclk_rga_src", mux_pll_src_4plls_p, CLK_IS_CRITICAL,
311314 			RK2928_CLKSEL_CON(33), 13, 2, MFLAGS),
312
-	COMPOSITE_NOMUX(ACLK_RGA_PRE, "aclk_rga_pre", "sclk_rga_src", 0,
315
+	COMPOSITE_NOMUX(ACLK_RGA_PRE, "aclk_rga_pre", "sclk_rga_src", CLK_IS_CRITICAL,
313316 			RK2928_CLKSEL_CON(33), 8, 5, DFLAGS,
314317 			RK2928_CLKGATE_CON(1), 2, GFLAGS),
315318 	COMPOSITE(SCLK_RGA, "sclk_rga", mux_sclk_rga_p, 0,
....@@ -332,16 +335,21 @@
332335 			RK2928_CLKGATE_CON(3), 8, GFLAGS),
333336 
334337 	/* PD_PERI */
335
-	COMPOSITE(0, "aclk_peri_src", mux_pll_src_3plls_p, 0,
336
-			RK2928_CLKSEL_CON(10), 10, 2, MFLAGS, 0, 5, DFLAGS,
338
+	GATE(0, "cpll_peri", "cpll", CLK_IS_CRITICAL,
337339 			RK2928_CLKGATE_CON(2), 0, GFLAGS),
338
-	COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0,
340
+	GATE(0, "gpll_peri", "gpll", CLK_IS_CRITICAL,
341
+			RK2928_CLKGATE_CON(2), 0, GFLAGS),
342
+	GATE(0, "hdmiphy_peri", "hdmiphy", CLK_IS_CRITICAL,
343
+			RK2928_CLKGATE_CON(2), 0, GFLAGS),
344
+	COMPOSITE_NOGATE(0, "aclk_peri_src", mux_aclk_peri_src_p, CLK_IS_CRITICAL,
345
+			RK2928_CLKSEL_CON(10), 10, 2, MFLAGS, 0, 5, DFLAGS),
346
+	COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", CLK_IS_CRITICAL,
339347 			RK2928_CLKSEL_CON(10), 12, 3, DFLAGS,
340348 			RK2928_CLKGATE_CON(5), 2, GFLAGS),
341
-	COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", 0,
349
+	COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", CLK_IS_CRITICAL,
342350 			RK2928_CLKSEL_CON(10), 8, 2, DFLAGS,
343351 			RK2928_CLKGATE_CON(5), 1, GFLAGS),
344
-	GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 0,
352
+	GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", CLK_IS_CRITICAL,
345353 			RK2928_CLKGATE_CON(5), 0, GFLAGS),
346354 
347355 	GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
....@@ -369,7 +377,7 @@
369377 			RK2928_CLKGATE_CON(10), 12, GFLAGS),
370378 
371379 	COMPOSITE(SCLK_WIFI, "sclk_wifi", mux_pll_src_cpll_gpll_usb480m_p, 0,
372
-			RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, 0, 5, DFLAGS,
380
+			RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, 0, 6, DFLAGS,
373381 			RK2928_CLKGATE_CON(2), 15, GFLAGS),
374382 
375383 	COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,
....@@ -392,14 +400,17 @@
392400 	 * Clock-Architecture Diagram 2
393401 	 */
394402 
395
-	COMPOSITE_NODIV(0, "sclk_vop_src", mux_sclk_vop_src_p, 0,
396
-			RK2928_CLKSEL_CON(27), 0, 1, MFLAGS,
403
+	GATE(0, "gpll_vop", "gpll", 0,
397404 			RK2928_CLKGATE_CON(3), 1, GFLAGS),
405
+	GATE(0, "cpll_vop", "cpll", 0,
406
+			RK2928_CLKGATE_CON(3), 1, GFLAGS),
407
+	MUX(0, "sclk_vop_src", mux_sclk_vop_src_p, 0,
408
+			RK2928_CLKSEL_CON(27), 0, 1, MFLAGS),
398409 	DIV(DCLK_HDMI_PHY, "dclk_hdmiphy", "sclk_vop_src", 0,
399410 			RK2928_CLKSEL_CON(29), 0, 3, DFLAGS),
400411 	DIV(0, "sclk_vop_pre", "sclk_vop_src", 0,
401412 			RK2928_CLKSEL_CON(27), 8, 8, DFLAGS),
402
-	MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
413
+	MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, 0,
403414 			RK2928_CLKSEL_CON(27), 1, 1, MFLAGS),
404415 
405416 	FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
....@@ -410,7 +421,7 @@
410421 	COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT,
411422 			RK2928_CLKSEL_CON(8), 0,
412423 			RK2928_CLKGATE_CON(0), 4, GFLAGS,
413
-			&rk3228_i2s0_fracmux, RK3228_I2S_FRAC_MAX_PRATE),
424
+			&rk3228_i2s0_fracmux),
414425 	GATE(SCLK_I2S0, "sclk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT,
415426 			RK2928_CLKGATE_CON(0), 5, GFLAGS),
416427 
....@@ -420,7 +431,7 @@
420431 	COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT,
421432 			RK2928_CLKSEL_CON(7), 0,
422433 			RK2928_CLKGATE_CON(0), 11, GFLAGS,
423
-			&rk3228_i2s1_fracmux, RK3228_I2S_FRAC_MAX_PRATE),
434
+			&rk3228_i2s1_fracmux),
424435 	GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
425436 			RK2928_CLKGATE_CON(0), 14, GFLAGS),
426437 	COMPOSITE_NODIV(SCLK_I2S_OUT, "i2s_out", mux_i2s_out_p, 0,
....@@ -433,7 +444,7 @@
433444 	COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_src", CLK_SET_RATE_PARENT,
434445 			RK2928_CLKSEL_CON(30), 0,
435446 			RK2928_CLKGATE_CON(0), 8, GFLAGS,
436
-			&rk3228_i2s2_fracmux, RK3228_I2S_FRAC_MAX_PRATE),
447
+			&rk3228_i2s2_fracmux),
437448 	GATE(SCLK_I2S2, "sclk_i2s2", "i2s2_pre", CLK_SET_RATE_PARENT,
438449 			RK2928_CLKGATE_CON(0), 9, GFLAGS),
439450 
....@@ -443,7 +454,7 @@
443454 	COMPOSITE_FRACMUX(0, "spdif_frac", "sclk_spdif_src", CLK_SET_RATE_PARENT,
444455 			RK2928_CLKSEL_CON(20), 0,
445456 			RK2928_CLKGATE_CON(2), 12, GFLAGS,
446
-			&rk3228_spdif_fracmux, RK3228_SPDIF_FRAC_MAX_PRATE),
457
+			&rk3228_spdif_fracmux),
447458 
448459 	GATE(0, "jtag", "ext_jtag", CLK_IGNORE_UNUSED,
449460 			RK2928_CLKGATE_CON(1), 3, GFLAGS),
....@@ -478,15 +489,15 @@
478489 	COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
479490 			RK2928_CLKSEL_CON(17), 0,
480491 			RK2928_CLKGATE_CON(1), 9, GFLAGS,
481
-			&rk3228_uart0_fracmux, RK3228_UART_FRAC_MAX_PRATE),
492
+			&rk3228_uart0_fracmux),
482493 	COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
483494 			RK2928_CLKSEL_CON(18), 0,
484495 			RK2928_CLKGATE_CON(1), 11, GFLAGS,
485
-			&rk3228_uart1_fracmux, RK3228_UART_FRAC_MAX_PRATE),
496
+			&rk3228_uart1_fracmux),
486497 	COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
487498 			RK2928_CLKSEL_CON(19), 0,
488499 			RK2928_CLKGATE_CON(1), 13, GFLAGS,
489
-			&rk3228_uart2_fracmux, RK3228_UART_FRAC_MAX_PRATE),
500
+			&rk3228_uart2_fracmux),
490501 
491502 	COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_2plls_p, 0,
492503 			RK2928_CLKSEL_CON(2), 14, 1, MFLAGS, 8, 5, DFLAGS,
....@@ -520,26 +531,26 @@
520531 
521532 	/* PD_VOP */
522533 	GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK2928_CLKGATE_CON(13), 0, GFLAGS),
523
-	GATE(0, "aclk_rga_noc", "aclk_rga_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(13), 11, GFLAGS),
534
+	GATE(0, "aclk_rga_noc", "aclk_rga_pre", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(13), 11, GFLAGS),
524535 	GATE(ACLK_IEP, "aclk_iep", "aclk_iep_pre", 0, RK2928_CLKGATE_CON(13), 2, GFLAGS),
525
-	GATE(0, "aclk_iep_noc", "aclk_iep_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(13), 9, GFLAGS),
536
+	GATE(0, "aclk_iep_noc", "aclk_iep_pre", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(13), 9, GFLAGS),
526537 
527538 	GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 0, RK2928_CLKGATE_CON(13), 5, GFLAGS),
528
-	GATE(0, "aclk_vop_noc", "aclk_vop_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(13), 12, GFLAGS),
539
+	GATE(0, "aclk_vop_noc", "aclk_vop_pre", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(13), 12, GFLAGS),
529540 
530541 	GATE(ACLK_HDCP, "aclk_hdcp", "aclk_hdcp_pre", 0, RK2928_CLKGATE_CON(14), 10, GFLAGS),
531
-	GATE(0, "aclk_hdcp_noc", "aclk_hdcp_pre", 0, RK2928_CLKGATE_CON(13), 10, GFLAGS),
542
+	GATE(0, "aclk_hdcp_noc", "aclk_hdcp_pre", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(13), 10, GFLAGS),
532543 
533544 	GATE(HCLK_RGA, "hclk_rga", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 1, GFLAGS),
534545 	GATE(HCLK_IEP, "hclk_iep", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 3, GFLAGS),
535546 	GATE(HCLK_VOP, "hclk_vop", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 6, GFLAGS),
536
-	GATE(0, "hclk_vio_ahb_arbi", "hclk_vio_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(13), 7, GFLAGS),
537
-	GATE(0, "hclk_vio_noc", "hclk_vio_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(13), 8, GFLAGS),
538
-	GATE(0, "hclk_vop_noc", "hclk_vio_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(13), 13, GFLAGS),
539
-	GATE(HCLK_VIO_H2P, "hclk_vio_h2p", "hclk_vio_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(14), 7, GFLAGS),
547
+	GATE(0, "hclk_vio_ahb_arbi", "hclk_vio_pre", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(13), 7, GFLAGS),
548
+	GATE(0, "hclk_vio_noc", "hclk_vio_pre", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(13), 8, GFLAGS),
549
+	GATE(0, "hclk_vop_noc", "hclk_vio_pre", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(13), 13, GFLAGS),
550
+	GATE(HCLK_VIO_H2P, "hclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 7, GFLAGS),
540551 	GATE(HCLK_HDCP_MMU, "hclk_hdcp_mmu", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 12, GFLAGS),
541552 	GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 6, GFLAGS),
542
-	GATE(PCLK_VIO_H2P, "pclk_vio_h2p", "hclk_vio_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(14), 8, GFLAGS),
553
+	GATE(PCLK_VIO_H2P, "pclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 8, GFLAGS),
543554 	GATE(PCLK_HDCP, "pclk_hdcp", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 11, GFLAGS),
544555 
545556 	/* PD_PERI */
....@@ -551,29 +562,29 @@
551562 	GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 2, GFLAGS),
552563 	GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 3, GFLAGS),
553564 	GATE(HCLK_HOST0, "hclk_host0", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 6, GFLAGS),
554
-	GATE(0, "hclk_host0_arb", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(11), 7, GFLAGS),
565
+	GATE(0, "hclk_host0_arb", "hclk_peri", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(11), 7, GFLAGS),
555566 	GATE(HCLK_HOST1, "hclk_host1", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 8, GFLAGS),
556
-	GATE(0, "hclk_host1_arb", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(11), 9, GFLAGS),
567
+	GATE(0, "hclk_host1_arb", "hclk_peri", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(11), 9, GFLAGS),
557568 	GATE(HCLK_HOST2, "hclk_host2", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 10, GFLAGS),
558569 	GATE(HCLK_OTG, "hclk_otg", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 12, GFLAGS),
559
-	GATE(0, "hclk_otg_pmu", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(11), 13, GFLAGS),
560
-	GATE(0, "hclk_host2_arb", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(11), 14, GFLAGS),
570
+	GATE(0, "hclk_otg_pmu", "hclk_peri", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(11), 13, GFLAGS),
571
+	GATE(0, "hclk_host2_arb", "hclk_peri", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(11), 14, GFLAGS),
561572 	GATE(0, "hclk_peri_noc", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 1, GFLAGS),
562573 
563574 	GATE(PCLK_GMAC, "pclk_gmac", "pclk_peri", 0, RK2928_CLKGATE_CON(11), 5, GFLAGS),
564
-	GATE(0, "pclk_peri_noc", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 2, GFLAGS),
575
+	GATE(0, "pclk_peri_noc", "pclk_peri", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(12), 2, GFLAGS),
565576 
566577 	/* PD_GPU */
567578 	GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(7), 14, GFLAGS),
568
-	GATE(0, "aclk_gpu_noc", "aclk_gpu_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(7), 15, GFLAGS),
579
+	GATE(0, "aclk_gpu_noc", "aclk_gpu_pre", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(7), 15, GFLAGS),
569580 
570581 	/* PD_BUS */
571
-	GATE(0, "sclk_initmem_mbist", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(8), 1, GFLAGS),
572
-	GATE(0, "aclk_initmem", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(8), 0, GFLAGS),
582
+	GATE(0, "sclk_initmem_mbist", "aclk_cpu", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(8), 1, GFLAGS),
583
+	GATE(0, "aclk_initmem", "aclk_cpu", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(8), 0, GFLAGS),
573584 	GATE(ACLK_DMAC, "aclk_dmac_bus", "aclk_cpu", 0, RK2928_CLKGATE_CON(8), 2, GFLAGS),
574585 	GATE(0, "aclk_bus_noc", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 1, GFLAGS),
575586 
576
-	GATE(0, "hclk_rom", "hclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(8), 3, GFLAGS),
587
+	GATE(0, "hclk_rom", "hclk_cpu", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(8), 3, GFLAGS),
577588 	GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 7, GFLAGS),
578589 	GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 8, GFLAGS),
579590 	GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS),
....@@ -582,9 +593,9 @@
582593 	GATE(HCLK_M_CRYPTO, "hclk_crypto_mst", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS),
583594 	GATE(HCLK_S_CRYPTO, "hclk_crypto_slv", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 12, GFLAGS),
584595 
585
-	GATE(0, "pclk_ddrupctl", "pclk_ddr_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(8), 4, GFLAGS),
586
-	GATE(0, "pclk_ddrmon", "pclk_ddr_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(8), 6, GFLAGS),
587
-	GATE(0, "pclk_msch_noc", "pclk_ddr_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 2, GFLAGS),
596
+	GATE(0, "pclk_ddrupctl", "pclk_ddr_pre", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(8), 4, GFLAGS),
597
+	GATE(0, "pclk_ddrmon", "pclk_ddr_pre", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(8), 6, GFLAGS),
598
+	GATE(0, "pclk_msch_noc", "pclk_ddr_pre", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(10), 2, GFLAGS),
588599 
589600 	GATE(PCLK_EFUSE_1024, "pclk_efuse_1024", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS),
590601 	GATE(PCLK_EFUSE_256, "pclk_efuse_256", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 14, GFLAGS),
....@@ -593,7 +604,7 @@
593604 	GATE(PCLK_I2C2, "pclk_i2c2", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 1, GFLAGS),
594605 	GATE(PCLK_I2C3, "pclk_i2c3", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 2, GFLAGS),
595606 	GATE(PCLK_TIMER, "pclk_timer0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 4, GFLAGS),
596
-	GATE(0, "pclk_stimer", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 5, GFLAGS),
607
+	GATE(0, "pclk_stimer", "pclk_cpu", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(9), 5, GFLAGS),
597608 	GATE(PCLK_SPI0, "pclk_spi0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS),
598609 	GATE(PCLK_PWM, "pclk_rk_pwm", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 7, GFLAGS),
599610 	GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 8, GFLAGS),
....@@ -609,20 +620,20 @@
609620 	GATE(0, "pclk_sgrf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 2, GFLAGS),
610621 	GATE(0, "pclk_sim", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 3, GFLAGS),
611622 
612
-	GATE(0, "pclk_ddrphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 3, GFLAGS),
613
-	GATE(PCLK_ACODECPHY, "pclk_acodecphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 5, GFLAGS),
623
+	GATE(0, "pclk_ddrphy", "pclk_phy_pre", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(10), 3, GFLAGS),
624
+	GATE(0, "pclk_acodecphy", "pclk_phy_pre", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(10), 5, GFLAGS),
614625 	GATE(PCLK_HDMI_PHY, "pclk_hdmiphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 7, GFLAGS),
615626 	GATE(0, "pclk_vdacphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 8, GFLAGS),
616
-	GATE(0, "pclk_phy_noc", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 9, GFLAGS),
627
+	GATE(0, "pclk_phy_noc", "pclk_phy_pre", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(10), 9, GFLAGS),
617628 
618629 	GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 0, GFLAGS),
619
-	GATE(0, "aclk_vpu_noc", "aclk_vpu_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(15), 4, GFLAGS),
630
+	GATE(0, "aclk_vpu_noc", "aclk_vpu_pre", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(15), 4, GFLAGS),
620631 	GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 2, GFLAGS),
621
-	GATE(0, "aclk_rkvdec_noc", "aclk_rkvdec_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(15), 6, GFLAGS),
632
+	GATE(0, "aclk_rkvdec_noc", "aclk_rkvdec_pre", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(15), 6, GFLAGS),
622633 	GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 1, GFLAGS),
623
-	GATE(0, "hclk_vpu_noc", "hclk_vpu_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(15), 5, GFLAGS),
634
+	GATE(0, "hclk_vpu_noc", "hclk_vpu_pre", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(15), 5, GFLAGS),
624635 	GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 3, GFLAGS),
625
-	GATE(0, "hclk_rkvdec_noc", "hclk_rkvdec_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(15), 7, GFLAGS),
636
+	GATE(0, "hclk_rkvdec_noc", "hclk_rkvdec_pre", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(15), 7, GFLAGS),
626637 
627638 	/* PD_MMC */
628639 	MMC(SCLK_SDMMC_DRV,    "sdmmc_drv",    "sclk_sdmmc", RK3228_SDMMC_CON0, 1),
....@@ -633,43 +644,6 @@
633644 
634645 	MMC(SCLK_EMMC_DRV,     "emmc_drv",     "sclk_emmc",  RK3228_EMMC_CON0,  1),
635646 	MMC(SCLK_EMMC_SAMPLE,  "emmc_sample",  "sclk_emmc",  RK3228_EMMC_CON1,  1),
636
-};
637
-
638
-static const char *const rk3228_critical_clocks[] __initconst = {
639
-	"aclk_cpu",
640
-	"pclk_cpu",
641
-	"hclk_cpu",
642
-	"aclk_peri",
643
-	"hclk_peri",
644
-	"pclk_peri",
645
-	"aclk_rga_noc",
646
-	"aclk_iep_noc",
647
-	"aclk_vop_noc",
648
-	"aclk_hdcp_noc",
649
-	"hclk_vio_ahb_arbi",
650
-	"hclk_vio_noc",
651
-	"hclk_vop_noc",
652
-	"hclk_host0_arb",
653
-	"hclk_host1_arb",
654
-	"hclk_host2_arb",
655
-	"hclk_otg_pmu",
656
-	"aclk_gpu_noc",
657
-	"sclk_initmem_mbist",
658
-	"aclk_initmem",
659
-	"hclk_rom",
660
-	"pclk_ddrupctl",
661
-	"pclk_ddrmon",
662
-	"pclk_msch_noc",
663
-	"pclk_stimer",
664
-	"pclk_ddrphy",
665
-	"pclk_acodecphy",
666
-	"pclk_phy_noc",
667
-	"aclk_vpu_noc",
668
-	"aclk_rkvdec_noc",
669
-	"aclk_rkvdec",
670
-	"hclk_vpu_noc",
671
-	"hclk_rkvdec_noc",
672
-	"hclk_rkvdec",
673647 };
674648 
675649 static void __iomem *rk3228_cru_base;
....@@ -688,6 +662,7 @@
688662 {
689663 	struct rockchip_clk_provider *ctx;
690664 	void __iomem *reg_base;
665
+	struct clk **clks;
691666 
692667 	reg_base = of_iomap(np, 0);
693668 	if (!reg_base) {
....@@ -701,17 +676,16 @@
701676 		iounmap(reg_base);
702677 		return;
703678 	}
679
+	clks = ctx->clk_data.clks;
704680 
705681 	rockchip_clk_register_plls(ctx, rk3228_pll_clks,
706682 				   ARRAY_SIZE(rk3228_pll_clks),
707683 				   RK3228_GRF_SOC_STATUS0);
708684 	rockchip_clk_register_branches(ctx, rk3228_clk_branches,
709685 				  ARRAY_SIZE(rk3228_clk_branches));
710
-	rockchip_clk_protect_critical(rk3228_critical_clocks,
711
-				      ARRAY_SIZE(rk3228_critical_clocks));
712686 
713687 	rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
714
-			mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
688
+			3, clks[PLL_APLL], clks[PLL_GPLL],
715689 			&rk3228_cpuclk_data, rk3228_cpuclk_rates,
716690 			ARRAY_SIZE(rk3228_cpuclk_rates));
717691 
....@@ -728,3 +702,31 @@
728702 	}
729703 }
730704 CLK_OF_DECLARE(rk3228_cru, "rockchip,rk3228-cru", rk3228_clk_init);
705
+
706
+static int __init clk_rk3228_probe(struct platform_device *pdev)
707
+{
708
+	struct device_node *np = pdev->dev.of_node;
709
+
710
+	rk3228_clk_init(np);
711
+
712
+	return 0;
713
+}
714
+
715
+static const struct of_device_id clk_rk3228_match_table[] = {
716
+	{
717
+		.compatible = "rockchip,rk3228-cru",
718
+	},
719
+	{ }
720
+};
721
+MODULE_DEVICE_TABLE(of, clk_rk3228_match_table);
722
+
723
+static struct platform_driver clk_rk3228_driver = {
724
+	.driver		= {
725
+		.name	= "clk-rk3228",
726
+		.of_match_table = clk_rk3228_match_table,
727
+	},
728
+};
729
+builtin_platform_driver_probe(clk_rk3228_driver, clk_rk3228_probe);
730
+
731
+MODULE_DESCRIPTION("Rockchip RK3228 Clock Driver");
732
+MODULE_LICENSE("GPL");