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2024-10-09 244b2c5ca8b14627e4a17755e5922221e121c771 
 kernel/drivers/clk/rockchip/clk-rk3128.c
....@@ -1,30 +1,21 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23  * Copyright (c) 2017 Rockchip Electronics Co. Ltd.
34  * Author: Elaine <zhangqing@rock-chips.com>
4
- *
5
- * This program is free software; you can redistribute it and/or modify
6
- * it under the terms of the GNU General Public License as published by
7
- * the Free Software Foundation; either version 2 of the License, or
8
- * (at your option) any later version.
9
- *
10
- * This program is distributed in the hope that it will be useful,
11
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
12
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13
- * GNU General Public License for more details.
145  */
156 
167 #include <linux/clk-provider.h>
8
+#include <linux/io.h>
9
+#include <linux/module.h>
1710 #include <linux/of.h>
1811 #include <linux/of_address.h>
12
+#include <linux/of_device.h>
1913 #include <linux/rockchip/cpu.h>
2014 #include <linux/syscore_ops.h>
2115 #include <dt-bindings/clock/rk3128-cru.h>
2216 #include "clk.h"
2317 
2418 #define RK3128_GRF_SOC_STATUS0	0x14c
25
-#define RK3128_UART_FRAC_MAX_PRATE	600000000
26
-#define RK3128_I2S_FRAC_MAX_PRATE	600000000
27
-#define RK3128_SPDIF_FRAC_MAX_PRATE	600000000
2819 
2920 enum rk3128_plls {
3021 	apll, dpll, cpll, gpll,
....@@ -142,7 +133,6 @@
142133 PNAME(mux_pll_p)		= { "clk_24m", "xin24m" };
143134 
144135 PNAME(mux_ddrphy_p)		= { "dpll_ddr", "gpll_div2_ddr" };
145
-PNAME(mux_armclk_p)		= { "apll_core", "gpll_div2_core" };
146136 PNAME(mux_usb480m_p)		= { "usb480m_phy", "xin24m" };
147137 PNAME(mux_aclk_cpu_src_p)	= { "cpll", "gpll", "gpll_div2", "gpll_div3" };
148138 
....@@ -244,15 +234,15 @@
244234 			RK2928_MISC_CON, 15, 1, MFLAGS),
245235 
246236 	/* PD_CPU */
247
-	COMPOSITE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, 0,
237
+	COMPOSITE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, CLK_IS_CRITICAL,
248238 			RK2928_CLKSEL_CON(0), 13, 2, MFLAGS, 8, 5, DFLAGS,
249239 			RK2928_CLKGATE_CON(0), 1, GFLAGS),
250
-	GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_src", 0,
240
+	GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_src", CLK_IS_CRITICAL,
251241 			RK2928_CLKGATE_CON(0), 3, GFLAGS),
252
-	COMPOSITE_NOMUX(HCLK_CPU, "hclk_cpu", "aclk_cpu_src", 0,
242
+	COMPOSITE_NOMUX(HCLK_CPU, "hclk_cpu", "aclk_cpu_src", CLK_IS_CRITICAL,
253243 			RK2928_CLKSEL_CON(1), 8, 2, DFLAGS,
254244 			RK2928_CLKGATE_CON(0), 4, GFLAGS),
255
-	COMPOSITE_NOMUX(PCLK_CPU, "pclk_cpu", "aclk_cpu_src", 0,
245
+	COMPOSITE_NOMUX(PCLK_CPU, "pclk_cpu", "aclk_cpu_src", CLK_IS_CRITICAL,
256246 			RK2928_CLKSEL_CON(1), 12, 2, DFLAGS,
257247 			RK2928_CLKGATE_CON(0), 5, GFLAGS),
258248 	COMPOSITE_NOMUX(SCLK_CRYPTO, "clk_crypto", "aclk_cpu_src", 0,
....@@ -276,13 +266,13 @@
276266 			RK2928_CLKGATE_CON(3), 10, GFLAGS),
277267 
278268 	/* PD_VIO */
279
-	COMPOSITE(ACLK_VIO0, "aclk_vio0", mux_pll_src_5plls_p, 0,
269
+	COMPOSITE(ACLK_VIO0, "aclk_vio0", mux_pll_src_5plls_p, CLK_IS_CRITICAL,
280270 			RK2928_CLKSEL_CON(31), 5, 3, MFLAGS, 0, 5, DFLAGS,
281271 			RK2928_CLKGATE_CON(3), 0, GFLAGS),
282272 	COMPOSITE(ACLK_VIO1, "aclk_vio1", mux_pll_src_5plls_p, 0,
283273 			RK2928_CLKSEL_CON(31), 13, 3, MFLAGS, 8, 5, DFLAGS,
284274 			RK2928_CLKGATE_CON(1), 4, GFLAGS),
285
-	FACTOR_GATE(HCLK_VIO, "hclk_vio", "aclk_vio0", 0, 1, 4,
275
+	FACTOR_GATE(HCLK_VIO, "hclk_vio", "aclk_vio0", CLK_IS_CRITICAL, 1, 4,
286276 			RK2928_CLKGATE_CON(0), 11, GFLAGS),
287277 
288278 	/* PD_PERI */
....@@ -290,13 +280,13 @@
290280 			RK2928_CLKSEL_CON(10), 14, 2, MFLAGS, 0, 5, DFLAGS,
291281 			RK2928_CLKGATE_CON(2), 0, GFLAGS),
292282 
293
-	COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0,
283
+	COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", CLK_IS_CRITICAL,
294284 			RK2928_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
295285 			RK2928_CLKGATE_CON(2), 3, GFLAGS),
296
-	COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", 0,
286
+	COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", CLK_IS_CRITICAL,
297287 			RK2928_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
298288 			RK2928_CLKGATE_CON(2), 2, GFLAGS),
299
-	GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 0,
289
+	GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", CLK_IS_CRITICAL,
300290 			RK2928_CLKGATE_CON(2), 1, GFLAGS),
301291 
302292 	GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
....@@ -309,7 +299,7 @@
309299 			RK2928_CLKGATE_CON(10), 6, GFLAGS),
310300 	GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
311301 			RK2928_CLKGATE_CON(10), 7, GFLAGS),
312
-	GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
302
+	GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", CLK_IS_CRITICAL,
313303 			RK2928_CLKGATE_CON(10), 8, GFLAGS),
314304 
315305 	GATE(SCLK_PVTM_CORE, "clk_pvtm_core", "xin24m", 0,
....@@ -321,7 +311,7 @@
321311 	GATE(SCLK_MIPI_24M, "clk_mipi_24m", "xin24m", 0,
322312 			RK2928_CLKGATE_CON(2), 15, GFLAGS),
323313 
324
-	COMPOSITE(SCLK_SDMMC, "sclk_sdmmc0", mux_mmc_src_p, 0,
314
+	COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,
325315 			RK2928_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 6, DFLAGS,
326316 			RK2928_CLKGATE_CON(2), 11, GFLAGS),
327317 
....@@ -365,7 +355,7 @@
365355 	COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT,
366356 			RK2928_CLKSEL_CON(8), 0,
367357 			RK2928_CLKGATE_CON(4), 5, GFLAGS,
368
-			&rk3128_i2s0_fracmux, RK3128_I2S_FRAC_MAX_PRATE),
358
+			&rk3128_i2s0_fracmux),
369359 	GATE(SCLK_I2S0, "sclk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT,
370360 			RK2928_CLKGATE_CON(4), 6, GFLAGS),
371361 
....@@ -375,7 +365,7 @@
375365 	COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT,
376366 			RK2928_CLKSEL_CON(7), 0,
377367 			RK2928_CLKGATE_CON(0), 10, GFLAGS,
378
-			&rk3128_i2s1_fracmux, RK3128_I2S_FRAC_MAX_PRATE),
368
+			&rk3128_i2s1_fracmux),
379369 	GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
380370 			RK2928_CLKGATE_CON(0), 14, GFLAGS),
381371 	COMPOSITE_NODIV(SCLK_I2S_OUT, "i2s_out", mux_i2s_out_p, 0,
....@@ -388,7 +378,7 @@
388378 	COMPOSITE_FRACMUX(0, "spdif_frac", "sclk_spdif_src", CLK_SET_RATE_PARENT,
389379 			RK2928_CLKSEL_CON(20), 0,
390380 			RK2928_CLKGATE_CON(2), 12, GFLAGS,
391
-			&rk3128_spdif_fracmux, RK3128_SPDIF_FRAC_MAX_PRATE),
381
+			&rk3128_spdif_fracmux),
392382 
393383 	GATE(0, "jtag", "ext_jtag", CLK_IGNORE_UNUSED,
394384 			RK2928_CLKGATE_CON(1), 3, GFLAGS),
....@@ -425,15 +415,15 @@
425415 	COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
426416 			RK2928_CLKSEL_CON(17), 0,
427417 			RK2928_CLKGATE_CON(1), 9, GFLAGS,
428
-			&rk3128_uart0_fracmux, RK3128_UART_FRAC_MAX_PRATE),
418
+			&rk3128_uart0_fracmux),
429419 	COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
430420 			RK2928_CLKSEL_CON(18), 0,
431421 			RK2928_CLKGATE_CON(1), 11, GFLAGS,
432
-			&rk3128_uart1_fracmux, RK3128_UART_FRAC_MAX_PRATE),
422
+			&rk3128_uart1_fracmux),
433423 	COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
434424 			RK2928_CLKSEL_CON(19), 0,
435425 			RK2928_CLKGATE_CON(1), 13, GFLAGS,
436
-			&rk3128_uart2_fracmux, RK3128_UART_FRAC_MAX_PRATE),
426
+			&rk3128_uart2_fracmux),
437427 
438428 	COMPOSITE(SCLK_MAC_SRC, "sclk_gmac_src", mux_pll_src_3plls_p, 0,
439429 			RK2928_CLKSEL_CON(5), 6, 2, MFLAGS, 0, 5, DFLAGS,
....@@ -459,7 +449,7 @@
459449 			RK2928_CLKSEL_CON(2), 14, 2, MFLAGS, 8, 5, DFLAGS,
460450 			RK2928_CLKGATE_CON(10), 15, GFLAGS),
461451 
462
-	COMPOSITE_NOMUX(PCLK_PMU_PRE, "pclk_pmu_pre", "cpll", 0,
452
+	COMPOSITE_NOMUX(PCLK_PMU_PRE, "pclk_pmu_pre", "cpll", CLK_IS_CRITICAL,
463453 			RK2928_CLKSEL_CON(29), 8, 6, DFLAGS,
464454 			RK2928_CLKGATE_CON(1), 0, GFLAGS),
465455 
....@@ -476,12 +466,12 @@
476466 	GATE(ACLK_IEP, "aclk_iep", "aclk_vio1", 0, RK2928_CLKGATE_CON(9), 8, GFLAGS),
477467 	GATE(0, "aclk_vio1_niu", "aclk_vio1", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 10, GFLAGS),
478468 
479
-	GATE(HCLK_VIO_H2P, "hclk_vio_h2p", "hclk_vio", 0, RK2928_CLKGATE_CON(9), 5, GFLAGS),
469
+	GATE(HCLK_VIO_H2P, "hclk_vio_h2p", "hclk_vio", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(9), 5, GFLAGS),
480470 	GATE(PCLK_MIPI, "pclk_mipi", "hclk_vio", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS),
481471 	GATE(HCLK_RGA, "hclk_rga", "hclk_vio", 0, RK2928_CLKGATE_CON(6), 10, GFLAGS),
482472 	GATE(HCLK_LCDC0, "hclk_lcdc0", "hclk_vio", 0, RK2928_CLKGATE_CON(6), 1, GFLAGS),
483473 	GATE(HCLK_IEP, "hclk_iep", "hclk_vio", 0, RK2928_CLKGATE_CON(9), 7, GFLAGS),
484
-	GATE(0, "hclk_vio_niu", "hclk_vio", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(6), 12, GFLAGS),
474
+	GATE(0, "hclk_vio_niu", "hclk_vio", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(6), 12, GFLAGS),
485475 	GATE(HCLK_CIF, "hclk_cif", "hclk_vio", 0, RK2928_CLKGATE_CON(6), 4, GFLAGS),
486476 	GATE(HCLK_EBC, "hclk_ebc", "hclk_vio", 0, RK2928_CLKGATE_CON(9), 9, GFLAGS),
487477 
....@@ -542,8 +532,8 @@
542532 	GATE(0, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 4, GFLAGS),
543533 	GATE(PCLK_MIPIPHY, "pclk_mipiphy", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 0, GFLAGS),
544534 
545
-	GATE(0, "pclk_pmu", "pclk_pmu_pre", 0, RK2928_CLKGATE_CON(9), 2, GFLAGS),
546
-	GATE(0, "pclk_pmu_niu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 3, GFLAGS),
535
+	GATE(0, "pclk_pmu", "pclk_pmu_pre", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(9), 2, GFLAGS),
536
+	GATE(0, "pclk_pmu_niu", "pclk_pmu_pre", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(9), 3, GFLAGS),
547537 
548538 	/* PD_MMC */
549539 	MMC(SCLK_SDMMC_DRV,    "sdmmc_drv",    "sclk_sdmmc", RK3228_SDMMC_CON0, 1),
....@@ -571,19 +561,6 @@
571561 	GATE(PCLK_HDMI, "pclk_hdmi", "pclk_cpu", 0, RK2928_CLKGATE_CON(3), 8, GFLAGS),
572562 };
573563 
574
-static const char *const rk3128_critical_clocks[] __initconst = {
575
-	"aclk_cpu",
576
-	"hclk_cpu",
577
-	"pclk_cpu",
578
-	"aclk_peri",
579
-	"hclk_peri",
580
-	"pclk_peri",
581
-	"pclk_pmu",
582
-	"sclk_timer5",
583
-	"hclk_vio_niu",
584
-	"hclk_vio_h2p",
585
-};
586
-
587564 static void __iomem *rk312x_reg_base;
588565 
589566 void rkclk_cpuclk_div_setting(int div)
....@@ -607,6 +584,7 @@
607584 {
608585 	struct rockchip_clk_provider *ctx;
609586 	void __iomem *reg_base;
587
+	struct clk **clks;
610588 
611589 	reg_base = of_iomap(np, 0);
612590 	if (!reg_base) {
....@@ -621,6 +599,7 @@
621599 		iounmap(reg_base);
622600 		return ERR_PTR(-ENOMEM);
623601 	}
602
+	clks = ctx->clk_data.clks;
624603 
625604 	rockchip_clk_register_plls(ctx, rk3128_pll_clks,
626605 				   ARRAY_SIZE(rk3128_pll_clks),
....@@ -629,7 +608,7 @@
629608 				  ARRAY_SIZE(common_clk_branches));
630609 
631610 	rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
632
-			mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
611
+			2, clks[PLL_APLL], clks[PLL_GPLL_DIV2],
633612 			&rk3128_cpuclk_data, rk3128_cpuclk_rates,
634613 			ARRAY_SIZE(rk3128_cpuclk_rates));
635614 
....@@ -654,8 +633,6 @@
654633 
655634 	rockchip_clk_register_branches(ctx, rk3126_clk_branches,
656635 				       ARRAY_SIZE(rk3126_clk_branches));
657
-	rockchip_clk_protect_critical(rk3128_critical_clocks,
658
-				      ARRAY_SIZE(rk3128_critical_clocks));
659636 
660637 	rockchip_clk_of_add_provider(np, ctx);
661638 }
....@@ -672,10 +649,60 @@
672649 
673650 	rockchip_clk_register_branches(ctx, rk3128_clk_branches,
674651 				       ARRAY_SIZE(rk3128_clk_branches));
675
-	rockchip_clk_protect_critical(rk3128_critical_clocks,
676
-				      ARRAY_SIZE(rk3128_critical_clocks));
677652 
678653 	rockchip_clk_of_add_provider(np, ctx);
679654 }
680655 
681656 CLK_OF_DECLARE(rk3128_cru, "rockchip,rk3128-cru", rk3128_clk_init);
657
+
658
+struct clk_rk3128_inits {
659
+	void (*inits)(struct device_node *np);
660
+};
661
+
662
+static const struct clk_rk3128_inits clk_rk3126_init = {
663
+	.inits = rk3126_clk_init,
664
+};
665
+
666
+static const struct clk_rk3128_inits clk_rk3128_init = {
667
+	.inits = rk3128_clk_init,
668
+};
669
+
670
+static const struct of_device_id clk_rk3128_match_table[] = {
671
+	{
672
+		.compatible = "rockchip,rk3126-cru",
673
+		.data = &clk_rk3126_init,
674
+	}, {
675
+		.compatible = "rockchip,rk3128-cru",
676
+		.data = &clk_rk3128_init,
677
+	},
678
+	{ }
679
+};
680
+MODULE_DEVICE_TABLE(of, clk_rk3128_match_table);
681
+
682
+static int __init clk_rk3128_probe(struct platform_device *pdev)
683
+{
684
+	struct device_node *np = pdev->dev.of_node;
685
+	const struct of_device_id *match;
686
+	const struct clk_rk3128_inits *init_data;
687
+
688
+	match = of_match_device(clk_rk3128_match_table, &pdev->dev);
689
+	if (!match || !match->data)
690
+		return -EINVAL;
691
+
692
+	init_data = match->data;
693
+	if (init_data->inits)
694
+		init_data->inits(np);
695
+
696
+	return 0;
697
+}
698
+
699
+static struct platform_driver clk_rk3128_driver = {
700
+	.driver		= {
701
+		.name	= "clk-rk3128",
702
+		.of_match_table = clk_rk3128_match_table,
703
+	},
704
+};
705
+builtin_platform_driver_probe(clk_rk3128_driver, clk_rk3128_probe);
706
+
707
+MODULE_DESCRIPTION("Rockchip RK3128 Clock Driver");
708
+MODULE_LICENSE("GPL");