forked from ~ljy/RK356X_SDK_RELEASE
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2024-10-09 244b2c5ca8b14627e4a17755e5922221e121c771 
 kernel/drivers/clk/rockchip/clk-px30.c
....@@ -1,28 +1,21 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23  * Copyright (c) 2018 Rockchip Electronics Co. Ltd.
34  * Author: Elaine Zhang<zhangqing@rock-chips.com>
4
- *
5
- * This program is free software; you can redistribute it and/or modify
6
- * it under the terms of the GNU General Public License as published by
7
- * the Free Software Foundation; either version 2 of the License, or
8
- * (at your option) any later version.
9
- *
10
- * This program is distributed in the hope that it will be useful,
11
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
12
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13
- * GNU General Public License for more details.
145  */
156 
167 #include <linux/clk-provider.h>
8
+#include <linux/io.h>
9
+#include <linux/module.h>
1710 #include <linux/of.h>
1811 #include <linux/of_address.h>
12
+#include <linux/of_device.h>
1913 #include <linux/rockchip/cpu.h>
2014 #include <linux/syscore_ops.h>
2115 #include <dt-bindings/clock/px30-cru.h>
2216 #include "clk.h"
2317 
2418 #define PX30_GRF_SOC_STATUS0		0x480
25
-#define PX30_FRAC_MAX_PRATE		600000000
2619 
2720 enum px30_plls {
2821 	apll, dpll, cpll, npll, apll_b_h, apll_b_l,
....@@ -147,7 +140,6 @@
147140 
148141 PNAME(mux_pll_p)		= { "xin24m"};
149142 PNAME(mux_usb480m_p)		= { "xin24m", "usb480m_phy", "clk_rtc32k_pmu" };
150
-PNAME(mux_armclk_p)		= { "apll_core", "gpll_core" };
151143 PNAME(mux_ddrphy_p)		= { "dpll_ddr", "gpll_ddr" };
152144 PNAME(mux_ddrstdby_p)		= { "clk_ddrphy1x", "clk_stdby_2wrap" };
153145 PNAME(mux_gpll_dmycpll_usb480m_npll_p)		= { "gpll", "dummy_cpll", "usb480m", "npll" };
....@@ -205,7 +197,7 @@
205197 		     0, PX30_PLL_CON(16),
206198 		     PX30_MODE_CON, 2, 2, 0, px30_pll_rates),
207199 	[npll] = PLL(pll_rk3328, PLL_NPLL, "npll", mux_pll_p,
208
-		     0, PX30_PLL_CON(24),
200
+		     CLK_IS_CRITICAL, PX30_PLL_CON(24),
209201 		     PX30_MODE_CON, 6, 4, 0, px30_pll_rates),
210202 };
211203 
....@@ -267,7 +259,7 @@
267259 			PX30_CLKSEL_CON(8), 14, 2, MFLAGS);
268260 
269261 static struct rockchip_clk_branch px30_rtc32k_pmu_fracmux __initdata =
270
-	MUX(SCLK_RTC32K_PMU, "clk_rtc32k_pmu", mux_rtc32k_pmu_p, CLK_SET_RATE_PARENT,
262
+	MUX(SCLK_RTC32K_PMU, "clk_rtc32k_pmu", mux_rtc32k_pmu_p, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
271263 			PX30_PMU_CLKSEL_CON(0), 14, 2, MFLAGS);
272264 
273265 static struct rockchip_clk_branch px30_uart0_pmu_fracmux __initdata =
....@@ -320,7 +312,7 @@
320312 	COMPOSITE_NOMUX(0, "aclk_gpu", "clk_gpu", CLK_IGNORE_UNUSED,
321313 			PX30_CLKSEL_CON(1), 13, 2, DFLAGS,
322314 			PX30_CLKGATE_CON(17), 10, GFLAGS),
323
-	GATE(0, "aclk_gpu_niu", "aclk_gpu", CLK_IGNORE_UNUSED,
315
+	GATE(0, "aclk_gpu_niu", "aclk_gpu", CLK_IS_CRITICAL,
324316 			PX30_CLKGATE_CON(0), 11, GFLAGS),
325317 	GATE(0, "aclk_gpu_prf", "aclk_gpu", CLK_IGNORE_UNUSED,
326318 			PX30_CLKGATE_CON(17), 8, GFLAGS),
....@@ -423,7 +415,7 @@
423415 	COMPOSITE_FRACMUX(0, "dclk_vopb_frac", "dclk_vopb_src", CLK_SET_RATE_PARENT,
424416 			PX30_CLKSEL_CON(6), 0,
425417 			PX30_CLKGATE_CON(2), 3, GFLAGS,
426
-			&px30_dclk_vopb_fracmux, 0),
418
+			&px30_dclk_vopb_fracmux),
427419 	GATE(DCLK_VOPB, "dclk_vopb", "dclk_vopb_mux", CLK_SET_RATE_PARENT,
428420 			PX30_CLKGATE_CON(2), 4, GFLAGS),
429421 	COMPOSITE(0, "dclk_vopl_src", mux_npll_cpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
....@@ -432,7 +424,7 @@
432424 	COMPOSITE_FRACMUX(0, "dclk_vopl_frac", "dclk_vopl_src", CLK_SET_RATE_PARENT,
433425 			PX30_CLKSEL_CON(9), 0,
434426 			PX30_CLKGATE_CON(2), 7, GFLAGS,
435
-			&px30_dclk_vopl_fracmux, 0),
427
+			&px30_dclk_vopl_fracmux),
436428 	GATE(DCLK_VOPL, "dclk_vopl", "dclk_vopl_mux", CLK_SET_RATE_PARENT,
437429 			PX30_CLKGATE_CON(2), 8, GFLAGS),
438430 
....@@ -451,13 +443,13 @@
451443 	 * Clock-Architecture Diagram 7
452444 	 */
453445 
454
-	COMPOSITE_NODIV(ACLK_PERI_SRC, "aclk_peri_src", mux_gpll_cpll_p, 0,
446
+	COMPOSITE_NODIV(ACLK_PERI_SRC, "aclk_peri_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
455447 			PX30_CLKSEL_CON(14), 15, 1, MFLAGS,
456448 			PX30_CLKGATE_CON(5), 7, GFLAGS),
457
-	COMPOSITE_NOMUX(ACLK_PERI_PRE, "aclk_peri_pre", "aclk_peri_src", CLK_IGNORE_UNUSED,
449
+	COMPOSITE_NOMUX(ACLK_PERI_PRE, "aclk_peri_pre", "aclk_peri_src", CLK_IS_CRITICAL,
458450 			PX30_CLKSEL_CON(14), 0, 5, DFLAGS,
459451 			PX30_CLKGATE_CON(5), 8, GFLAGS),
460
-	DIV(HCLK_PERI_PRE, "hclk_peri_pre", "aclk_peri_src", CLK_IGNORE_UNUSED,
452
+	DIV(HCLK_PERI_PRE, "hclk_peri_pre", "aclk_peri_src", CLK_IS_CRITICAL,
461453 			PX30_CLKSEL_CON(14), 8, 5, DFLAGS),
462454 
463455 	/* PD_MMC_NAND */
....@@ -534,7 +526,7 @@
534526 			PX30_CLKGATE_CON(6), 15, GFLAGS),
535527 
536528 	/* PD_USB */
537
-	GATE(HCLK_USB, "hclk_usb", "hclk_peri_pre", 0,
529
+	GATE(HCLK_USB, "hclk_usb", "hclk_peri_pre", CLK_IS_CRITICAL,
538530 			PX30_CLKGATE_CON(7), 2, GFLAGS),
539531 	GATE(SCLK_OTG_ADP, "clk_otg_adp", "clk_rtc32k_pmu", 0,
540532 			PX30_CLKGATE_CON(7), 3, GFLAGS),
....@@ -569,19 +561,19 @@
569561 	 */
570562 
571563 	/* PD_BUS */
572
-	COMPOSITE_NODIV(ACLK_BUS_SRC, "aclk_bus_src", mux_gpll_cpll_p, CLK_IGNORE_UNUSED,
564
+	COMPOSITE_NODIV(ACLK_BUS_SRC, "aclk_bus_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
573565 			PX30_CLKSEL_CON(23), 15, 1, MFLAGS,
574566 			PX30_CLKGATE_CON(8), 6, GFLAGS),
575
-	COMPOSITE_NOMUX(HCLK_BUS_PRE, "hclk_bus_pre", "aclk_bus_src", CLK_IGNORE_UNUSED,
567
+	COMPOSITE_NOMUX(HCLK_BUS_PRE, "hclk_bus_pre", "aclk_bus_src", CLK_IS_CRITICAL,
576568 			PX30_CLKSEL_CON(24), 0, 5, DFLAGS,
577569 			PX30_CLKGATE_CON(8), 8, GFLAGS),
578
-	COMPOSITE_NOMUX(ACLK_BUS_PRE, "aclk_bus_pre", "aclk_bus_src", CLK_IGNORE_UNUSED,
570
+	COMPOSITE_NOMUX(ACLK_BUS_PRE, "aclk_bus_pre", "aclk_bus_src", CLK_IS_CRITICAL,
579571 			PX30_CLKSEL_CON(23), 8, 5, DFLAGS,
580572 			PX30_CLKGATE_CON(8), 7, GFLAGS),
581
-	COMPOSITE_NOMUX(PCLK_BUS_PRE, "pclk_bus_pre", "aclk_bus_pre", CLK_IGNORE_UNUSED,
573
+	COMPOSITE_NOMUX(PCLK_BUS_PRE, "pclk_bus_pre", "aclk_bus_pre", CLK_IS_CRITICAL,
582574 			PX30_CLKSEL_CON(24), 8, 2, DFLAGS,
583575 			PX30_CLKGATE_CON(8), 9, GFLAGS),
584
-	GATE(0, "pclk_top_pre", "pclk_bus_pre", CLK_IGNORE_UNUSED,
576
+	GATE(0, "pclk_top_pre", "pclk_bus_pre", CLK_IS_CRITICAL,
585577 			PX30_CLKGATE_CON(8), 10, GFLAGS),
586578 
587579 	COMPOSITE(0, "clk_pdm_src", mux_gpll_xin24m_npll_p, 0,
....@@ -590,7 +582,7 @@
590582 	COMPOSITE_FRACMUX(0, "clk_pdm_frac", "clk_pdm_src", CLK_SET_RATE_PARENT,
591583 			PX30_CLKSEL_CON(27), 0,
592584 			PX30_CLKGATE_CON(9), 10, GFLAGS,
593
-			&px30_pdm_fracmux, PX30_FRAC_MAX_PRATE),
585
+			&px30_pdm_fracmux),
594586 	GATE(SCLK_PDM, "clk_pdm", "clk_pdm_mux", CLK_SET_RATE_PARENT,
595587 			PX30_CLKGATE_CON(9), 11, GFLAGS),
596588 
....@@ -600,7 +592,7 @@
600592 	COMPOSITE_FRACMUX(0, "clk_i2s0_tx_frac", "clk_i2s0_tx_src", CLK_SET_RATE_PARENT,
601593 			PX30_CLKSEL_CON(29), 0,
602594 			PX30_CLKGATE_CON(9), 13, GFLAGS,
603
-			&px30_i2s0_tx_fracmux, PX30_FRAC_MAX_PRATE),
595
+			&px30_i2s0_tx_fracmux),
604596 	COMPOSITE_NODIV(SCLK_I2S0_TX, "clk_i2s0_tx", mux_i2s0_tx_rx_p, CLK_SET_RATE_PARENT,
605597 			PX30_CLKSEL_CON(28), 12, 1, MFLAGS,
606598 			PX30_CLKGATE_CON(9), 14, GFLAGS),
....@@ -616,7 +608,7 @@
616608 	COMPOSITE_FRACMUX(0, "clk_i2s0_rx_frac", "clk_i2s0_rx_src", CLK_SET_RATE_PARENT,
617609 			PX30_CLKSEL_CON(59), 0,
618610 			PX30_CLKGATE_CON(17), 1, GFLAGS,
619
-			&px30_i2s0_rx_fracmux, PX30_FRAC_MAX_PRATE),
611
+			&px30_i2s0_rx_fracmux),
620612 	COMPOSITE_NODIV(SCLK_I2S0_RX, "clk_i2s0_rx", mux_i2s0_rx_tx_p, CLK_SET_RATE_PARENT,
621613 			PX30_CLKSEL_CON(58), 12, 1, MFLAGS,
622614 			PX30_CLKGATE_CON(17), 2, GFLAGS),
....@@ -632,7 +624,7 @@
632624 	COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_src", CLK_SET_RATE_PARENT,
633625 			PX30_CLKSEL_CON(31), 0,
634626 			PX30_CLKGATE_CON(10), 1, GFLAGS,
635
-			&px30_i2s1_fracmux, PX30_FRAC_MAX_PRATE),
627
+			&px30_i2s1_fracmux),
636628 	GATE(SCLK_I2S1, "clk_i2s1", "clk_i2s1_mux", CLK_SET_RATE_PARENT,
637629 			PX30_CLKGATE_CON(10), 2, GFLAGS),
638630 	COMPOSITE_NODIV(0, "clk_i2s1_out_pre", mux_i2s1_out_p, CLK_SET_RATE_PARENT,
....@@ -647,7 +639,7 @@
647639 	COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_src", CLK_SET_RATE_PARENT,
648640 			PX30_CLKSEL_CON(33), 0,
649641 			PX30_CLKGATE_CON(10), 5, GFLAGS,
650
-			&px30_i2s2_fracmux, PX30_FRAC_MAX_PRATE),
642
+			&px30_i2s2_fracmux),
651643 	GATE(SCLK_I2S2, "clk_i2s2", "clk_i2s2_mux", CLK_SET_RATE_PARENT,
652644 			PX30_CLKGATE_CON(10), 6, GFLAGS),
653645 	COMPOSITE_NODIV(0, "clk_i2s2_out_pre", mux_i2s2_out_p, 0,
....@@ -665,7 +657,7 @@
665657 	COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT,
666658 			PX30_CLKSEL_CON(36), 0,
667659 			PX30_CLKGATE_CON(10), 14, GFLAGS,
668
-			&px30_uart1_fracmux, PX30_FRAC_MAX_PRATE),
660
+			&px30_uart1_fracmux),
669661 	GATE(SCLK_UART1, "clk_uart1", "clk_uart1_mux", CLK_SET_RATE_PARENT,
670662 			PX30_CLKGATE_CON(10), 15, GFLAGS),
671663 
....@@ -678,8 +670,8 @@
678670 	COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT,
679671 			PX30_CLKSEL_CON(39), 0,
680672 			PX30_CLKGATE_CON(11), 2, GFLAGS,
681
-			&px30_uart2_fracmux, PX30_FRAC_MAX_PRATE),
682
-	GATE(SCLK_UART2, "clk_uart2", "clk_uart2_mux", CLK_SET_RATE_PARENT,
673
+			&px30_uart2_fracmux),
674
+	GATE(SCLK_UART2, "clk_uart2", "clk_uart2_mux", CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
683675 			PX30_CLKGATE_CON(11), 3, GFLAGS),
684676 
685677 	COMPOSITE(0, "clk_uart3_src", mux_uart_src_p, 0,
....@@ -691,7 +683,7 @@
691683 	COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT,
692684 			PX30_CLKSEL_CON(42), 0,
693685 			PX30_CLKGATE_CON(11), 6, GFLAGS,
694
-			&px30_uart3_fracmux, PX30_FRAC_MAX_PRATE),
686
+			&px30_uart3_fracmux),
695687 	GATE(SCLK_UART3, "clk_uart3", "clk_uart3_mux", CLK_SET_RATE_PARENT,
696688 			PX30_CLKGATE_CON(11), 7, GFLAGS),
697689 
....@@ -704,7 +696,7 @@
704696 	COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT,
705697 			PX30_CLKSEL_CON(45), 0,
706698 			PX30_CLKGATE_CON(11), 10, GFLAGS,
707
-			&px30_uart4_fracmux, PX30_FRAC_MAX_PRATE),
699
+			&px30_uart4_fracmux),
708700 	GATE(SCLK_UART4, "clk_uart4", "clk_uart4_mux", CLK_SET_RATE_PARENT,
709701 			PX30_CLKGATE_CON(11), 11, GFLAGS),
710702 
....@@ -717,7 +709,7 @@
717709 	COMPOSITE_FRACMUX(0, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT,
718710 			PX30_CLKSEL_CON(48), 0,
719711 			PX30_CLKGATE_CON(11), 14, GFLAGS,
720
-			&px30_uart5_fracmux, PX30_FRAC_MAX_PRATE),
712
+			&px30_uart5_fracmux),
721713 	GATE(SCLK_UART5, "clk_uart5", "clk_uart5_mux", CLK_SET_RATE_PARENT,
722714 			PX30_CLKGATE_CON(11), 15, GFLAGS),
723715 
....@@ -792,29 +784,29 @@
792784 	GATE(0, "pclk_ddrphy", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 3, GFLAGS),
793785 	GATE(PCLK_MIPIDSIPHY, "pclk_mipidsiphy", "pclk_top_pre", 0, PX30_CLKGATE_CON(16), 4, GFLAGS),
794786 	GATE(PCLK_MIPICSIPHY, "pclk_mipicsiphy", "pclk_top_pre", 0, PX30_CLKGATE_CON(16), 5, GFLAGS),
795
-	GATE(PCLK_USB_GRF, "pclk_usb_grf", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 6, GFLAGS),
787
+	GATE(PCLK_USB_GRF, "pclk_usb_grf", "pclk_top_pre", CLK_IS_CRITICAL, PX30_CLKGATE_CON(16), 6, GFLAGS),
796788 	GATE(0, "pclk_cpu_hoost", "pclk_top_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(16), 7, GFLAGS),
797789 
798790 	/* PD_VI */
799
-	GATE(0, "aclk_vi_niu", "aclk_vi_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(4), 15, GFLAGS),
791
+	GATE(0, "aclk_vi_niu", "aclk_vi_pre", CLK_IS_CRITICAL, PX30_CLKGATE_CON(4), 15, GFLAGS),
800792 	GATE(ACLK_CIF, "aclk_cif", "aclk_vi_pre", 0, PX30_CLKGATE_CON(5), 1, GFLAGS),
801793 	GATE(ACLK_ISP, "aclk_isp", "aclk_vi_pre", 0, PX30_CLKGATE_CON(5), 3, GFLAGS),
802
-	GATE(0, "hclk_vi_niu", "hclk_vi_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(5), 0, GFLAGS),
794
+	GATE(0, "hclk_vi_niu", "hclk_vi_pre", CLK_IS_CRITICAL, PX30_CLKGATE_CON(5), 0, GFLAGS),
803795 	GATE(HCLK_CIF, "hclk_cif", "hclk_vi_pre", 0, PX30_CLKGATE_CON(5), 2, GFLAGS),
804796 	GATE(HCLK_ISP, "hclk_isp", "hclk_vi_pre", 0, PX30_CLKGATE_CON(5), 4, GFLAGS),
805797 
806798 	/* PD_VO */
807
-	GATE(0, "aclk_vo_niu", "aclk_vo_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(3), 0, GFLAGS),
799
+	GATE(0, "aclk_vo_niu", "aclk_vo_pre", CLK_IS_CRITICAL, PX30_CLKGATE_CON(3), 0, GFLAGS),
808800 	GATE(ACLK_VOPB, "aclk_vopb", "aclk_vo_pre", 0, PX30_CLKGATE_CON(3), 3, GFLAGS),
809801 	GATE(ACLK_RGA, "aclk_rga", "aclk_vo_pre", 0, PX30_CLKGATE_CON(3), 7, GFLAGS),
810802 	GATE(ACLK_VOPL, "aclk_vopl", "aclk_vo_pre", 0, PX30_CLKGATE_CON(3), 5, GFLAGS),
811803 
812
-	GATE(0, "hclk_vo_niu", "hclk_vo_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(3), 1, GFLAGS),
804
+	GATE(0, "hclk_vo_niu", "hclk_vo_pre", CLK_IS_CRITICAL, PX30_CLKGATE_CON(3), 1, GFLAGS),
813805 	GATE(HCLK_VOPB, "hclk_vopb", "hclk_vo_pre", 0, PX30_CLKGATE_CON(3), 4, GFLAGS),
814806 	GATE(HCLK_RGA, "hclk_rga", "hclk_vo_pre", 0, PX30_CLKGATE_CON(3), 8, GFLAGS),
815807 	GATE(HCLK_VOPL, "hclk_vopl", "hclk_vo_pre", 0, PX30_CLKGATE_CON(3), 6, GFLAGS),
816808 
817
-	GATE(0, "pclk_vo_niu", "pclk_vo_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(3), 2, GFLAGS),
809
+	GATE(0, "pclk_vo_niu", "pclk_vo_pre", CLK_IS_CRITICAL, PX30_CLKGATE_CON(3), 2, GFLAGS),
818810 	GATE(PCLK_MIPI_DSI, "pclk_mipi_dsi", "pclk_vo_pre", 0, PX30_CLKGATE_CON(3), 9, GFLAGS),
819811 
820812 	/* PD_BUS */
....@@ -822,6 +814,9 @@
822814 	GATE(0, "aclk_intmem", "aclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 11, GFLAGS),
823815 	GATE(ACLK_GIC, "aclk_gic", "aclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 12, GFLAGS),
824816 	GATE(ACLK_DCF, "aclk_dcf", "aclk_bus_pre", 0, PX30_CLKGATE_CON(13), 15, GFLAGS),
817
+
818
+	/* aclk_dmac is controlled by sgrf_soc_con1[11]. */
819
+	SGRF_GATE(ACLK_DMAC, "aclk_dmac", "aclk_bus_pre"),
825820 
826821 	GATE(0, "hclk_bus_niu", "hclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 9, GFLAGS),
827822 	GATE(0, "hclk_rom", "hclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 14, GFLAGS),
....@@ -833,7 +828,7 @@
833828 	GATE(0, "pclk_bus_niu", "pclk_bus_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(13), 10, GFLAGS),
834829 	GATE(PCLK_DCF, "pclk_dcf", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 0, GFLAGS),
835830 	GATE(PCLK_UART1, "pclk_uart1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 5, GFLAGS),
836
-	GATE(PCLK_UART2, "pclk_uart2", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 6, GFLAGS),
831
+	GATE(PCLK_UART2, "pclk_uart2", "pclk_bus_pre", CLK_IS_CRITICAL, PX30_CLKGATE_CON(14), 6, GFLAGS),
837832 	GATE(PCLK_UART3, "pclk_uart3", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 7, GFLAGS),
838833 	GATE(PCLK_UART4, "pclk_uart4", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 8, GFLAGS),
839834 	GATE(PCLK_UART5, "pclk_uart5", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 9, GFLAGS),
....@@ -874,7 +869,7 @@
874869 	GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sdmmc_pre", 0, PX30_CLKGATE_CON(7), 1, GFLAGS),
875870 
876871 	/* PD_PERI */
877
-	GATE(0, "aclk_peri_niu", "aclk_peri_pre", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(5), 9, GFLAGS),
872
+	GATE(0, "aclk_peri_niu", "aclk_peri_pre", CLK_IS_CRITICAL, PX30_CLKGATE_CON(5), 9, GFLAGS),
878873 
879874 	/* PD_MMC_NAND */
880875 	GATE(HCLK_NANDC, "hclk_nandc", "hclk_mmc_nand", 0, PX30_CLKGATE_CON(5), 15, GFLAGS),
....@@ -884,7 +879,7 @@
884879 	GATE(HCLK_SFC, "hclk_sfc", "hclk_mmc_nand", 0, PX30_CLKGATE_CON(6), 11, GFLAGS),
885880 
886881 	/* PD_USB */
887
-	GATE(0, "hclk_usb_niu", "hclk_usb", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(7), 4, GFLAGS),
882
+	GATE(0, "hclk_usb_niu", "hclk_usb", CLK_IS_CRITICAL, PX30_CLKGATE_CON(7), 4, GFLAGS),
888883 	GATE(HCLK_OTG, "hclk_otg", "hclk_usb", 0, PX30_CLKGATE_CON(7), 5, GFLAGS),
889884 	GATE(HCLK_HOST, "hclk_host", "hclk_usb", 0, PX30_CLKGATE_CON(7), 6, GFLAGS),
890885 	GATE(HCLK_HOST_ARB, "hclk_host_arb", "hclk_usb", CLK_IGNORE_UNUSED, PX30_CLKGATE_CON(7), 8, GFLAGS),
....@@ -920,7 +915,7 @@
920915 	COMPOSITE_FRACMUX(0, "clk_rtc32k_frac", "xin24m", CLK_IGNORE_UNUSED,
921916 			PX30_PMU_CLKSEL_CON(1), 0,
922917 			PX30_PMU_CLKGATE_CON(0), 13, GFLAGS,
923
-			&px30_rtc32k_pmu_fracmux, 0),
918
+			&px30_rtc32k_pmu_fracmux),
924919 
925920 	COMPOSITE_NOMUX(XIN24M_DIV, "xin24m_div", "xin24m", CLK_IGNORE_UNUSED,
926921 			PX30_PMU_CLKSEL_CON(0), 8, 5, DFLAGS,
....@@ -942,14 +937,14 @@
942937 	COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_pmu_src", CLK_SET_RATE_PARENT,
943938 			PX30_PMU_CLKSEL_CON(5), 0,
944939 			PX30_PMU_CLKGATE_CON(1), 2, GFLAGS,
945
-			&px30_uart0_pmu_fracmux, PX30_FRAC_MAX_PRATE),
940
+			&px30_uart0_pmu_fracmux),
946941 	GATE(SCLK_UART0_PMU, "clk_uart0_pmu", "clk_uart0_pmu_mux", CLK_SET_RATE_PARENT,
947942 			PX30_PMU_CLKGATE_CON(1), 3, GFLAGS),
948943 
949944 	GATE(SCLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", 0,
950945 			PX30_PMU_CLKGATE_CON(1), 4, GFLAGS),
951946 
952
-	COMPOSITE_NOMUX(PCLK_PMU_PRE, "pclk_pmu_pre", "gpll", 0,
947
+	COMPOSITE_NOMUX(PCLK_PMU_PRE, "pclk_pmu_pre", "gpll", CLK_IS_CRITICAL,
953948 			PX30_PMU_CLKSEL_CON(0), 0, 5, DFLAGS,
954949 			PX30_PMU_CLKGATE_CON(0), 0, GFLAGS),
955950 
....@@ -976,23 +971,6 @@
976971 	GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pclk_pmu_pre", 0, PX30_PMU_CLKGATE_CON(0), 6, GFLAGS),
977972 	GATE(PCLK_UART0_PMU, "pclk_uart0_pmu", "pclk_pmu_pre", 0, PX30_PMU_CLKGATE_CON(0), 7, GFLAGS),
978973 	GATE(0, "pclk_cru_pmu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, PX30_PMU_CLKGATE_CON(0), 8, GFLAGS),
979
-};
980
-
981
-static const char *const px30_pmucru_critical_clocks[] __initconst = {
982
-	"aclk_bus_pre",
983
-	"pclk_bus_pre",
984
-	"hclk_bus_pre",
985
-	"aclk_peri_pre",
986
-	"hclk_peri_pre",
987
-	"aclk_gpu_niu",
988
-	"pclk_top_pre",
989
-	"pclk_pmu_pre",
990
-	"hclk_usb_niu",
991
-	"pll_npll",
992
-	"usb480m",
993
-	"clk_uart2",
994
-	"pclk_uart2",
995
-	"clk_rtc32k_pmu",
996974 };
997975 
998976 static struct rockchip_clk_branch px30_clk_ddrphy_otp[] __initdata = {
....@@ -1025,11 +1003,21 @@
10251003 			PX30_CLKGATE_CON(12), 11, GFLAGS),
10261004 };
10271005 
1006
+static __initdata struct rockchip_clk_provider *cru_ctx, *pmucru_ctx;
1007
+static void __init px30_register_armclk(void)
1008
+{
1009
+	rockchip_clk_register_armclk(cru_ctx, ARMCLK, "armclk", 2,
1010
+				     cru_ctx->clk_data.clks[PLL_APLL],
1011
+				     pmucru_ctx->clk_data.clks[PLL_GPLL],
1012
+				     &px30_cpuclk_data,
1013
+				     px30_cpuclk_rates,
1014
+				     ARRAY_SIZE(px30_cpuclk_rates));
1015
+}
1016
+
10281017 static void __init px30_clk_init(struct device_node *np)
10291018 {
10301019 	struct rockchip_clk_provider *ctx;
10311020 	void __iomem *reg_base;
1032
-	struct clk *clk;
10331021 
10341022 	reg_base = of_iomap(np, 0);
10351023 	if (!reg_base) {
....@@ -1043,18 +1031,15 @@
10431031 		iounmap(reg_base);
10441032 		return;
10451033 	}
1046
-
1047
-	/* aclk_dmac is controlled by sgrf_soc_con1[11]. */
1048
-	clk = clk_register_fixed_factor(NULL, "aclk_dmac", "aclk_bus_pre", 0, 1, 1);
1049
-	if (IS_ERR(clk))
1050
-		pr_warn("%s: could not register clock aclk_dmac: %ld\n",
1051
-			__func__, PTR_ERR(clk));
1052
-	else
1053
-		rockchip_clk_add_lookup(ctx, clk, ACLK_DMAC);
1034
+	cru_ctx = ctx;
10541035 
10551036 	rockchip_clk_register_plls(ctx, px30_pll_clks,
10561037 				   ARRAY_SIZE(px30_pll_clks),
10571038 				   PX30_GRF_SOC_STATUS0);
1039
+
1040
+	if (pmucru_ctx)
1041
+		px30_register_armclk();
1042
+
10581043 	rockchip_clk_register_branches(ctx, px30_clk_branches,
10591044 				       ARRAY_SIZE(px30_clk_branches));
10601045 	if (of_machine_is_compatible("rockchip,px30"))
....@@ -1071,11 +1056,6 @@
10711056 	else
10721057 		rockchip_clk_register_branches(ctx, px30_clk_ddrphy_otp,
10731058 					       ARRAY_SIZE(px30_clk_ddrphy_otp));
1074
-
1075
-	rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
1076
-				     mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
1077
-				     &px30_cpuclk_data, px30_cpuclk_rates,
1078
-				     ARRAY_SIZE(px30_cpuclk_rates));
10791059 
10801060 	rockchip_register_softrst(np, 12, reg_base + PX30_SOFTRST_CON(0),
10811061 				  ROCKCHIP_SOFTRST_HIWORD_MASK);
....@@ -1102,16 +1082,72 @@
11021082 		pr_err("%s: rockchip pmu clk init failed\n", __func__);
11031083 		return;
11041084 	}
1085
+	pmucru_ctx = ctx;
11051086 
11061087 	rockchip_clk_register_plls(ctx, px30_pmu_pll_clks,
11071088 				   ARRAY_SIZE(px30_pmu_pll_clks), PX30_GRF_SOC_STATUS0);
11081089 
1090
+	if (cru_ctx)
1091
+		px30_register_armclk();
1092
+
11091093 	rockchip_clk_register_branches(ctx, px30_clk_pmu_branches,
11101094 				       ARRAY_SIZE(px30_clk_pmu_branches));
1111
-
1112
-	rockchip_clk_protect_critical(px30_pmucru_critical_clocks,
1113
-				      ARRAY_SIZE(px30_pmucru_critical_clocks));
11141095 
11151096 	rockchip_clk_of_add_provider(np, ctx);
11161097 }
11171098 CLK_OF_DECLARE(px30_cru_pmu, "rockchip,px30-pmucru", px30_pmu_clk_init);
1099
+
1100
+#ifdef MODULE
1101
+struct clk_px30_inits {
1102
+	void (*inits)(struct device_node *np);
1103
+};
1104
+
1105
+static const struct clk_px30_inits clk_px30_init = {
1106
+	.inits = px30_clk_init,
1107
+};
1108
+
1109
+static const struct clk_px30_inits clk_px30_pmu_init = {
1110
+	.inits = px30_pmu_clk_init,
1111
+};
1112
+
1113
+static const struct of_device_id clk_px30_match_table[] = {
1114
+	{
1115
+		.compatible = "rockchip,px30-cru",
1116
+		.data = &clk_px30_init,
1117
+	}, {
1118
+		.compatible = "rockchip,px30-pmucru",
1119
+		.data = &clk_px30_pmu_init,
1120
+	},
1121
+	{ }
1122
+};
1123
+MODULE_DEVICE_TABLE(of, clk_px30_match_table);
1124
+
1125
+static int clk_px30_probe(struct platform_device *pdev)
1126
+{
1127
+	struct device_node *np = pdev->dev.of_node;
1128
+	const struct of_device_id *match;
1129
+	const struct clk_px30_inits *init_data;
1130
+
1131
+	match = of_match_device(clk_px30_match_table, &pdev->dev);
1132
+	if (!match || !match->data)
1133
+		return -EINVAL;
1134
+
1135
+	init_data = match->data;
1136
+	if (init_data->inits)
1137
+		init_data->inits(np);
1138
+
1139
+	return 0;
1140
+}
1141
+
1142
+static struct platform_driver clk_px30_driver = {
1143
+	.probe		= clk_px30_probe,
1144
+	.driver		= {
1145
+		.name	= "clk-px30",
1146
+		.of_match_table = clk_px30_match_table,
1147
+	},
1148
+};
1149
+module_platform_driver(clk_px30_driver);
1150
+
1151
+MODULE_DESCRIPTION("Rockchip PX30 Clock Driver");
1152
+MODULE_LICENSE("GPL");
1153
+#endif /* MODULE */