| .. | .. |
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| 3 | 3 | * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd |
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| 4 | 4 | */ |
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| 5 | 5 | |
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| 6 | | -#include <linux/slab.h> |
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| 7 | 6 | #include <linux/clk-provider.h> |
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| 7 | +#include <linux/io.h> |
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| 8 | +#include <linux/slab.h> |
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| 8 | 9 | #include "clk.h" |
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| 9 | 10 | |
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| 10 | 11 | #define div_mask(width) ((1 << (width)) - 1) |
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| .. | .. |
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| 24 | 25 | struct clk_divider *divider = to_clk_divider(hw); |
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| 25 | 26 | unsigned int val; |
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| 26 | 27 | |
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| 27 | | - val = clk_readl(divider->reg) >> divider->shift; |
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| 28 | + val = readl(divider->reg) >> divider->shift; |
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| 28 | 29 | val &= div_mask(divider->width); |
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| 29 | 30 | val = val * 2 + 3; |
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| 30 | 31 | |
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| .. | .. |
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| 116 | 117 | if (divider->flags & CLK_DIVIDER_HIWORD_MASK) { |
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| 117 | 118 | val = div_mask(divider->width) << (divider->shift + 16); |
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| 118 | 119 | } else { |
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| 119 | | - val = clk_readl(divider->reg); |
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| 120 | + val = readl(divider->reg); |
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| 120 | 121 | val &= ~(div_mask(divider->width) << divider->shift); |
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| 121 | 122 | } |
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| 122 | 123 | val |= value << divider->shift; |
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| 123 | | - clk_writel(val, divider->reg); |
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| 124 | + writel(val, divider->reg); |
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| 124 | 125 | |
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| 125 | 126 | if (divider->lock) |
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| 126 | 127 | spin_unlock_irqrestore(divider->lock, flags); |
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| .. | .. |
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| 130 | 131 | return 0; |
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| 131 | 132 | } |
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| 132 | 133 | |
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| 133 | | -const struct clk_ops clk_half_divider_ops = { |
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| 134 | +static const struct clk_ops clk_half_divider_ops = { |
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| 134 | 135 | .recalc_rate = clk_half_divider_recalc_rate, |
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| 135 | 136 | .round_rate = clk_half_divider_round_rate, |
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| 136 | 137 | .set_rate = clk_half_divider_set_rate, |
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| 137 | 138 | }; |
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| 138 | | -EXPORT_SYMBOL_GPL(clk_half_divider_ops); |
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| 139 | 139 | |
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| 140 | 140 | /** |
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| 141 | 141 | * Register a clock branch. |
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| .. | .. |
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| 158 | 158 | u8 gate_flags, unsigned long flags, |
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| 159 | 159 | spinlock_t *lock) |
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| 160 | 160 | { |
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| 161 | | - struct clk *clk = ERR_PTR(-ENOMEM); |
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| 161 | + struct clk_hw *hw = ERR_PTR(-ENOMEM); |
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| 162 | 162 | struct clk_mux *mux = NULL; |
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| 163 | 163 | struct clk_gate *gate = NULL; |
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| 164 | 164 | struct clk_divider *div = NULL; |
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| .. | .. |
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| 207 | 207 | div_ops = &clk_half_divider_ops; |
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| 208 | 208 | } |
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| 209 | 209 | |
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| 210 | | - clk = clk_register_composite(NULL, name, parent_names, num_parents, |
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| 211 | | - mux ? &mux->hw : NULL, mux_ops, |
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| 212 | | - div ? &div->hw : NULL, div_ops, |
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| 213 | | - gate ? &gate->hw : NULL, gate_ops, |
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| 214 | | - flags); |
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| 210 | + hw = clk_hw_register_composite(NULL, name, parent_names, num_parents, |
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| 211 | + mux ? &mux->hw : NULL, mux_ops, |
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| 212 | + div ? &div->hw : NULL, div_ops, |
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| 213 | + gate ? &gate->hw : NULL, gate_ops, |
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| 214 | + flags); |
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| 215 | + if (IS_ERR(hw)) |
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| 216 | + goto err_div; |
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| 215 | 217 | |
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| 216 | | - return clk; |
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| 218 | + return hw->clk; |
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| 217 | 219 | err_div: |
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| 218 | 220 | kfree(gate); |
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| 219 | 221 | err_gate: |
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| 220 | 222 | kfree(mux); |
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| 221 | | - return ERR_PTR(-ENOMEM); |
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| 223 | + return ERR_CAST(hw); |
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| 222 | 224 | } |
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