| .. | .. |
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| 1 | +// SPDX-License-Identifier: GPL-2.0-or-later |
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| 1 | 2 | /* |
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| 2 | 3 | * Copyright 2012-2013 Freescale Semiconductor, Inc. |
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| 3 | | - * |
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| 4 | | - * This program is free software; you can redistribute it and/or modify |
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| 5 | | - * it under the terms of the GNU General Public License as published by |
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| 6 | | - * the Free Software Foundation; either version 2 of the License, or |
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| 7 | | - * (at your option) any later version. |
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| 8 | | - * |
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| 9 | 4 | */ |
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| 10 | 5 | |
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| 11 | 6 | #include <linux/of_address.h> |
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| 7 | +#include <linux/bits.h> |
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| 12 | 8 | #include <linux/clk.h> |
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| 13 | 9 | #include <linux/syscore_ops.h> |
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| 14 | 10 | #include <dt-bindings/clock/vf610-clock.h> |
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| .. | .. |
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| 333 | 329 | clk[VF610_CLK_DSPI2] = imx_clk_gate2("dspi2", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(12)); |
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| 334 | 330 | clk[VF610_CLK_DSPI3] = imx_clk_gate2("dspi3", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(13)); |
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| 335 | 331 | |
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| 332 | + clk[VF610_CLK_CRC] = imx_clk_gate2("crc", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(3)); |
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| 336 | 333 | clk[VF610_CLK_WDT] = imx_clk_gate2("wdt", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(14)); |
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| 337 | 334 | |
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| 338 | 335 | clk[VF610_CLK_ESDHC0_SEL] = imx_clk_mux("esdhc0_sel", CCM_CSCMR1, 16, 2, esdhc_sels, 4); |
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| .. | .. |
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| 443 | 440 | clk[VF610_CLK_SNVS] = imx_clk_gate2("snvs-rtc", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(7)); |
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| 444 | 441 | clk[VF610_CLK_DAP] = imx_clk_gate("dap", "platform_bus", CCM_CCSR, 24); |
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| 445 | 442 | clk[VF610_CLK_OCOTP] = imx_clk_gate("ocotp", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(5)); |
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| 443 | + clk[VF610_CLK_CAAM] = imx_clk_gate2("caam", "ipg_bus", CCM_CCGR11, CCM_CCGRx_CGn(0)); |
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| 446 | 444 | |
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| 447 | 445 | imx_check_clocks(clk, ARRAY_SIZE(clk)); |
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| 448 | 446 | |
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