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2024-10-09 244b2c5ca8b14627e4a17755e5922221e121c771 
 kernel/drivers/clk/imx/clk-pllv3.c
....@@ -1,18 +1,13 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23  * Copyright 2012 Freescale Semiconductor, Inc.
34  * Copyright 2012 Linaro Ltd.
4
- *
5
- * The code contained herein is licensed under the GNU General Public
6
- * License. You may obtain a copy of the GNU General Public License
7
- * Version 2 or later at the following locations:
8
- *
9
- * http://www.opensource.org/licenses/gpl-license.html
10
- * http://www.gnu.org/copyleft/gpl.html
115  */
126 
137 #include <linux/clk-provider.h>
148 #include <linux/delay.h>
159 #include <linux/io.h>
10
+#include <linux/iopoll.h>
1611 #include <linux/slab.h>
1712 #include <linux/jiffies.h>
1813 #include <linux/err.h>
....@@ -20,6 +15,8 @@
2015 
2116 #define PLL_NUM_OFFSET		0x10
2217 #define PLL_DENOM_OFFSET	0x20
18
+#define PLL_IMX7_NUM_OFFSET	0x20
19
+#define PLL_IMX7_DENOM_OFFSET	0x30
2320 
2421 #define PLL_VF610_NUM_OFFSET	0x20
2522 #define PLL_VF610_DENOM_OFFSET	0x30
....@@ -29,14 +26,19 @@
2926 #define IMX7_ENET_PLL_POWER	(0x1 << 5)
3027 #define IMX7_DDR_PLL_POWER	(0x1 << 20)
3128 
29
+#define PLL_LOCK_TIMEOUT	10000
30
+
3231 /**
3332  * struct clk_pllv3 - IMX PLL clock version 3
34
- * @clk_hw:	 clock source
33
+ * @hw:		clock source
3534  * @base:	 base address of PLL registers
3635  * @power_bit:	 pll power bit mask
3736  * @powerup_set: set power_bit to power up the PLL
3837  * @div_mask:	 mask of divider bits
3938  * @div_shift:	 shift of divider bits
39
+ * @ref_clock:	reference clock rate
40
+ * @num_offset:	num register offset
41
+ * @denom_offset: denom register offset
4042  *
4143  * IMX PLL clock version 3, found on i.MX6 series.  Divider for pllv3
4244  * is actually a multiplier, and always sits at bit 0.
....@@ -49,29 +51,22 @@
4951 	u32		div_mask;
5052 	u32		div_shift;
5153 	unsigned long	ref_clock;
54
+	u32		num_offset;
55
+	u32		denom_offset;
5256 };
5357 
5458 #define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw)
5559 
5660 static int clk_pllv3_wait_lock(struct clk_pllv3 *pll)
5761 {
58
-	unsigned long timeout = jiffies + msecs_to_jiffies(10);
5962 	u32 val = readl_relaxed(pll->base) & pll->power_bit;
6063 
6164 	/* No need to wait for lock when pll is not powered up */
6265 	if ((pll->powerup_set && !val) || (!pll->powerup_set && val))
6366 		return 0;
6467 
65
-	/* Wait for PLL to lock */
66
-	do {
67
-		if (readl_relaxed(pll->base) & BM_PLL_LOCK)
68
-			break;
69
-		if (time_after(jiffies, timeout))
70
-			break;
71
-		usleep_range(50, 500);
72
-	} while (1);
73
-
74
-	return readl_relaxed(pll->base) & BM_PLL_LOCK ? 0 : -ETIMEDOUT;
68
+	return readl_relaxed_poll_timeout(pll->base, val, val & BM_PLL_LOCK,
69
+					  500, PLL_LOCK_TIMEOUT);
7570 }
7671 
7772 static int clk_pllv3_prepare(struct clk_hw *hw)
....@@ -219,8 +214,8 @@
219214 					      unsigned long parent_rate)
220215 {
221216 	struct clk_pllv3 *pll = to_clk_pllv3(hw);
222
-	u32 mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET);
223
-	u32 mfd = readl_relaxed(pll->base + PLL_DENOM_OFFSET);
217
+	u32 mfn = readl_relaxed(pll->base + pll->num_offset);
218
+	u32 mfd = readl_relaxed(pll->base + pll->denom_offset);
224219 	u32 div = readl_relaxed(pll->base) & pll->div_mask;
225220 	u64 temp64 = (u64)parent_rate;
226221 
....@@ -289,8 +284,8 @@
289284 	val &= ~pll->div_mask;
290285 	val |= div;
291286 	writel_relaxed(val, pll->base);
292
-	writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET);
293
-	writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET);
287
+	writel_relaxed(mfn, pll->base + pll->num_offset);
288
+	writel_relaxed(mfd, pll->base + pll->denom_offset);
294289 
295290 	return clk_pllv3_wait_lock(pll);
296291 }
....@@ -352,8 +347,8 @@
352347 	struct clk_pllv3 *pll = to_clk_pllv3(hw);
353348 	struct clk_pllv3_vf610_mf mf;
354349 
355
-	mf.mfn = readl_relaxed(pll->base + PLL_VF610_NUM_OFFSET);
356
-	mf.mfd = readl_relaxed(pll->base + PLL_VF610_DENOM_OFFSET);
350
+	mf.mfn = readl_relaxed(pll->base + pll->num_offset);
351
+	mf.mfd = readl_relaxed(pll->base + pll->denom_offset);
357352 	mf.mfi = (readl_relaxed(pll->base) & pll->div_mask) ? 22 : 20;
358353 
359354 	return clk_pllv3_vf610_mf_to_rate(parent_rate, mf);
....@@ -382,8 +377,8 @@
382377 		val |= pll->div_mask;	/* set bit for mfi=22 */
383378 	writel_relaxed(val, pll->base);
384379 
385
-	writel_relaxed(mf.mfn, pll->base + PLL_VF610_NUM_OFFSET);
386
-	writel_relaxed(mf.mfd, pll->base + PLL_VF610_DENOM_OFFSET);
380
+	writel_relaxed(mf.mfn, pll->base + pll->num_offset);
381
+	writel_relaxed(mf.mfd, pll->base + pll->denom_offset);
387382 
388383 	return clk_pllv3_wait_lock(pll);
389384 }
....@@ -412,20 +407,23 @@
412407 	.recalc_rate	= clk_pllv3_enet_recalc_rate,
413408 };
414409 
415
-struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
410
+struct clk_hw *imx_clk_hw_pllv3(enum imx_pllv3_type type, const char *name,
416411 			  const char *parent_name, void __iomem *base,
417412 			  u32 div_mask)
418413 {
419414 	struct clk_pllv3 *pll;
420415 	const struct clk_ops *ops;
421
-	struct clk *clk;
422
-	struct clk_init_data init = {};
416
+	struct clk_hw *hw;
417
+	struct clk_init_data init;
418
+	int ret;
423419 
424420 	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
425421 	if (!pll)
426422 		return ERR_PTR(-ENOMEM);
427423 
428424 	pll->power_bit = BM_PLL_POWER;
425
+	pll->num_offset = PLL_NUM_OFFSET;
426
+	pll->denom_offset = PLL_DENOM_OFFSET;
429427 
430428 	switch (type) {
431429 	case IMX_PLLV3_SYS:
....@@ -433,13 +431,20 @@
433431 		break;
434432 	case IMX_PLLV3_SYS_VF610:
435433 		ops = &clk_pllv3_vf610_ops;
434
+		pll->num_offset = PLL_VF610_NUM_OFFSET;
435
+		pll->denom_offset = PLL_VF610_DENOM_OFFSET;
436436 		break;
437437 	case IMX_PLLV3_USB_VF610:
438438 		pll->div_shift = 1;
439
+		fallthrough;
439440 	case IMX_PLLV3_USB:
440441 		ops = &clk_pllv3_ops;
441442 		pll->powerup_set = true;
442443 		break;
444
+	case IMX_PLLV3_AV_IMX7:
445
+		pll->num_offset = PLL_IMX7_NUM_OFFSET;
446
+		pll->denom_offset = PLL_IMX7_DENOM_OFFSET;
447
+		fallthrough;
443448 	case IMX_PLLV3_AV:
444449 		ops = &clk_pllv3_av_ops;
445450 		break;
....@@ -454,6 +459,8 @@
454459 		break;
455460 	case IMX_PLLV3_DDR_IMX7:
456461 		pll->power_bit = IMX7_DDR_PLL_POWER;
462
+		pll->num_offset = PLL_IMX7_NUM_OFFSET;
463
+		pll->denom_offset = PLL_IMX7_DENOM_OFFSET;
457464 		ops = &clk_pllv3_av_ops;
458465 		break;
459466 	default:
....@@ -469,10 +476,13 @@
469476 	init.num_parents = 1;
470477 
471478 	pll->hw.init = &init;
479
+	hw = &pll->hw;
472480 
473
-	clk = clk_register(NULL, &pll->hw);
474
-	if (IS_ERR(clk))
481
+	ret = clk_hw_register(NULL, hw);
482
+	if (ret) {
475483 		kfree(pll);
484
+		return ERR_PTR(ret);
485
+	}
476486 
477
-	return clk;
487
+	return hw;
478488 }