change system file

hc

2024-10-09 244b2c5ca8b14627e4a17755e5922221e121c771

 kernel/drivers/clk/at91/clk-generated.c
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..
@@ -1,16 +1,12 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later
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 /*
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  *  Copyright (C) 2015 Atmel Corporation,
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  *                     Nicolas Ferre <nicolas.ferre@atmel.com>
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  *
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  * Based on clk-programmable & clk-peripheral drivers by Boris BREZILLON.
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License as published by
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- * the Free Software Foundation; either version 2 of the License, or
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- * (at your option) any later version.
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- *
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  */
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8
 
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+#include <linux/bitfield.h>
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 #include <linux/clk-provider.h>
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 #include <linux/clkdev.h>
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12
 #include <linux/clk/at91_pmc.h>
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@@ -20,28 +16,19 @@
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16
 
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 #include "pmc.h"
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18
 
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-#define PERIPHERAL_MAX		64
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-#define PERIPHERAL_ID_MIN	2
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-
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-#define GENERATED_SOURCE_MAX	6
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 #define GENERATED_MAX_DIV	255
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-
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-#define GCK_ID_SSC0		43
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-#define GCK_ID_SSC1		44
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-#define GCK_ID_I2S0		54
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-#define GCK_ID_I2S1		55
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-#define GCK_ID_CLASSD		59
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-#define GCK_INDEX_DT_AUDIO_PLL	5
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 struct clk_generated {
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 	struct clk_hw hw;
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 	struct regmap *regmap;
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 	struct clk_range range;
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 	spinlock_t *lock;
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+	u32 *mux_table;
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 	u32 id;
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 	u32 gckdiv;
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+	const struct clk_pcr_layout *layout;
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 	u8 parent_id;
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-	bool audio_pll_allowed;
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+	int chg_pid;
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 };
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33
 
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 #define to_clk_generated(hw) \
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@@ -56,14 +43,14 @@
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 		 __func__, gck->gckdiv, gck->parent_id);
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44
 
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 	spin_lock_irqsave(gck->lock, flags);
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-	regmap_write(gck->regmap, AT91_PMC_PCR,
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-		     (gck->id & AT91_PMC_PCR_PID_MASK));
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-	regmap_update_bits(gck->regmap, AT91_PMC_PCR,
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-			   AT91_PMC_PCR_GCKDIV_MASK | AT91_PMC_PCR_GCKCSS_MASK |
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-			   AT91_PMC_PCR_CMD | AT91_PMC_PCR_GCKEN,
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-			   AT91_PMC_PCR_GCKCSS(gck->parent_id) |
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-			   AT91_PMC_PCR_CMD |
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-			   AT91_PMC_PCR_GCKDIV(gck->gckdiv) |
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+	regmap_write(gck->regmap, gck->layout->offset,
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+		     (gck->id & gck->layout->pid_mask));
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+	regmap_update_bits(gck->regmap, gck->layout->offset,
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+			   AT91_PMC_PCR_GCKDIV_MASK | gck->layout->gckcss_mask |
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+			   gck->layout->cmd | AT91_PMC_PCR_GCKEN,
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+			   field_prep(gck->layout->gckcss_mask, gck->parent_id) |
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+			   gck->layout->cmd |
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+			   FIELD_PREP(AT91_PMC_PCR_GCKDIV_MASK, gck->gckdiv) |
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 			   AT91_PMC_PCR_GCKEN);
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 	spin_unlock_irqrestore(gck->lock, flags);
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 	return 0;
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@@ -75,11 +62,11 @@
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 	unsigned long flags;
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63
 
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 	spin_lock_irqsave(gck->lock, flags);
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-	regmap_write(gck->regmap, AT91_PMC_PCR,
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-		     (gck->id & AT91_PMC_PCR_PID_MASK));
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-	regmap_update_bits(gck->regmap, AT91_PMC_PCR,
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-			   AT91_PMC_PCR_CMD | AT91_PMC_PCR_GCKEN,
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-			   AT91_PMC_PCR_CMD);
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+	regmap_write(gck->regmap, gck->layout->offset,
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+		     (gck->id & gck->layout->pid_mask));
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+	regmap_update_bits(gck->regmap, gck->layout->offset,
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+			   gck->layout->cmd | AT91_PMC_PCR_GCKEN,
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+			   gck->layout->cmd);
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 	spin_unlock_irqrestore(gck->lock, flags);
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 }
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@@ -90,12 +77,12 @@
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 	unsigned int status;
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 	spin_lock_irqsave(gck->lock, flags);
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-	regmap_write(gck->regmap, AT91_PMC_PCR,
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-		     (gck->id & AT91_PMC_PCR_PID_MASK));
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-	regmap_read(gck->regmap, AT91_PMC_PCR, &status);
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+	regmap_write(gck->regmap, gck->layout->offset,
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+		     (gck->id & gck->layout->pid_mask));
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+	regmap_read(gck->regmap, gck->layout->offset, &status);
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 	spin_unlock_irqrestore(gck->lock, flags);
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-	return status & AT91_PMC_PCR_GCKEN ? 1 : 0;
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+	return !!(status & AT91_PMC_PCR_GCKEN);
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 }
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 static unsigned long
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@@ -119,9 +106,13 @@
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 		tmp_rate = parent_rate;
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 	else
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 		tmp_rate = parent_rate / div;
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+
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+	if (tmp_rate < req->min_rate || tmp_rate > req->max_rate)
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+		return;
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+
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 	tmp_diff = abs(req->rate - tmp_rate);
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-	if (*best_diff < 0 || *best_diff > tmp_diff) {
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+	if (*best_diff < 0 || *best_diff >= tmp_diff) {
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 		*best_rate = tmp_rate;
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 		*best_diff = tmp_diff;
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 		req->best_parent_rate = parent_rate;
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@@ -141,7 +132,16 @@
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 	int i;
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 	u32 div;
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-	for (i = 0; i < clk_hw_get_num_parents(hw) - 1; i++) {
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+	/* do not look for a rate that is outside of our range */
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+	if (gck->range.max && req->rate > gck->range.max)
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+		req->rate = gck->range.max;
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+	if (gck->range.min && req->rate < gck->range.min)
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+		req->rate = gck->range.min;
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+
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+	for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
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+		if (gck->chg_pid == i)
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+			continue;
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+
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 		parent = clk_hw_get_parent_by_index(hw, i);
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 		if (!parent)
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 			continue;
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@@ -173,16 +173,17 @@
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 	 * that the only clks able to modify gck rate are those of audio IPs.
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 	 */
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-	if (!gck->audio_pll_allowed)
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+	if (gck->chg_pid < 0)
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 		goto end;
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-	parent = clk_hw_get_parent_by_index(hw, GCK_INDEX_DT_AUDIO_PLL);
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+	parent = clk_hw_get_parent_by_index(hw, gck->chg_pid);
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 	if (!parent)
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 		goto end;
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 	for (div = 1; div < GENERATED_MAX_DIV + 2; div++) {
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 		req_parent.rate = req->rate * div;
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-		__clk_determine_rate(parent, &req_parent);
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+		if (__clk_determine_rate(parent, &req_parent))
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+			continue;
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 		clk_generated_best_diff(req, parent, req_parent.rate, div,
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 					&best_diff, &best_rate);
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@@ -196,8 +197,8 @@
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 		 __clk_get_name((req->best_parent_hw)->clk),
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 		 req->best_parent_rate);
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-	if (best_rate < 0)
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-		return best_rate;
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+	if (best_rate < 0 || (gck->range.max && best_rate > gck->range.max))
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+		return -EINVAL;
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 	req->rate = best_rate;
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 	return 0;
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@@ -211,7 +212,11 @@
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 	if (index >= clk_hw_get_num_parents(hw))
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 		return -EINVAL;
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-	gck->parent_id = index;
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+	if (gck->mux_table)
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+		gck->parent_id = clk_mux_index_to_val(gck->mux_table, 0, index);
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+	else
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+		gck->parent_id = index;
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+
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 	return 0;
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 }
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@@ -270,25 +275,25 @@
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 	unsigned long flags;
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 	spin_lock_irqsave(gck->lock, flags);
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-	regmap_write(gck->regmap, AT91_PMC_PCR,
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-		     (gck->id & AT91_PMC_PCR_PID_MASK));
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-	regmap_read(gck->regmap, AT91_PMC_PCR, &tmp);
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+	regmap_write(gck->regmap, gck->layout->offset,
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+		     (gck->id & gck->layout->pid_mask));
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+	regmap_read(gck->regmap, gck->layout->offset, &tmp);
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 	spin_unlock_irqrestore(gck->lock, flags);
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-	gck->parent_id = (tmp & AT91_PMC_PCR_GCKCSS_MASK)
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-					>> AT91_PMC_PCR_GCKCSS_OFFSET;
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-	gck->gckdiv = (tmp & AT91_PMC_PCR_GCKDIV_MASK)
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-					>> AT91_PMC_PCR_GCKDIV_OFFSET;
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+	gck->parent_id = field_get(gck->layout->gckcss_mask, tmp);
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+	gck->gckdiv = FIELD_GET(AT91_PMC_PCR_GCKDIV_MASK, tmp);
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 }
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-static struct clk_hw * __init
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+struct clk_hw * __init
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 at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock,
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+			    const struct clk_pcr_layout *layout,
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 			    const char *name, const char **parent_names,
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-			    u8 num_parents, u8 id, bool pll_audio,
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-			    const struct clk_range *range)
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+			    u32 *mux_table, u8 num_parents, u8 id,
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+			    const struct clk_range *range,
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+			    int chg_pid)
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 {
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 	struct clk_generated *gck;
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-	struct clk_init_data init = {};
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+	struct clk_init_data init;
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 	struct clk_hw *hw;
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 	int ret;
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@@ -300,15 +305,18 @@
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 	init.ops = &generated_ops;
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 	init.parent_names = parent_names;
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 	init.num_parents = num_parents;
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-	init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
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-		CLK_SET_RATE_PARENT;
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+	init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
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+	if (chg_pid >= 0)
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+		init.flags |= CLK_SET_RATE_PARENT;
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 	gck->id = id;
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 	gck->hw.init = &init;
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 	gck->regmap = regmap;
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 	gck->lock = lock;
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 	gck->range = *range;
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-	gck->audio_pll_allowed = pll_audio;
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+	gck->chg_pid = chg_pid;
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+	gck->layout = layout;
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+	gck->mux_table = mux_table;
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 	clk_generated_startup(gck);
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 	hw = &gck->hw;
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@@ -322,61 +330,3 @@
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 	return hw;
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 }
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-
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-static void __init of_sama5d2_clk_generated_setup(struct device_node *np)
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-{
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-	int num;
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-	u32 id;
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-	const char *name;
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-	struct clk_hw *hw;
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-	unsigned int num_parents;
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-	const char *parent_names[GENERATED_SOURCE_MAX];
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-	struct device_node *gcknp;
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-	struct clk_range range = CLK_RANGE(0, 0);
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-	struct regmap *regmap;
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-
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-	num_parents = of_clk_get_parent_count(np);
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-	if (num_parents == 0 || num_parents > GENERATED_SOURCE_MAX)
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-		return;
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-
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-	of_clk_parent_fill(np, parent_names, num_parents);
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-
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-	num = of_get_child_count(np);
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-	if (!num || num > PERIPHERAL_MAX)
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-		return;
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-
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-	regmap = syscon_node_to_regmap(of_get_parent(np));
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-	if (IS_ERR(regmap))
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-		return;
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-
352
-	for_each_child_of_node(np, gcknp) {
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-		bool pll_audio = false;
354
-
355
-		if (of_property_read_u32(gcknp, "reg", &id))
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-			continue;
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-
358
-		if (id < PERIPHERAL_ID_MIN || id >= PERIPHERAL_MAX)
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-			continue;
360
-
361
-		if (of_property_read_string(np, "clock-output-names", &name))
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-			name = gcknp->name;
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-
364
-		of_at91_get_clk_range(gcknp, "atmel,clk-output-range",
365
-				      &range);
366
-
367
-		if (of_device_is_compatible(np, "atmel,sama5d2-clk-generated") &&
368
-		    (id == GCK_ID_I2S0 || id == GCK_ID_I2S1 ||
369
-		     id == GCK_ID_CLASSD))
370
-			pll_audio = true;
371
-
372
-		hw = at91_clk_register_generated(regmap, &pmc_pcr_lock, name,
373
-						  parent_names, num_parents,
374
-						  id, pll_audio, &range);
375
-		if (IS_ERR(hw))
376
-			continue;
377
-
378
-		of_clk_add_hw_provider(gcknp, of_clk_hw_simple_get, hw);
379
-	}
380
-}
381
-CLK_OF_DECLARE(of_sama5d2_clk_generated_setup, "atmel,sama5d2-clk-generated",
382
-	       of_sama5d2_clk_generated_setup);