change system file

hc

2024-10-09 244b2c5ca8b14627e4a17755e5922221e121c771

 kernel/drivers/bus/imx-weim.c
..
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@@ -19,6 +19,8 @@
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 	unsigned int	cs_count;
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 	unsigned int	cs_regs_count;
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 	unsigned int	cs_stride;
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+	unsigned int	wcr_offset;
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+	unsigned int	wcr_bcm;
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 };
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 static const struct imx_weim_devtype imx1_weim_devtype = {
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@@ -37,6 +39,8 @@
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 	.cs_count	= 4,
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 	.cs_regs_count	= 6,
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 	.cs_stride	= 0x18,
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+	.wcr_offset	= 0x90,
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+	.wcr_bcm	= BIT(0),
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 };
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 static const struct imx_weim_devtype imx51_weim_devtype = {
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@@ -46,6 +50,17 @@
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 };
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 #define MAX_CS_REGS_COUNT	6
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+#define MAX_CS_COUNT		6
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+#define OF_REG_SIZE		3
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+
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+struct cs_timing {
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+	bool is_applied;
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+	u32 regs[MAX_CS_REGS_COUNT];
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+};
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+
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+struct cs_timing_state {
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+	struct cs_timing cs[MAX_CS_COUNT];
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+};
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 static const struct of_device_id weim_id_table[] = {
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 	/* i.MX1/21 */
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@@ -61,7 +76,7 @@
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 };
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 MODULE_DEVICE_TABLE(of, weim_id_table);
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-static int __init imx_weim_gpr_setup(struct platform_device *pdev)
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+static int imx_weim_gpr_setup(struct platform_device *pdev)
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 {
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 	struct device_node *np = pdev->dev.of_node;
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 	struct property *prop;
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@@ -111,21 +126,19 @@
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 }
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 /* Parse and set the timing for this device. */
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-static int __init weim_timing_setup(struct device_node *np, void __iomem *base,
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-				    const struct imx_weim_devtype *devtype)
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+static int weim_timing_setup(struct device *dev,
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+			     struct device_node *np, void __iomem *base,
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+			     const struct imx_weim_devtype *devtype,
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+			     struct cs_timing_state *ts)
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 {
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 	u32 cs_idx, value[MAX_CS_REGS_COUNT];
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 	int i, ret;
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+	int reg_idx, num_regs;
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+	struct cs_timing *cst;
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 	if (WARN_ON(devtype->cs_regs_count > MAX_CS_REGS_COUNT))
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 		return -EINVAL;
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-
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-	/* get the CS index from this child node's "reg" property. */
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-	ret = of_property_read_u32(np, "reg", &cs_idx);
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-	if (ret)
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-		return ret;
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-
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-	if (cs_idx >= devtype->cs_count)
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+	if (WARN_ON(devtype->cs_count > MAX_CS_COUNT))
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 		return -EINVAL;
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 	ret = of_property_read_u32_array(np, "fsl,weim-cs-timing",
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@@ -133,21 +146,56 @@
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 	if (ret)
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 		return ret;
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-	/* set the timing for WEIM */
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-	for (i = 0; i < devtype->cs_regs_count; i++)
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-		writel(value[i], base + cs_idx * devtype->cs_stride + i * 4);
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+	/*
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+	 * the child node's "reg" property may contain multiple address ranges,
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+	 * extract the chip select for each.
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+	 */
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+	num_regs = of_property_count_elems_of_size(np, "reg", OF_REG_SIZE);
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+	if (num_regs < 0)
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+		return num_regs;
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+	if (!num_regs)
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+		return -EINVAL;
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+	for (reg_idx = 0; reg_idx < num_regs; reg_idx++) {
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+		/* get the CS index from this child node's "reg" property. */
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+		ret = of_property_read_u32_index(np, "reg",
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+					reg_idx * OF_REG_SIZE, &cs_idx);
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+		if (ret)
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+			break;
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+
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+		if (cs_idx >= devtype->cs_count)
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+			return -EINVAL;
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+
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+		/* prevent re-configuring a CS that's already been configured */
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+		cst = &ts->cs[cs_idx];
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+		if (cst->is_applied && memcmp(value, cst->regs,
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+					devtype->cs_regs_count * sizeof(u32))) {
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+			dev_err(dev, "fsl,weim-cs-timing conflict on %pOF", np);
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+			return -EINVAL;
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+		}
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+
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+		/* set the timing for WEIM */
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+		for (i = 0; i < devtype->cs_regs_count; i++)
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+			writel(value[i],
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+				base + cs_idx * devtype->cs_stride + i * 4);
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+		if (!cst->is_applied) {
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+			cst->is_applied = true;
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+			memcpy(cst->regs, value,
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+				devtype->cs_regs_count * sizeof(u32));
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+		}
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+	}
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 	return 0;
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 }
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-static int __init weim_parse_dt(struct platform_device *pdev,
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-				void __iomem *base)
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+static int weim_parse_dt(struct platform_device *pdev, void __iomem *base)
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 {
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 	const struct of_device_id *of_id = of_match_device(weim_id_table,
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 							   &pdev->dev);
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 	const struct imx_weim_devtype *devtype = of_id->data;
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+	int ret = 0, have_child = 0;
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 	struct device_node *child;
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-	int ret, have_child = 0;
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+	struct cs_timing_state ts = {};
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+	u32 reg;
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 	if (devtype == &imx50_weim_devtype) {
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 		ret = imx_weim_gpr_setup(pdev);
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@@ -155,11 +203,19 @@
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 			return ret;
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 	}
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-	for_each_available_child_of_node(pdev->dev.of_node, child) {
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-		if (!child->name)
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-			continue;
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+	if (of_property_read_bool(pdev->dev.of_node, "fsl,burst-clk-enable")) {
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+		if (devtype->wcr_bcm) {
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+			reg = readl(base + devtype->wcr_offset);
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+			writel(reg | devtype->wcr_bcm,
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+				base + devtype->wcr_offset);
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+		} else {
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+			dev_err(&pdev->dev, "burst clk mode not supported.\n");
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+			return -EINVAL;
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+		}
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+	}
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-		ret = weim_timing_setup(child, base, devtype);
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+	for_each_available_child_of_node(pdev->dev.of_node, child) {
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+		ret = weim_timing_setup(&pdev->dev, child, base, devtype, &ts);
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 		if (ret)
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 			dev_warn(&pdev->dev, "%pOF set timing failed.\n",
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 				child);
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@@ -176,7 +232,7 @@
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 	return ret;
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 }
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-static int __init weim_probe(struct platform_device *pdev)
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+static int weim_probe(struct platform_device *pdev)
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 {
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 	struct resource *res;
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 	struct clk *clk;
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@@ -213,8 +269,9 @@
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 		.name		= "imx-weim",
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 		.of_match_table	= weim_id_table,
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 	},
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+	.probe = weim_probe,
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 };
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-module_platform_driver_probe(weim_driver, weim_probe);
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+module_platform_driver(weim_driver);
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 MODULE_AUTHOR("Freescale Semiconductor Inc.");
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 MODULE_DESCRIPTION("i.MX EIM Controller Driver");