forked from ~ljy/RK356X_SDK_RELEASE
blame | history | patch | commit | commitdiff
hc
2024-10-09 244b2c5ca8b14627e4a17755e5922221e121c771 
 kernel/arch/arm64/kernel/hw_breakpoint.c
....@@ -1,21 +1,10 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
34  * using the CPU's debug registers.
45  *
56  * Copyright (C) 2012 ARM Limited
67  * Author: Will Deacon <will.deacon@arm.com>
7
- *
8
- * This program is free software; you can redistribute it and/or modify
9
- * it under the terms of the GNU General Public License version 2 as
10
- * published by the Free Software Foundation.
11
- *
12
- * This program is distributed in the hope that it will be useful,
13
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
14
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15
- * GNU General Public License for more details.
16
- *
17
- * You should have received a copy of the GNU General Public License
18
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
198  */
209 
2110 #define pr_fmt(fmt) "hw-breakpoint: " fmt
....@@ -62,7 +51,7 @@
6251 	case TYPE_DATA:
6352 		return get_num_wrps();
6453 	default:
65
-		pr_warning("unknown slot type: %d\n", type);
54
+		pr_warn("unknown slot type: %d\n", type);
6655 		return 0;
6756 	}
6857 }
....@@ -123,7 +112,7 @@
123112 	GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_WVR, AARCH64_DBG_REG_NAME_WVR, val);
124113 	GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_WCR, AARCH64_DBG_REG_NAME_WCR, val);
125114 	default:
126
-		pr_warning("attempt to read from unknown breakpoint register %d\n", n);
115
+		pr_warn("attempt to read from unknown breakpoint register %d\n", n);
127116 	}
128117 
129118 	return val;
....@@ -138,7 +127,7 @@
138127 	GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_WVR, AARCH64_DBG_REG_NAME_WVR, val);
139128 	GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_WCR, AARCH64_DBG_REG_NAME_WCR, val);
140129 	default:
141
-		pr_warning("attempt to write to unknown breakpoint register %d\n", n);
130
+		pr_warn("attempt to write to unknown breakpoint register %d\n", n);
142131 	}
143132 	isb();
144133 }
....@@ -156,7 +145,7 @@
156145 	case AARCH64_BREAKPOINT_EL1:
157146 		return DBG_ACTIVE_EL1;
158147 	default:
159
-		pr_warning("invalid breakpoint privilege level %d\n", privilege);
148
+		pr_warn("invalid breakpoint privilege level %d\n", privilege);
160149 		return -EINVAL;
161150 	}
162151 }
....@@ -268,7 +257,7 @@
268257 		 * level.
269258 		 */
270259 		enable_debug_monitors(dbg_el);
271
-		/* Fall through */
260
+		fallthrough;
272261 	case HW_BREAKPOINT_RESTORE:
273262 		/* Setup the address register. */
274263 		write_wb_reg(val_reg, i, info->address);
....@@ -551,10 +540,14 @@
551540 			/* Allow halfword watchpoints and breakpoints. */
552541 			if (hw->ctrl.len == ARM_BREAKPOINT_LEN_2)
553542 				break;
543
+
544
+			fallthrough;
554545 		case 3:
555546 			/* Allow single byte watchpoint. */
556547 			if (hw->ctrl.len == ARM_BREAKPOINT_LEN_1)
557548 				break;
549
+
550
+			fallthrough;
558551 		default:
559552 			return -EINVAL;
560553 		}
....@@ -661,7 +654,7 @@
661654 		perf_bp_event(bp, regs);
662655 
663656 		/* Do we need to handle the stepping? */
664
-		if (is_default_overflow_handler(bp))
657
+		if (uses_default_overflow_handler(bp))
665658 			step = 1;
666659 unlock:
667660 		rcu_read_unlock();
....@@ -740,7 +733,7 @@
740733 static int watchpoint_report(struct perf_event *wp, unsigned long addr,
741734 			     struct pt_regs *regs)
742735 {
743
-	int step = is_default_overflow_handler(wp);
736
+	int step = uses_default_overflow_handler(wp);
744737 	struct arch_hw_breakpoint *info = counter_arch_bp(wp);
745738 
746739 	info->trigger = addr;