change system file

hc

2024-10-09 244b2c5ca8b14627e4a17755e5922221e121c771

 kernel/arch/arm/vfp/vfphw.S
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@@ -1,12 +1,9 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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 /*
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  *  linux/arch/arm/vfp/vfphw.S
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  *
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  *  Copyright (C) 2004 ARM Limited.
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  *  Written by Deep Blue Solutions Limited.
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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  *
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  * This code is called from the kernel's undefined instruction trap.
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  * r9 holds the return address for successful handling.
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@@ -81,11 +78,7 @@
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 ENTRY(vfp_support_entry)
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 	DBGSTR3	"instr %08x pc %08x state %p", r0, r2, r10
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-	ldr	r3, [sp, #S_PSR]	@ Neither lazy restore nor FP exceptions
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-	and	r3, r3, #MODE_MASK	@ are supported in kernel mode
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-	teq	r3, #USR_MODE
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-	bne	vfp_kmode_exception	@ Returns through lr
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-
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+	.fpu	vfpv2
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 	VFPFMRX	r1, FPEXC		@ Is the VFP enabled?
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 	DBGSTR1	"fpexc %08x", r1
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 	tst	r1, #FPEXC_EN
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@@ -261,11 +254,14 @@
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 ENTRY(vfp_get_float)
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 	tbl_branch r0, r3, #3
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+	.fpu	vfpv2
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 	.irp	dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
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-1:	mrc	p10, 0, r0, c\dr, c0, 0	@ fmrs	r0, s0
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+1:	vmov	r0, s\dr
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 	ret	lr
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 	.org	1b + 8
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-1:	mrc	p10, 0, r0, c\dr, c0, 4	@ fmrs	r0, s1
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+	.endr
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+	.irp	dr,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
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+1:	vmov	r0, s\dr
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 	ret	lr
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 	.org	1b + 8
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 	.endr
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@@ -273,11 +269,14 @@
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 ENTRY(vfp_put_float)
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 	tbl_branch r1, r3, #3
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+	.fpu	vfpv2
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 	.irp	dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
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-1:	mcr	p10, 0, r0, c\dr, c0, 0	@ fmsr	r0, s0
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+1:	vmov	s\dr, r0
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 	ret	lr
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 	.org	1b + 8
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-1:	mcr	p10, 0, r0, c\dr, c0, 4	@ fmsr	r0, s1
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+	.endr
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+	.irp	dr,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
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+1:	vmov	s\dr, r0
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 	ret	lr
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 	.org	1b + 8
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 	.endr
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@@ -285,15 +284,17 @@
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 ENTRY(vfp_get_double)
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 	tbl_branch r0, r3, #3
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+	.fpu	vfpv2
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 	.irp	dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
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-1:	fmrrd	r0, r1, d\dr
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+1:	vmov	r0, r1, d\dr
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 	ret	lr
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 	.org	1b + 8
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 	.endr
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 #ifdef CONFIG_VFPv3
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 	@ d16 - d31 registers
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-	.irp	dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
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-1:	mrrc	p11, 3, r0, r1, c\dr	@ fmrrd	r0, r1, d\dr
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+	.fpu	vfpv3
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+	.irp	dr,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
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+1:	vmov	r0, r1, d\dr
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 	ret	lr
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 	.org	1b + 8
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 	.endr
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@@ -307,15 +308,17 @@
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 ENTRY(vfp_put_double)
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 	tbl_branch r2, r3, #3
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+	.fpu	vfpv2
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 	.irp	dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
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-1:	fmdrr	d\dr, r0, r1
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+1:	vmov	d\dr, r0, r1
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 	ret	lr
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 	.org	1b + 8
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 	.endr
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 #ifdef CONFIG_VFPv3
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+	.fpu	vfpv3
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 	@ d16 - d31 registers
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-	.irp	dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
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-1:	mcrr	p11, 3, r0, r1, c\dr	@ fmdrr	r0, r1, d\dr
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+	.irp	dr,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
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+1:	vmov	d\dr, r0, r1
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 	ret	lr
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 	.org	1b + 8
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 	.endr