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| 1 | +// SPDX-License-Identifier: GPL-2.0-only |
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| 1 | 2 | /* |
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| 2 | 3 | * linux/arch/arm/common/time-acorn.c |
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| 3 | 4 | * |
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| 4 | 5 | * Copyright (c) 1996-2000 Russell King. |
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| 5 | | - * |
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| 6 | | - * This program is free software; you can redistribute it and/or modify |
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| 7 | | - * it under the terms of the GNU General Public License version 2 as |
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| 8 | | - * published by the Free Software Foundation. |
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| 9 | 6 | * |
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| 10 | 7 | * Changelog: |
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| 11 | 8 | * 24-Sep-1996 RMK Created |
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| .. | .. |
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| 13 | 10 | * 04-Dec-1997 RMK Updated for new arch/arm/time.c |
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| 14 | 11 | * 13=Jun-2004 DS Moved to arch/arm/common b/c shared w/CLPS7500 |
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| 15 | 12 | */ |
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| 16 | | -#include <linux/timex.h> |
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| 13 | +#include <linux/clocksource.h> |
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| 17 | 14 | #include <linux/init.h> |
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| 18 | 15 | #include <linux/interrupt.h> |
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| 19 | 16 | #include <linux/irq.h> |
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| .. | .. |
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| 27 | 24 | #define RPC_CLOCK_FREQ 2000000 |
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| 28 | 25 | #define RPC_LATCH DIV_ROUND_CLOSEST(RPC_CLOCK_FREQ, HZ) |
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| 29 | 26 | |
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| 30 | | -static u32 ioc_timer_gettimeoffset(void) |
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| 27 | +static u32 ioc_time; |
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| 28 | + |
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| 29 | +static u64 ioc_timer_read(struct clocksource *cs) |
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| 31 | 30 | { |
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| 32 | 31 | unsigned int count1, count2, status; |
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| 33 | | - long offset; |
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| 32 | + unsigned long flags; |
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| 33 | + u32 ticks; |
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| 34 | 34 | |
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| 35 | + local_irq_save(flags); |
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| 35 | 36 | ioc_writeb (0, IOC_T0LATCH); |
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| 36 | 37 | barrier (); |
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| 37 | 38 | count1 = ioc_readb(IOC_T0CNTL) | (ioc_readb(IOC_T0CNTH) << 8); |
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| .. | .. |
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| 41 | 42 | ioc_writeb (0, IOC_T0LATCH); |
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| 42 | 43 | barrier (); |
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| 43 | 44 | count2 = ioc_readb(IOC_T0CNTL) | (ioc_readb(IOC_T0CNTH) << 8); |
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| 45 | + ticks = ioc_time + RPC_LATCH - count2; |
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| 46 | + local_irq_restore(flags); |
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| 44 | 47 | |
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| 45 | | - offset = count2; |
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| 46 | 48 | if (count2 < count1) { |
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| 47 | 49 | /* |
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| 48 | | - * We have not had an interrupt between reading count1 |
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| 49 | | - * and count2. |
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| 50 | + * The timer has not reloaded between reading count1 and |
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| 51 | + * count2, check whether an interrupt was actually pending. |
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| 50 | 52 | */ |
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| 51 | 53 | if (status & (1 << 5)) |
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| 52 | | - offset -= RPC_LATCH; |
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| 54 | + ticks += RPC_LATCH; |
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| 53 | 55 | } else if (count2 > count1) { |
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| 54 | 56 | /* |
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| 55 | | - * We have just had another interrupt between reading |
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| 56 | | - * count1 and count2. |
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| 57 | + * The timer has reloaded, so count2 indicates the new |
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| 58 | + * count since the wrap. The interrupt would not have |
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| 59 | + * been processed, so add the missed ticks. |
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| 57 | 60 | */ |
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| 58 | | - offset -= RPC_LATCH; |
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| 61 | + ticks += RPC_LATCH; |
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| 59 | 62 | } |
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| 60 | 63 | |
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| 61 | | - offset = (RPC_LATCH - offset) * (tick_nsec / 1000); |
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| 62 | | - return DIV_ROUND_CLOSEST(offset, RPC_LATCH) * 1000; |
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| 64 | + return ticks; |
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| 63 | 65 | } |
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| 66 | + |
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| 67 | +static struct clocksource ioctime_clocksource = { |
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| 68 | + .read = ioc_timer_read, |
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| 69 | + .mask = CLOCKSOURCE_MASK(32), |
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| 70 | + .rating = 100, |
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| 71 | +}; |
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| 64 | 72 | |
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| 65 | 73 | void __init ioctime_init(void) |
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| 66 | 74 | { |
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| .. | .. |
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| 72 | 80 | static irqreturn_t |
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| 73 | 81 | ioc_timer_interrupt(int irq, void *dev_id) |
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| 74 | 82 | { |
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| 83 | + ioc_time += RPC_LATCH; |
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| 75 | 84 | timer_tick(); |
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| 76 | 85 | return IRQ_HANDLED; |
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| 77 | 86 | } |
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| 78 | | - |
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| 79 | | -static struct irqaction ioc_timer_irq = { |
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| 80 | | - .name = "timer", |
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| 81 | | - .handler = ioc_timer_interrupt |
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| 82 | | -}; |
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| 83 | 87 | |
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| 84 | 88 | /* |
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| 85 | 89 | * Set up timer interrupt. |
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| 86 | 90 | */ |
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| 87 | 91 | void __init ioc_timer_init(void) |
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| 88 | 92 | { |
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| 89 | | - arch_gettimeoffset = ioc_timer_gettimeoffset; |
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| 93 | + WARN_ON(clocksource_register_hz(&ioctime_clocksource, RPC_CLOCK_FREQ)); |
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| 90 | 94 | ioctime_init(); |
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| 91 | | - setup_irq(IRQ_TIMER0, &ioc_timer_irq); |
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| 95 | + if (request_irq(IRQ_TIMER0, ioc_timer_interrupt, 0, "timer", NULL)) |
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| 96 | + pr_err("Failed to request irq %d (timer)\n", IRQ_TIMER0); |
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| 92 | 97 | } |
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