| .. | .. |
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| 7 | 7 | #define __MACH_ROCKCHIP_RV1106_PM_H |
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| 8 | 8 | |
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| 9 | 9 | #define RV1106_WAKEUP_TO_SYSTEM_RESET 0 |
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| 10 | +#define RV1106_HPMCU_FAST_WKUP_TIMEOUT 2000 /* ms */ |
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| 10 | 11 | |
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| 11 | 12 | #define RV1106_PERIGRF_OFFSET 0x0 |
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| 12 | 13 | #define RV1106_VENCGRF_OFFSET 0x10000 |
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| .. | .. |
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| 34 | 35 | |
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| 35 | 36 | #define RV1106_PMUCRU_OFFSET 0x3a0000 |
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| 36 | 37 | #define RV1106_CRU_OFFSET 0x3b0000 |
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| 38 | +#define RV1106_PVTPLLCRU_OFFSET 0x3b1000 |
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| 37 | 39 | #define RV1106_PERICRU_OFFSET 0x3b2000 |
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| 38 | 40 | #define RV1106_VICRU_OFFSET 0x3b4000 |
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| 39 | 41 | #define RV1106_NPUCRU_OFFSET 0x3b6000 |
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| 54 | 56 | |
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| 55 | 57 | #define RV1106_NSTIMER_OFFSET 0x580000 |
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| 56 | 58 | #define RV1106_STIMER_OFFSET 0x590000 |
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| 59 | +#define RV1106_MBOX_OFFSET 0x5c0000 |
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| 57 | 60 | #define RV1106_PMUSRAM_OFFSET 0x670000 |
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| 58 | 61 | #define RV1106_DDRC_OFFSET 0x800000 |
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| 59 | 62 | #define RV1106_FW_DDR_OFFSET 0x900000 |
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| .. | .. |
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| 70 | 73 | #define RV1106_CRU_MODE_CON00 0x280 |
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| 71 | 74 | #define RV1106_CRU_GATE_CON(i) (0x800 + (i) * 4) |
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| 72 | 75 | #define RV1106_CRU_GATE_CON_NUM 4 |
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| 76 | +#define RV1106_CRU_GLB_SRST_FST 0xc08 |
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| 77 | +#define RV1106_CRU_GLB_RST_CON 0xc10 |
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| 73 | 78 | |
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| 74 | 79 | #define CRU_PLLCON1_PWRDOWN BIT(13) |
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| 75 | 80 | #define CRU_PLLCON1_LOCK_STATUS BIT(10) |
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| .. | .. |
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| 101 | 106 | #define RV1106_CORECRU_GATE_CON(i) (0x800 + (i) * 4) |
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| 102 | 107 | #define RV1106_COERCRU_CLKSEL_CON(i) (0x300 + (i) * 4) |
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| 103 | 108 | #define RV1106_CORECRU_GATE_CON_NUM 2 |
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| 109 | +#define RV1106_COERCRU_SFTRST_CON(i) (0xa00 + (i) * 4) |
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| 104 | 110 | |
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| 105 | 111 | /* grf */ |
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| 106 | 112 | #define RV1106_PMUGRF_SOC_CON(i) ((i) * 4) |
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| .. | .. |
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| 109 | 115 | #define RV1106_PMUSGRF_SOC_CON(i) ((i) * 4) |
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| 110 | 116 | |
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| 111 | 117 | #define RV1106_DDRGRF_CON(i) ((i) * 0x4) |
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| 118 | + |
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| 119 | +#define RV1106_CORESGRF_HPMCU_BOOTADDR 0x44 |
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| 120 | + |
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| 121 | +#define RV1106_COREGRF_CACHE_PERI_ADDR_START 0x24 |
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| 122 | +#define RV1106_COREGRF_CACHE_PERI_ADDR_END 0x28 |
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| 112 | 123 | |
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| 113 | 124 | /* pvmt */ |
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| 114 | 125 | #define RV1106_PVTM_CON(i) (0x4 + (i) * 4) |
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| .. | .. |
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| 177 | 188 | #define PMU_SUSPEND_MAGIC 0x02468ace |
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| 178 | 189 | #define PMU_RESUME_MAGIC 0x13579bdf |
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| 179 | 190 | |
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| 191 | +/* mcu */ |
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| 192 | +#define RV1106_MBOX_B2A_STATUS 0x2c |
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| 193 | +#define RV1106_MBOX_B2A_CMD_0 0x30 |
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| 194 | + |
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| 195 | +#define RV1106_HPMCU_MBOX_IRQ_AP 33 |
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| 196 | + |
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| 197 | +#define RV1106_HPMCU_BOOT_ADDR 0x40000 |
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| 198 | +#define RV1106_MBOX_CMD_AP_SUSPEND 0x12345600 |
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| 199 | +#define RV1106_MBOX_CMD_AP_RESUME 0x12345601 |
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| 200 | +#define RV1106_SYS_IS_WKUP 0x87654300 |
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| 201 | + |
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| 180 | 202 | #ifndef __ASSEMBLER__ |
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| 181 | 203 | extern unsigned long rkpm_bootdata_cpusp; |
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| 182 | 204 | extern unsigned long rkpm_bootdata_cpu_code; |
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| .. | .. |
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| 216 | 238 | |
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| 217 | 239 | RV1106_PMU_WAKEUP_USBDEV_EN, |
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| 218 | 240 | RV1106_PMU_WAKEUP_TIMER_EN, |
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| 219 | | - RV1106_PMU_WAKEUP_TIMEROUT_EN, |
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| 241 | + RV1106_PMU_WAKEUP_TIMEOUT_EN, |
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| 220 | 242 | RV1106_PMU_WAKEUP_SFT_WAKEUP_CFG, |
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| 221 | 243 | }; |
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| 222 | 244 | |
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