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hc
2024-10-09 244b2c5ca8b14627e4a17755e5922221e121c771 
 kernel/arch/arm/kernel/iwmmxt.S
....@@ -1,3 +1,4 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
12 /*
23  *  linux/arch/arm/kernel/iwmmxt.S
34  *
....@@ -8,10 +9,6 @@
89  *
910  *  Full lazy switching support, optimizations and more, by Nicolas Pitre
1011 *   Copyright (c) 2003-2004, MontaVista Software, Inc.
11
- *
12
- * This program is free software; you can redistribute it and/or modify
13
- * it under the terms of the GNU General Public License version 2 as
14
- * published by the Free Software Foundation.
1512  */
1613 
1714 #include <linux/linkage.h>
....@@ -19,6 +16,7 @@
1916 #include <asm/thread_info.h>
2017 #include <asm/asm-offsets.h>
2118 #include <asm/assembler.h>
19
+#include "iwmmxt.h"
2220 
2321 #if defined(CONFIG_CPU_PJ4) || defined(CONFIG_CPU_PJ4B)
2422 #define PJ4(code...)		code
....@@ -116,33 +114,33 @@
116114 
117115 concan_dump:
118116 
119
-	wstrw	wCSSF, [r1, #MMX_WCSSF]
120
-	wstrw	wCASF, [r1, #MMX_WCASF]
121
-	wstrw	wCGR0, [r1, #MMX_WCGR0]
122
-	wstrw	wCGR1, [r1, #MMX_WCGR1]
123
-	wstrw	wCGR2, [r1, #MMX_WCGR2]
124
-	wstrw	wCGR3, [r1, #MMX_WCGR3]
117
+	wstrw	wCSSF, r1, MMX_WCSSF
118
+	wstrw	wCASF, r1, MMX_WCASF
119
+	wstrw	wCGR0, r1, MMX_WCGR0
120
+	wstrw	wCGR1, r1, MMX_WCGR1
121
+	wstrw	wCGR2, r1, MMX_WCGR2
122
+	wstrw	wCGR3, r1, MMX_WCGR3
125123 
126124 1:	@ MUP? wRn
127125 	tst	r2, #0x2
128126 	beq	2f
129127 
130
-	wstrd	wR0,  [r1, #MMX_WR0]
131
-	wstrd	wR1,  [r1, #MMX_WR1]
132
-	wstrd	wR2,  [r1, #MMX_WR2]
133
-	wstrd	wR3,  [r1, #MMX_WR3]
134
-	wstrd	wR4,  [r1, #MMX_WR4]
135
-	wstrd	wR5,  [r1, #MMX_WR5]
136
-	wstrd	wR6,  [r1, #MMX_WR6]
137
-	wstrd	wR7,  [r1, #MMX_WR7]
138
-	wstrd	wR8,  [r1, #MMX_WR8]
139
-	wstrd	wR9,  [r1, #MMX_WR9]
140
-	wstrd	wR10, [r1, #MMX_WR10]
141
-	wstrd	wR11, [r1, #MMX_WR11]
142
-	wstrd	wR12, [r1, #MMX_WR12]
143
-	wstrd	wR13, [r1, #MMX_WR13]
144
-	wstrd	wR14, [r1, #MMX_WR14]
145
-	wstrd	wR15, [r1, #MMX_WR15]
128
+	wstrd	wR0,  r1, MMX_WR0
129
+	wstrd	wR1,  r1, MMX_WR1
130
+	wstrd	wR2,  r1, MMX_WR2
131
+	wstrd	wR3,  r1, MMX_WR3
132
+	wstrd	wR4,  r1, MMX_WR4
133
+	wstrd	wR5,  r1, MMX_WR5
134
+	wstrd	wR6,  r1, MMX_WR6
135
+	wstrd	wR7,  r1, MMX_WR7
136
+	wstrd	wR8,  r1, MMX_WR8
137
+	wstrd	wR9,  r1, MMX_WR9
138
+	wstrd	wR10, r1, MMX_WR10
139
+	wstrd	wR11, r1, MMX_WR11
140
+	wstrd	wR12, r1, MMX_WR12
141
+	wstrd	wR13, r1, MMX_WR13
142
+	wstrd	wR14, r1, MMX_WR14
143
+	wstrd	wR15, r1, MMX_WR15
146144 
147145 2:	teq	r0, #0				@ anything to load?
148146 	reteq	lr				@ if not, return
....@@ -150,30 +148,30 @@
150148 concan_load:
151149 
152150 	@ Load wRn
153
-	wldrd	wR0,  [r0, #MMX_WR0]
154
-	wldrd	wR1,  [r0, #MMX_WR1]
155
-	wldrd	wR2,  [r0, #MMX_WR2]
156
-	wldrd	wR3,  [r0, #MMX_WR3]
157
-	wldrd	wR4,  [r0, #MMX_WR4]
158
-	wldrd	wR5,  [r0, #MMX_WR5]
159
-	wldrd	wR6,  [r0, #MMX_WR6]
160
-	wldrd	wR7,  [r0, #MMX_WR7]
161
-	wldrd	wR8,  [r0, #MMX_WR8]
162
-	wldrd	wR9,  [r0, #MMX_WR9]
163
-	wldrd	wR10, [r0, #MMX_WR10]
164
-	wldrd	wR11, [r0, #MMX_WR11]
165
-	wldrd	wR12, [r0, #MMX_WR12]
166
-	wldrd	wR13, [r0, #MMX_WR13]
167
-	wldrd	wR14, [r0, #MMX_WR14]
168
-	wldrd	wR15, [r0, #MMX_WR15]
151
+	wldrd	wR0,  r0, MMX_WR0
152
+	wldrd	wR1,  r0, MMX_WR1
153
+	wldrd	wR2,  r0, MMX_WR2
154
+	wldrd	wR3,  r0, MMX_WR3
155
+	wldrd	wR4,  r0, MMX_WR4
156
+	wldrd	wR5,  r0, MMX_WR5
157
+	wldrd	wR6,  r0, MMX_WR6
158
+	wldrd	wR7,  r0, MMX_WR7
159
+	wldrd	wR8,  r0, MMX_WR8
160
+	wldrd	wR9,  r0, MMX_WR9
161
+	wldrd	wR10, r0, MMX_WR10
162
+	wldrd	wR11, r0, MMX_WR11
163
+	wldrd	wR12, r0, MMX_WR12
164
+	wldrd	wR13, r0, MMX_WR13
165
+	wldrd	wR14, r0, MMX_WR14
166
+	wldrd	wR15, r0, MMX_WR15
169167 
170168 	@ Load wCx
171
-	wldrw	wCSSF, [r0, #MMX_WCSSF]
172
-	wldrw	wCASF, [r0, #MMX_WCASF]
173
-	wldrw	wCGR0, [r0, #MMX_WCGR0]
174
-	wldrw	wCGR1, [r0, #MMX_WCGR1]
175
-	wldrw	wCGR2, [r0, #MMX_WCGR2]
176
-	wldrw	wCGR3, [r0, #MMX_WCGR3]
169
+	wldrw	wCSSF, r0, MMX_WCSSF
170
+	wldrw	wCASF, r0, MMX_WCASF
171
+	wldrw	wCGR0, r0, MMX_WCGR0
172
+	wldrw	wCGR1, r0, MMX_WCGR1
173
+	wldrw	wCGR2, r0, MMX_WCGR2
174
+	wldrw	wCGR3, r0, MMX_WCGR3
177175 
178176 	@ clear CUP/MUP (only if r1 != 0)
179177 	teq	r1, #0