| .. | .. |
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| 1 | +// SPDX-License-Identifier: GPL-2.0-only |
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| 1 | 2 | /* |
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| 2 | | - * This program is free software; you can redistribute it and/or modify |
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| 3 | | - * it under the terms of the GNU General Public License version 2 as |
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| 4 | | - * published by the Free Software Foundation. |
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| 5 | | - * |
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| 6 | | - * This program is distributed in the hope that it will be useful, |
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| 7 | | - * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 8 | | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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| 9 | | - * GNU General Public License for more details. |
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| 10 | | - * |
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| 11 | | - * You should have received a copy of the GNU General Public License |
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| 12 | | - * along with this program; if not, write to the Free Software |
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| 13 | | - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
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| 14 | 3 | * |
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| 15 | 4 | * Copyright (C) 2009, 2010 ARM Limited |
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| 16 | 5 | * |
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| .. | .. |
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| 257 | 246 | case ARM_DEBUG_ARCH_V7_ECP14: |
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| 258 | 247 | case ARM_DEBUG_ARCH_V7_1: |
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| 259 | 248 | case ARM_DEBUG_ARCH_V8: |
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| 249 | + case ARM_DEBUG_ARCH_V8_1: |
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| 250 | + case ARM_DEBUG_ARCH_V8_2: |
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| 251 | + case ARM_DEBUG_ARCH_V8_4: |
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| 260 | 252 | ARM_DBG_WRITE(c0, c2, 2, (dscr | ARM_DSCR_MDBGEN)); |
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| 261 | 253 | isb(); |
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| 262 | 254 | break; |
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| .. | .. |
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| 555 | 547 | if ((hw->ctrl.type != ARM_BREAKPOINT_EXECUTE) |
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| 556 | 548 | && max_watchpoint_len >= 8) |
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| 557 | 549 | break; |
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| 550 | + fallthrough; |
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| 558 | 551 | default: |
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| 559 | 552 | return -EINVAL; |
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| 560 | 553 | } |
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| .. | .. |
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| 619 | 612 | /* Allow halfword watchpoints and breakpoints. */ |
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| 620 | 613 | if (hw->ctrl.len == ARM_BREAKPOINT_LEN_2) |
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| 621 | 614 | break; |
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| 615 | + fallthrough; |
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| 622 | 616 | case 3: |
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| 623 | 617 | /* Allow single byte watchpoint. */ |
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| 624 | 618 | if (hw->ctrl.len == ARM_BREAKPOINT_LEN_1) |
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| 625 | 619 | break; |
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| 620 | + fallthrough; |
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| 626 | 621 | default: |
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| 627 | 622 | ret = -EINVAL; |
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| 628 | 623 | goto out; |
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| .. | .. |
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| 631 | 626 | hw->address &= ~alignment_mask; |
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| 632 | 627 | hw->ctrl.len <<= offset; |
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| 633 | 628 | |
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| 634 | | - if (is_default_overflow_handler(bp)) { |
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| 629 | + if (uses_default_overflow_handler(bp)) { |
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| 635 | 630 | /* |
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| 636 | 631 | * Mismatch breakpoints are required for single-stepping |
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| 637 | 632 | * breakpoints. |
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| .. | .. |
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| 803 | 798 | * Otherwise, insert a temporary mismatch breakpoint so that |
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| 804 | 799 | * we can single-step over the watchpoint trigger. |
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| 805 | 800 | */ |
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| 806 | | - if (!is_default_overflow_handler(wp)) |
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| 801 | + if (!uses_default_overflow_handler(wp)) |
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| 807 | 802 | continue; |
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| 808 | 803 | step: |
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| 809 | 804 | enable_single_step(wp, instruction_pointer(regs)); |
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| .. | .. |
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| 816 | 811 | info->trigger = addr; |
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| 817 | 812 | pr_debug("watchpoint fired: address = 0x%x\n", info->trigger); |
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| 818 | 813 | perf_bp_event(wp, regs); |
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| 819 | | - if (is_default_overflow_handler(wp)) |
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| 814 | + if (uses_default_overflow_handler(wp)) |
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| 820 | 815 | enable_single_step(wp, instruction_pointer(regs)); |
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| 821 | 816 | } |
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| 822 | 817 | |
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| .. | .. |
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| 891 | 886 | info->trigger = addr; |
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| 892 | 887 | pr_debug("breakpoint fired: address = 0x%x\n", addr); |
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| 893 | 888 | perf_bp_event(bp, regs); |
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| 894 | | - if (is_default_overflow_handler(bp)) |
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| 889 | + if (uses_default_overflow_handler(bp)) |
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| 895 | 890 | enable_single_step(bp, addr); |
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| 896 | 891 | goto unlock; |
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| 897 | 892 | } |
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| .. | .. |
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| 933 | 928 | break; |
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| 934 | 929 | case ARM_ENTRY_ASYNC_WATCHPOINT: |
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| 935 | 930 | WARN(1, "Asynchronous watchpoint exception taken. Debugging results may be unreliable\n"); |
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| 931 | + fallthrough; |
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| 936 | 932 | case ARM_ENTRY_SYNC_WATCHPOINT: |
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| 937 | 933 | watchpoint_handler(addr, fsr, regs); |
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| 938 | 934 | break; |
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| .. | .. |
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| 981 | 977 | ARM_DBG_READ(c1, c1, 4, oslsr); |
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| 982 | 978 | if (oslsr & ARM_OSLSR_OSLM0) |
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| 983 | 979 | return true; |
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| 980 | + fallthrough; |
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| 984 | 981 | default: |
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| 985 | 982 | return false; |
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| 986 | 983 | } |
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