| .. | .. |
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| 180 | 180 | { |
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| 181 | 181 | struct nand_chip *this = mtd_to_nand(mtd); |
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| 182 | 182 | switch(cmd){ |
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| 183 | | - case NAND_CTL_SETCLE: this->IO_ADDR_W |= CLE_ADRR_BIT; break; |
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| 184 | | - case NAND_CTL_CLRCLE: this->IO_ADDR_W &= ~CLE_ADRR_BIT; break; |
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| 185 | | - case NAND_CTL_SETALE: this->IO_ADDR_W |= ALE_ADRR_BIT; break; |
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| 186 | | - case NAND_CTL_CLRALE: this->IO_ADDR_W &= ~ALE_ADRR_BIT; break; |
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| 183 | + case NAND_CTL_SETCLE: this->legacy.IO_ADDR_W |= CLE_ADRR_BIT; break; |
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| 184 | + case NAND_CTL_CLRCLE: this->legacy.IO_ADDR_W &= ~CLE_ADRR_BIT; break; |
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| 185 | + case NAND_CTL_SETALE: this->legacy.IO_ADDR_W |= ALE_ADRR_BIT; break; |
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| 186 | + case NAND_CTL_CLRALE: this->legacy.IO_ADDR_W &= ~ALE_ADRR_BIT; break; |
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| 187 | 187 | } |
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| 188 | 188 | } |
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| 189 | 189 | |
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| .. | .. |
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| 197 | 197 | should return 0, if the device is busy (R/B pin is low) and 1, if the |
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| 198 | 198 | device is ready (R/B pin is high). If the hardware interface does not |
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| 199 | 199 | give access to the ready busy pin, then the function must not be defined |
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| 200 | | -and the function pointer this->dev_ready is set to NULL. |
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| 200 | +and the function pointer this->legacy.dev_ready is set to NULL. |
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| 201 | 201 | |
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| 202 | 202 | Init function |
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| 203 | 203 | ------------- |
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| .. | .. |
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| 235 | 235 | } |
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| 236 | 236 | |
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| 237 | 237 | /* Set address of NAND IO lines */ |
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| 238 | | - this->IO_ADDR_R = baseaddr; |
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| 239 | | - this->IO_ADDR_W = baseaddr; |
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| 238 | + this->legacy.IO_ADDR_R = baseaddr; |
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| 239 | + this->legacy.IO_ADDR_W = baseaddr; |
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| 240 | 240 | /* Reference hardware control function */ |
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| 241 | 241 | this->hwcontrol = board_hwcontrol; |
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| 242 | 242 | /* Set command delay time, see datasheet for correct value */ |
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| 243 | | - this->chip_delay = CHIP_DEPENDEND_COMMAND_DELAY; |
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| 243 | + this->legacy.chip_delay = CHIP_DEPENDEND_COMMAND_DELAY; |
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| 244 | 244 | /* Assign the device ready function, if available */ |
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| 245 | | - this->dev_ready = board_dev_ready; |
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| 245 | + this->legacy.dev_ready = board_dev_ready; |
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| 246 | 246 | this->eccmode = NAND_ECC_SOFT; |
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| 247 | 247 | |
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| 248 | 248 | /* Scan to find existence of the device */ |
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| .. | .. |
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| 276 | 276 | #ifdef MODULE |
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| 277 | 277 | static void __exit board_cleanup (void) |
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| 278 | 278 | { |
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| 279 | | - /* Release resources, unregister device */ |
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| 280 | | - nand_release (mtd_to_nand(board_mtd)); |
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| 279 | + /* Unregister device */ |
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| 280 | + WARN_ON(mtd_device_unregister(board_mtd)); |
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| 281 | + /* Release resources */ |
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| 282 | + nand_cleanup(mtd_to_nand(board_mtd)); |
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| 281 | 283 | |
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| 282 | 284 | /* unmap physical address */ |
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| 283 | 285 | iounmap(baseaddr); |
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| .. | .. |
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| 336 | 338 | struct nand_chip *this = mtd_to_nand(mtd); |
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| 337 | 339 | |
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| 338 | 340 | /* Deselect all chips */ |
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| 339 | | - this->IO_ADDR_R &= ~BOARD_NAND_ADDR_MASK; |
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| 340 | | - this->IO_ADDR_W &= ~BOARD_NAND_ADDR_MASK; |
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| 341 | + this->legacy.IO_ADDR_R &= ~BOARD_NAND_ADDR_MASK; |
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| 342 | + this->legacy.IO_ADDR_W &= ~BOARD_NAND_ADDR_MASK; |
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| 341 | 343 | switch (chip) { |
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| 342 | 344 | case 0: |
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| 343 | | - this->IO_ADDR_R |= BOARD_NAND_ADDR_CHIP0; |
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| 344 | | - this->IO_ADDR_W |= BOARD_NAND_ADDR_CHIP0; |
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| 345 | + this->legacy.IO_ADDR_R |= BOARD_NAND_ADDR_CHIP0; |
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| 346 | + this->legacy.IO_ADDR_W |= BOARD_NAND_ADDR_CHIP0; |
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| 345 | 347 | break; |
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| 346 | 348 | .... |
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| 347 | 349 | case n: |
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| 348 | | - this->IO_ADDR_R |= BOARD_NAND_ADDR_CHIPn; |
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| 349 | | - this->IO_ADDR_W |= BOARD_NAND_ADDR_CHIPn; |
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| 350 | + this->legacy.IO_ADDR_R |= BOARD_NAND_ADDR_CHIPn; |
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| 351 | + this->legacy.IO_ADDR_W |= BOARD_NAND_ADDR_CHIPn; |
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| 350 | 352 | break; |
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| 351 | 353 | } |
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| 352 | 354 | } |
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