disable pwm7

hc

2024-05-10 23fa18eaa71266feff7ba8d83022d9e1cc83c65a

 u-boot/drivers/rng/rockchip_rng.c
..
..
@@ -2,13 +2,14 @@
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 /*
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  * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
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  */
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+#include <common.h>
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+#include <clk-uclass.h>
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+#include <dm.h>
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+#include <rng.h>
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 #include <asm/arch-rockchip/hardware.h>
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 #include <asm/io.h>
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-#include <common.h>
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-#include <dm.h>
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 #include <linux/iopoll.h>
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 #include <linux/string.h>
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-#include <rng.h>
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13
 
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 #define RK_HW_RNG_MAX 32
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15
 
..
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@@ -70,6 +71,27 @@
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 #define TRNG_v1_VERSION_CODE			0x46BC
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 /* end of TRNG V1 register define */
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+/* start of RKRNG register define */
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+#define RKRNG_CTRL				0x0010
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+#define RKRNG_CTRL_INST_REQ			BIT(0)
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+#define RKRNG_CTRL_RESEED_REQ			BIT(1)
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+#define RKRNG_CTRL_TEST_REQ			BIT(2)
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+#define RKRNG_CTRL_SW_DRNG_REQ			BIT(3)
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+#define RKRNG_CTRL_SW_TRNG_REQ			BIT(4)
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+
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+#define RKRNG_STATE				0x0014
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+#define RKRNG_STATE_INST_ACK			BIT(0)
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+#define RKRNG_STATE_RESEED_ACK			BIT(1)
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+#define RKRNG_STATE_TEST_ACK			BIT(2)
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+#define RKRNG_STATE_SW_DRNG_ACK			BIT(3)
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+#define RKRNG_STATE_SW_TRNG_ACK			BIT(4)
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+
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+/* DRNG_DATA_0 ~ DNG_DATA_7 */
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+#define RKRNG_DRNG_DATA_0			0x0070
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+#define RKRNG_DRNG_DATA_7			0x008C
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+
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+/* end of RKRNG register define */
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+
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 #define RK_RNG_TIME_OUT	50000  /* max 50ms */
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96
 
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 #define trng_write(pdata, pos, val)	writel(val, (pdata)->base + (pos))
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@@ -83,7 +105,36 @@
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 struct rk_rng_platdata {
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 	fdt_addr_t base;
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 	struct rk_rng_soc_data *soc_data;
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+	struct clk hclk;
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 };
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+
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+static int rk_rng_do_enable_clk(struct udevice *dev, int enable)
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+{
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+	struct rk_rng_platdata *pdata = dev_get_priv(dev);
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+	int ret;
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+
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+	if (!pdata->hclk.dev)
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+		return 0;
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+
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+	ret = enable ? clk_enable(&pdata->hclk) : clk_disable(&pdata->hclk);
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+	if (ret == -ENOSYS || !ret)
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+		return 0;
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+
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+	printf("rk rng: failed to %s clk, ret=%d\n",
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+	       enable ? "enable" : "disable", ret);
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+
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+	return ret;
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+}
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+
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+static int rk_rng_enable_clk(struct udevice *dev)
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+{
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+	return rk_rng_do_enable_clk(dev, 1);
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+}
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+
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+static int rk_rng_disable_clk(struct udevice *dev)
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+{
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+	return rk_rng_do_enable_clk(dev, 0);
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+}
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138
 
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 static int rk_rng_read_regs(fdt_addr_t addr, void *buf, size_t size)
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 {
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@@ -106,7 +157,7 @@
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 	return 0;
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 }
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159
 
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-static int rk_cryptov1_rng_read(struct udevice *dev, void *data, size_t len)
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+static int cryptov1_rng_read(struct udevice *dev, void *data, size_t len)
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 {
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 	struct rk_rng_platdata *pdata = dev_get_priv(dev);
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 	u32 reg = 0;
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@@ -137,7 +188,7 @@
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 	return 0;
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 }
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190
 
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-static int rk_cryptov2_rng_read(struct udevice *dev, void *data, size_t len)
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+static int cryptov2_rng_read(struct udevice *dev, void *data, size_t len)
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 {
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 	struct rk_rng_platdata *pdata = dev_get_priv(dev);
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 	u32 reg = 0;
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@@ -171,7 +222,7 @@
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 	return retval;
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 }
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224
 
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-static int rk_trngv1_init(struct udevice *dev)
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+static int trngv1_init(struct udevice *dev)
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 {
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 	u32 status, version;
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 	u32 auto_reseed_cnt = 1000;
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@@ -198,7 +249,7 @@
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 	return 0;
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 }
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-static int rk_trngv1_rng_read(struct udevice *dev, void *data, size_t len)
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+static int trngv1_rng_read(struct udevice *dev, void *data, size_t len)
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 {
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 	struct rk_rng_platdata *pdata = dev_get_priv(dev);
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 	u32 reg = 0;
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@@ -224,6 +275,53 @@
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 exit:
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 	/* close TRNG */
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 	trng_write(pdata, TRNG_V1_CTRL, TRNG_V1_CTRL_NOP);
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+
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+	return retval;
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+}
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+
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+static int rkrng_init(struct udevice *dev)
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+{
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+	struct rk_rng_platdata *pdata = dev_get_priv(dev);
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+	u32 reg = 0;
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+
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+	rk_clrreg(pdata->base + RKRNG_CTRL, 0xffff);
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+
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+	reg = trng_read(pdata, RKRNG_STATE);
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+	trng_write(pdata, RKRNG_STATE, reg);
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+
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+	return 0;
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+}
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+
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+static int rkrng_rng_read(struct udevice *dev, void *data, size_t len)
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+{
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+	struct rk_rng_platdata *pdata = dev_get_priv(dev);
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+	u32 reg = 0;
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+	int retval;
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+
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+	if (len > RK_HW_RNG_MAX)
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+		return -EINVAL;
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+
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+	rk_rng_enable_clk(dev);
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+
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+	reg = RKRNG_CTRL_SW_DRNG_REQ;
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+
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+	rk_clrsetreg(pdata->base + RKRNG_CTRL, 0xffff, reg);
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+
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+	retval = readl_poll_timeout(pdata->base + RKRNG_STATE, reg,
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+				    (reg & RKRNG_STATE_SW_DRNG_ACK),
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+				    RK_RNG_TIME_OUT);
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+	if (retval)
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+		goto exit;
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+
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+	trng_write(pdata, RKRNG_STATE, reg);
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+
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+	rk_rng_read_regs(pdata->base + RKRNG_DRNG_DATA_0, data, len);
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+
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+exit:
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+	/* close TRNG */
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+	rk_clrreg(pdata->base + RKRNG_CTRL, 0xffff);
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+
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+	rk_rng_disable_clk(dev);
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 	return retval;
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 }
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@@ -266,6 +364,8 @@
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 	if (!pdata->base)
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 		return -ENOMEM;
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+	clk_get_by_index(dev, 0, &pdata->hclk);
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+
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 	return 0;
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 }
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@@ -282,17 +382,22 @@
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 	return ret;
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 }
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-static const struct rk_rng_soc_data rk_cryptov1_soc_data = {
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-	.rk_rng_read = rk_cryptov1_rng_read,
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+static const struct rk_rng_soc_data cryptov1_soc_data = {
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+	.rk_rng_read = cryptov1_rng_read,
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 };
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-static const struct rk_rng_soc_data rk_cryptov2_soc_data = {
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-	.rk_rng_read = rk_cryptov2_rng_read,
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+static const struct rk_rng_soc_data cryptov2_soc_data = {
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+	.rk_rng_read = cryptov2_rng_read,
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 };
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-static const struct rk_rng_soc_data rk_trngv1_soc_data = {
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-	.rk_rng_init = rk_trngv1_init,
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-	.rk_rng_read = rk_trngv1_rng_read,
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+static const struct rk_rng_soc_data trngv1_soc_data = {
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+	.rk_rng_init = trngv1_init,
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+	.rk_rng_read = trngv1_rng_read,
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+};
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+
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+static const struct rk_rng_soc_data rkrng_soc_data = {
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+	.rk_rng_init = rkrng_init,
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+	.rk_rng_read = rkrng_rng_read,
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 };
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 static const struct dm_rng_ops rockchip_rng_ops = {
..
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@@ -302,15 +407,19 @@
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 static const struct udevice_id rockchip_rng_match[] = {
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 	{
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 		.compatible = "rockchip,cryptov1-rng",
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-		.data = (ulong)&rk_cryptov1_soc_data,
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+		.data = (ulong)&cryptov1_soc_data,
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 	},
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 	{
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 		.compatible = "rockchip,cryptov2-rng",
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-		.data = (ulong)&rk_cryptov2_soc_data,
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+		.data = (ulong)&cryptov2_soc_data,
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 	},
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 	{
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 		.compatible = "rockchip,trngv1",
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-		.data = (ulong)&rk_trngv1_soc_data,
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+		.data = (ulong)&trngv1_soc_data,
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+	},
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+	{
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+		.compatible = "rockchip,rkrng",
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+		.data = (ulong)&rkrng_soc_data,
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 	},
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 	{},
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 };