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hc
2024-05-10 23fa18eaa71266feff7ba8d83022d9e1cc83c65a 
 kernel/tools/perf/pmu-events/arch/x86/knightslanding/memory.json
....@@ -9,18 +9,18 @@
99     },
1010     {
1111         "EventCode": "0xB7",
12
-        "MSRValue": "0x0100400070 ",
12
+        "MSRValue": "0x0100400070",
1313         "Counter": "0,1",
1414         "UMask": "0x1",
1515         "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.MCDRAM_FAR",
1616         "MSRIndex": "0x1a6,0x1a7",
1717         "SampleAfterValue": "100007",
18
-        "BriefDescription": "Counts any Prefetch requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far. ",
18
+        "BriefDescription": "Counts any Prefetch requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
1919         "Offcore": "1"
2020     },
2121     {
2222         "EventCode": "0xB7",
23
-        "MSRValue": "0x0080200070 ",
23
+        "MSRValue": "0x0080200070",
2424         "Counter": "0,1",
2525         "UMask": "0x1",
2626         "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.MCDRAM_NEAR",
....@@ -31,18 +31,18 @@
3131     },
3232     {
3333         "EventCode": "0xB7",
34
-        "MSRValue": "0x0101000070 ",
34
+        "MSRValue": "0x0101000070",
3535         "Counter": "0,1",
3636         "UMask": "0x1",
3737         "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.DDR_FAR",
3838         "MSRIndex": "0x1a6,0x1a7",
3939         "SampleAfterValue": "100007",
40
-        "BriefDescription": "Counts any Prefetch requests that accounts for data responses from DRAM Far. ",
40
+        "BriefDescription": "Counts any Prefetch requests that accounts for data responses from DRAM Far.",
4141         "Offcore": "1"
4242     },
4343     {
4444         "EventCode": "0xB7",
45
-        "MSRValue": "0x0080800070 ",
45
+        "MSRValue": "0x0080800070",
4646         "Counter": "0,1",
4747         "UMask": "0x1",
4848         "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.DDR_NEAR",
....@@ -53,18 +53,18 @@
5353     },
5454     {
5555         "EventCode": "0xB7",
56
-        "MSRValue": "0x01004032f7 ",
56
+        "MSRValue": "0x01004032f7",
5757         "Counter": "0,1",
5858         "UMask": "0x1",
5959         "EventName": "OFFCORE_RESPONSE.ANY_READ.MCDRAM_FAR",
6060         "MSRIndex": "0x1a6,0x1a7",
6161         "SampleAfterValue": "100007",
62
-        "BriefDescription": "Counts any Read request  that accounts for data responses from MCDRAM Far or Other tile L2 hit far. ",
62
+        "BriefDescription": "Counts any Read request  that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
6363         "Offcore": "1"
6464     },
6565     {
6666         "EventCode": "0xB7",
67
-        "MSRValue": "0x00802032f7 ",
67
+        "MSRValue": "0x00802032f7",
6868         "Counter": "0,1",
6969         "UMask": "0x1",
7070         "EventName": "OFFCORE_RESPONSE.ANY_READ.MCDRAM_NEAR",
....@@ -75,18 +75,18 @@
7575     },
7676     {
7777         "EventCode": "0xB7",
78
-        "MSRValue": "0x01010032f7 ",
78
+        "MSRValue": "0x01010032f7",
7979         "Counter": "0,1",
8080         "UMask": "0x1",
8181         "EventName": "OFFCORE_RESPONSE.ANY_READ.DDR_FAR",
8282         "MSRIndex": "0x1a6,0x1a7",
8383         "SampleAfterValue": "100007",
84
-        "BriefDescription": "Counts any Read request  that accounts for data responses from DRAM Far. ",
84
+        "BriefDescription": "Counts any Read request  that accounts for data responses from DRAM Far.",
8585         "Offcore": "1"
8686     },
8787     {
8888         "EventCode": "0xB7",
89
-        "MSRValue": "0x00808032f7 ",
89
+        "MSRValue": "0x00808032f7",
9090         "Counter": "0,1",
9191         "UMask": "0x1",
9292         "EventName": "OFFCORE_RESPONSE.ANY_READ.DDR_NEAR",
....@@ -97,18 +97,18 @@
9797     },
9898     {
9999         "EventCode": "0xB7",
100
-        "MSRValue": "0x0100400044 ",
100
+        "MSRValue": "0x0100400044",
101101         "Counter": "0,1",
102102         "UMask": "0x1",
103103         "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.MCDRAM_FAR",
104104         "MSRIndex": "0x1a6,0x1a7",
105105         "SampleAfterValue": "100007",
106
-        "BriefDescription": "Counts Demand code reads and prefetch code read requests  that accounts for data responses from MCDRAM Far or Other tile L2 hit far. ",
106
+        "BriefDescription": "Counts Demand code reads and prefetch code read requests  that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
107107         "Offcore": "1"
108108     },
109109     {
110110         "EventCode": "0xB7",
111
-        "MSRValue": "0x0080200044 ",
111
+        "MSRValue": "0x0080200044",
112112         "Counter": "0,1",
113113         "UMask": "0x1",
114114         "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.MCDRAM_NEAR",
....@@ -119,18 +119,18 @@
119119     },
120120     {
121121         "EventCode": "0xB7",
122
-        "MSRValue": "0x0101000044 ",
122
+        "MSRValue": "0x0101000044",
123123         "Counter": "0,1",
124124         "UMask": "0x1",
125125         "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.DDR_FAR",
126126         "MSRIndex": "0x1a6,0x1a7",
127127         "SampleAfterValue": "100007",
128
-        "BriefDescription": "Counts Demand code reads and prefetch code read requests  that accounts for data responses from DRAM Far. ",
128
+        "BriefDescription": "Counts Demand code reads and prefetch code read requests  that accounts for data responses from DRAM Far.",
129129         "Offcore": "1"
130130     },
131131     {
132132         "EventCode": "0xB7",
133
-        "MSRValue": "0x0080800044 ",
133
+        "MSRValue": "0x0080800044",
134134         "Counter": "0,1",
135135         "UMask": "0x1",
136136         "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.DDR_NEAR",
....@@ -141,18 +141,18 @@
141141     },
142142     {
143143         "EventCode": "0xB7",
144
-        "MSRValue": "0x0100400022 ",
144
+        "MSRValue": "0x0100400022",
145145         "Counter": "0,1",
146146         "UMask": "0x1",
147147         "EventName": "OFFCORE_RESPONSE.ANY_RFO.MCDRAM_FAR",
148148         "MSRIndex": "0x1a6,0x1a7",
149149         "SampleAfterValue": "100007",
150
-        "BriefDescription": "Counts Demand cacheable data write requests  that accounts for data responses from MCDRAM Far or Other tile L2 hit far. ",
150
+        "BriefDescription": "Counts Demand cacheable data write requests  that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
151151         "Offcore": "1"
152152     },
153153     {
154154         "EventCode": "0xB7",
155
-        "MSRValue": "0x0080200022 ",
155
+        "MSRValue": "0x0080200022",
156156         "Counter": "0,1",
157157         "UMask": "0x1",
158158         "EventName": "OFFCORE_RESPONSE.ANY_RFO.MCDRAM_NEAR",
....@@ -163,18 +163,18 @@
163163     },
164164     {
165165         "EventCode": "0xB7",
166
-        "MSRValue": "0x0101000022 ",
166
+        "MSRValue": "0x0101000022",
167167         "Counter": "0,1",
168168         "UMask": "0x1",
169169         "EventName": "OFFCORE_RESPONSE.ANY_RFO.DDR_FAR",
170170         "MSRIndex": "0x1a6,0x1a7",
171171         "SampleAfterValue": "100007",
172
-        "BriefDescription": "Counts Demand cacheable data write requests  that accounts for data responses from DRAM Far. ",
172
+        "BriefDescription": "Counts Demand cacheable data write requests  that accounts for data responses from DRAM Far.",
173173         "Offcore": "1"
174174     },
175175     {
176176         "EventCode": "0xB7",
177
-        "MSRValue": "0x0080800022 ",
177
+        "MSRValue": "0x0080800022",
178178         "Counter": "0,1",
179179         "UMask": "0x1",
180180         "EventName": "OFFCORE_RESPONSE.ANY_RFO.DDR_NEAR",
....@@ -185,18 +185,18 @@
185185     },
186186     {
187187         "EventCode": "0xB7",
188
-        "MSRValue": "0x0100403091 ",
188
+        "MSRValue": "0x0100403091",
189189         "Counter": "0,1",
190190         "UMask": "0x1",
191191         "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.MCDRAM_FAR",
192192         "MSRIndex": "0x1a6,0x1a7",
193193         "SampleAfterValue": "100007",
194
-        "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests  that accounts for data responses from MCDRAM Far or Other tile L2 hit far. ",
194
+        "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests  that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
195195         "Offcore": "1"
196196     },
197197     {
198198         "EventCode": "0xB7",
199
-        "MSRValue": "0x0080203091 ",
199
+        "MSRValue": "0x0080203091",
200200         "Counter": "0,1",
201201         "UMask": "0x1",
202202         "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.MCDRAM_NEAR",
....@@ -207,18 +207,18 @@
207207     },
208208     {
209209         "EventCode": "0xB7",
210
-        "MSRValue": "0x0101003091 ",
210
+        "MSRValue": "0x0101003091",
211211         "Counter": "0,1",
212212         "UMask": "0x1",
213213         "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.DDR_FAR",
214214         "MSRIndex": "0x1a6,0x1a7",
215215         "SampleAfterValue": "100007",
216
-        "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests  that accounts for data responses from DRAM Far. ",
216
+        "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests  that accounts for data responses from DRAM Far.",
217217         "Offcore": "1"
218218     },
219219     {
220220         "EventCode": "0xB7",
221
-        "MSRValue": "0x0080803091 ",
221
+        "MSRValue": "0x0080803091",
222222         "Counter": "0,1",
223223         "UMask": "0x1",
224224         "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.DDR_NEAR",
....@@ -229,18 +229,18 @@
229229     },
230230     {
231231         "EventCode": "0xB7",
232
-        "MSRValue": "0x0100408000 ",
232
+        "MSRValue": "0x0100408000",
233233         "Counter": "0,1",
234234         "UMask": "0x1",
235235         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.MCDRAM_FAR",
236236         "MSRIndex": "0x1a6,0x1a7",
237237         "SampleAfterValue": "100007",
238
-        "BriefDescription": "Counts any request that accounts for data responses from MCDRAM Far or Other tile L2 hit far. ",
238
+        "BriefDescription": "Counts any request that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
239239         "Offcore": "1"
240240     },
241241     {
242242         "EventCode": "0xB7",
243
-        "MSRValue": "0x0080208000 ",
243
+        "MSRValue": "0x0080208000",
244244         "Counter": "0,1",
245245         "UMask": "0x1",
246246         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.MCDRAM_NEAR",
....@@ -251,18 +251,18 @@
251251     },
252252     {
253253         "EventCode": "0xB7",
254
-        "MSRValue": "0x0101008000 ",
254
+        "MSRValue": "0x0101008000",
255255         "Counter": "0,1",
256256         "UMask": "0x1",
257257         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.DDR_FAR",
258258         "MSRIndex": "0x1a6,0x1a7",
259259         "SampleAfterValue": "100007",
260
-        "BriefDescription": "Counts any request that accounts for data responses from DRAM Far. ",
260
+        "BriefDescription": "Counts any request that accounts for data responses from DRAM Far.",
261261         "Offcore": "1"
262262     },
263263     {
264264         "EventCode": "0xB7",
265
-        "MSRValue": "0x0080808000 ",
265
+        "MSRValue": "0x0080808000",
266266         "Counter": "0,1",
267267         "UMask": "0x1",
268268         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.DDR_NEAR",
....@@ -273,18 +273,18 @@
273273     },
274274     {
275275         "EventCode": "0xB7",
276
-        "MSRValue": "0x0100402000 ",
276
+        "MSRValue": "0x0100402000",
277277         "Counter": "0,1",
278278         "UMask": "0x1",
279279         "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.MCDRAM_FAR",
280280         "MSRIndex": "0x1a6,0x1a7",
281281         "SampleAfterValue": "100007",
282
-        "BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far. ",
282
+        "BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
283283         "Offcore": "1"
284284     },
285285     {
286286         "EventCode": "0xB7",
287
-        "MSRValue": "0x0080202000 ",
287
+        "MSRValue": "0x0080202000",
288288         "Counter": "0,1",
289289         "UMask": "0x1",
290290         "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.MCDRAM_NEAR",
....@@ -295,18 +295,18 @@
295295     },
296296     {
297297         "EventCode": "0xB7",
298
-        "MSRValue": "0x0101002000 ",
298
+        "MSRValue": "0x0101002000",
299299         "Counter": "0,1",
300300         "UMask": "0x1",
301301         "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.DDR_FAR",
302302         "MSRIndex": "0x1a6,0x1a7",
303303         "SampleAfterValue": "100007",
304
-        "BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from DRAM Far. ",
304
+        "BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from DRAM Far.",
305305         "Offcore": "1"
306306     },
307307     {
308308         "EventCode": "0xB7",
309
-        "MSRValue": "0x0080802000 ",
309
+        "MSRValue": "0x0080802000",
310310         "Counter": "0,1",
311311         "UMask": "0x1",
312312         "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.DDR_NEAR",
....@@ -317,18 +317,18 @@
317317     },
318318     {
319319         "EventCode": "0xB7",
320
-        "MSRValue": "0x0100401000 ",
320
+        "MSRValue": "0x0100401000",
321321         "Counter": "0,1",
322322         "UMask": "0x1",
323323         "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.MCDRAM_FAR",
324324         "MSRIndex": "0x1a6,0x1a7",
325325         "SampleAfterValue": "100007",
326
-        "BriefDescription": "Counts Software Prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far. ",
326
+        "BriefDescription": "Counts Software Prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
327327         "Offcore": "1"
328328     },
329329     {
330330         "EventCode": "0xB7",
331
-        "MSRValue": "0x0080201000 ",
331
+        "MSRValue": "0x0080201000",
332332         "Counter": "0,1",
333333         "UMask": "0x1",
334334         "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.MCDRAM_NEAR",
....@@ -339,18 +339,18 @@
339339     },
340340     {
341341         "EventCode": "0xB7",
342
-        "MSRValue": "0x0101001000 ",
342
+        "MSRValue": "0x0101001000",
343343         "Counter": "0,1",
344344         "UMask": "0x1",
345345         "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.DDR_FAR",
346346         "MSRIndex": "0x1a6,0x1a7",
347347         "SampleAfterValue": "100007",
348
-        "BriefDescription": "Counts Software Prefetches that accounts for data responses from DRAM Far. ",
348
+        "BriefDescription": "Counts Software Prefetches that accounts for data responses from DRAM Far.",
349349         "Offcore": "1"
350350     },
351351     {
352352         "EventCode": "0xB7",
353
-        "MSRValue": "0x0080801000 ",
353
+        "MSRValue": "0x0080801000",
354354         "Counter": "0,1",
355355         "UMask": "0x1",
356356         "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.DDR_NEAR",
....@@ -361,18 +361,18 @@
361361     },
362362     {
363363         "EventCode": "0xB7",
364
-        "MSRValue": "0x0100400400 ",
364
+        "MSRValue": "0x0100400400",
365365         "Counter": "0,1",
366366         "UMask": "0x1",
367367         "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.MCDRAM_FAR",
368368         "MSRIndex": "0x1a6,0x1a7",
369369         "SampleAfterValue": "100007",
370
-        "BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far. ",
370
+        "BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
371371         "Offcore": "1"
372372     },
373373     {
374374         "EventCode": "0xB7",
375
-        "MSRValue": "0x0080200400 ",
375
+        "MSRValue": "0x0080200400",
376376         "Counter": "0,1",
377377         "UMask": "0x1",
378378         "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.MCDRAM_NEAR",
....@@ -383,18 +383,18 @@
383383     },
384384     {
385385         "EventCode": "0xB7",
386
-        "MSRValue": "0x0101000400 ",
386
+        "MSRValue": "0x0101000400",
387387         "Counter": "0,1",
388388         "UMask": "0x1",
389389         "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.DDR_FAR",
390390         "MSRIndex": "0x1a6,0x1a7",
391391         "SampleAfterValue": "100007",
392
-        "BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from DRAM Far. ",
392
+        "BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from DRAM Far.",
393393         "Offcore": "1"
394394     },
395395     {
396396         "EventCode": "0xB7",
397
-        "MSRValue": "0x0080800400 ",
397
+        "MSRValue": "0x0080800400",
398398         "Counter": "0,1",
399399         "UMask": "0x1",
400400         "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.DDR_NEAR",
....@@ -405,18 +405,18 @@
405405     },
406406     {
407407         "EventCode": "0xB7",
408
-        "MSRValue": "0x0100400200 ",
408
+        "MSRValue": "0x0100400200",
409409         "Counter": "0,1",
410410         "UMask": "0x1",
411411         "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.MCDRAM_FAR",
412412         "MSRIndex": "0x1a6,0x1a7",
413413         "SampleAfterValue": "100007",
414
-        "BriefDescription": "Counts UC code reads (valid only for Outstanding response type)  that accounts for data responses from MCDRAM Far or Other tile L2 hit far. ",
414
+        "BriefDescription": "Counts UC code reads (valid only for Outstanding response type)  that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
415415         "Offcore": "1"
416416     },
417417     {
418418         "EventCode": "0xB7",
419
-        "MSRValue": "0x0080200200 ",
419
+        "MSRValue": "0x0080200200",
420420         "Counter": "0,1",
421421         "UMask": "0x1",
422422         "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.MCDRAM_NEAR",
....@@ -427,18 +427,18 @@
427427     },
428428     {
429429         "EventCode": "0xB7",
430
-        "MSRValue": "0x0101000200 ",
430
+        "MSRValue": "0x0101000200",
431431         "Counter": "0,1",
432432         "UMask": "0x1",
433433         "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.DDR_FAR",
434434         "MSRIndex": "0x1a6,0x1a7",
435435         "SampleAfterValue": "100007",
436
-        "BriefDescription": "Counts UC code reads (valid only for Outstanding response type)  that accounts for data responses from DRAM Far. ",
436
+        "BriefDescription": "Counts UC code reads (valid only for Outstanding response type)  that accounts for data responses from DRAM Far.",
437437         "Offcore": "1"
438438     },
439439     {
440440         "EventCode": "0xB7",
441
-        "MSRValue": "0x0080800200 ",
441
+        "MSRValue": "0x0080800200",
442442         "Counter": "0,1",
443443         "UMask": "0x1",
444444         "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.DDR_NEAR",
....@@ -449,18 +449,18 @@
449449     },
450450     {
451451         "EventCode": "0xB7",
452
-        "MSRValue": "0x0100400100 ",
452
+        "MSRValue": "0x0100400100",
453453         "Counter": "0,1",
454454         "UMask": "0x1",
455455         "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.MCDRAM_FAR",
456456         "MSRIndex": "0x1a7",
457457         "SampleAfterValue": "100007",
458
-        "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from MCDRAM Far or Other tile L2 hit far. ",
458
+        "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
459459         "Offcore": "1"
460460     },
461461     {
462462         "EventCode": "0xB7",
463
-        "MSRValue": "0x0080200100 ",
463
+        "MSRValue": "0x0080200100",
464464         "Counter": "0,1",
465465         "UMask": "0x1",
466466         "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.MCDRAM_NEAR",
....@@ -471,18 +471,18 @@
471471     },
472472     {
473473         "EventCode": "0xB7",
474
-        "MSRValue": "0x0101000100 ",
474
+        "MSRValue": "0x0101000100",
475475         "Counter": "0,1",
476476         "UMask": "0x1",
477477         "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.DDR_FAR",
478478         "MSRIndex": "0x1a7",
479479         "SampleAfterValue": "100007",
480
-        "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from DRAM Far. ",
480
+        "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from DRAM Far.",
481481         "Offcore": "1"
482482     },
483483     {
484484         "EventCode": "0xB7",
485
-        "MSRValue": "0x0080800100 ",
485
+        "MSRValue": "0x0080800100",
486486         "Counter": "0,1",
487487         "UMask": "0x1",
488488         "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.DDR_NEAR",
....@@ -493,7 +493,7 @@
493493     },
494494     {
495495         "EventCode": "0xB7",
496
-        "MSRValue": "0x2000020080 ",
496
+        "MSRValue": "0x2000020080",
497497         "Counter": "0,1",
498498         "UMask": "0x1",
499499         "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.NON_DRAM",
....@@ -504,18 +504,18 @@
504504     },
505505     {
506506         "EventCode": "0xB7",
507
-        "MSRValue": "0x0100400080 ",
507
+        "MSRValue": "0x0100400080",
508508         "Counter": "0,1",
509509         "UMask": "0x1",
510510         "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.MCDRAM_FAR",
511511         "MSRIndex": "0x1a6,0x1a7",
512512         "SampleAfterValue": "100007",
513
-        "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for data responses from MCDRAM Far or Other tile L2 hit far. ",
513
+        "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
514514         "Offcore": "1"
515515     },
516516     {
517517         "EventCode": "0xB7",
518
-        "MSRValue": "0x0080200080 ",
518
+        "MSRValue": "0x0080200080",
519519         "Counter": "0,1",
520520         "UMask": "0x1",
521521         "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.MCDRAM_NEAR",
....@@ -526,18 +526,18 @@
526526     },
527527     {
528528         "EventCode": "0xB7",
529
-        "MSRValue": "0x0101000080 ",
529
+        "MSRValue": "0x0101000080",
530530         "Counter": "0,1",
531531         "UMask": "0x1",
532532         "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.DDR_FAR",
533533         "MSRIndex": "0x1a6,0x1a7",
534534         "SampleAfterValue": "100007",
535
-        "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for data responses from DRAM Far. ",
535
+        "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type).  that accounts for data responses from DRAM Far.",
536536         "Offcore": "1"
537537     },
538538     {
539539         "EventCode": "0xB7",
540
-        "MSRValue": "0x0080800080 ",
540
+        "MSRValue": "0x0080800080",
541541         "Counter": "0,1",
542542         "UMask": "0x1",
543543         "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.DDR_NEAR",
....@@ -548,18 +548,18 @@
548548     },
549549     {
550550         "EventCode": "0xB7",
551
-        "MSRValue": "0x0100400040 ",
551
+        "MSRValue": "0x0100400040",
552552         "Counter": "0,1",
553553         "UMask": "0x1",
554554         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.MCDRAM_FAR",
555555         "MSRIndex": "0x1a6,0x1a7",
556556         "SampleAfterValue": "100007",
557
-        "BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far. ",
557
+        "BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
558558         "Offcore": "1"
559559     },
560560     {
561561         "EventCode": "0xB7",
562
-        "MSRValue": "0x0080200040 ",
562
+        "MSRValue": "0x0080200040",
563563         "Counter": "0,1",
564564         "UMask": "0x1",
565565         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.MCDRAM_NEAR",
....@@ -570,18 +570,18 @@
570570     },
571571     {
572572         "EventCode": "0xB7",
573
-        "MSRValue": "0x0101000040 ",
573
+        "MSRValue": "0x0101000040",
574574         "Counter": "0,1",
575575         "UMask": "0x1",
576576         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.DDR_FAR",
577577         "MSRIndex": "0x1a6,0x1a7",
578578         "SampleAfterValue": "100007",
579
-        "BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from DRAM Far. ",
579
+        "BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from DRAM Far.",
580580         "Offcore": "1"
581581     },
582582     {
583583         "EventCode": "0xB7",
584
-        "MSRValue": "0x0080800040 ",
584
+        "MSRValue": "0x0080800040",
585585         "Counter": "0,1",
586586         "UMask": "0x1",
587587         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.DDR_NEAR",
....@@ -592,7 +592,7 @@
592592     },
593593     {
594594         "EventCode": "0xB7",
595
-        "MSRValue": "0x2000020020 ",
595
+        "MSRValue": "0x2000020020",
596596         "Counter": "0,1",
597597         "UMask": "0x1",
598598         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.NON_DRAM",
....@@ -603,18 +603,18 @@
603603     },
604604     {
605605         "EventCode": "0xB7",
606
-        "MSRValue": "0x0100400020 ",
606
+        "MSRValue": "0x0100400020",
607607         "Counter": "0,1",
608608         "UMask": "0x1",
609609         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.MCDRAM_FAR",
610610         "MSRIndex": "0x1a6,0x1a7",
611611         "SampleAfterValue": "100007",
612
-        "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from MCDRAM Far or Other tile L2 hit far. ",
612
+        "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
613613         "Offcore": "1"
614614     },
615615     {
616616         "EventCode": "0xB7",
617
-        "MSRValue": "0x0080200020 ",
617
+        "MSRValue": "0x0080200020",
618618         "Counter": "0,1",
619619         "UMask": "0x1",
620620         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.MCDRAM_NEAR",
....@@ -625,18 +625,18 @@
625625     },
626626     {
627627         "EventCode": "0xB7",
628
-        "MSRValue": "0x0101000020 ",
628
+        "MSRValue": "0x0101000020",
629629         "Counter": "0,1",
630630         "UMask": "0x1",
631631         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.DDR_FAR",
632632         "MSRIndex": "0x1a6,0x1a7",
633633         "SampleAfterValue": "100007",
634
-        "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from DRAM Far. ",
634
+        "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from DRAM Far.",
635635         "Offcore": "1"
636636     },
637637     {
638638         "EventCode": "0xB7",
639
-        "MSRValue": "0x0080800020 ",
639
+        "MSRValue": "0x0080800020",
640640         "Counter": "0,1",
641641         "UMask": "0x1",
642642         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.DDR_NEAR",
....@@ -647,18 +647,18 @@
647647     },
648648     {
649649         "EventCode": "0xB7",
650
-        "MSRValue": "0x0100400004 ",
650
+        "MSRValue": "0x0100400004",
651651         "Counter": "0,1",
652652         "UMask": "0x1",
653653         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.MCDRAM_FAR",
654654         "MSRIndex": "0x1a6,0x1a7",
655655         "SampleAfterValue": "100007",
656
-        "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from MCDRAM Far or Other tile L2 hit far. ",
656
+        "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
657657         "Offcore": "1"
658658     },
659659     {
660660         "EventCode": "0xB7",
661
-        "MSRValue": "0x0080200004 ",
661
+        "MSRValue": "0x0080200004",
662662         "Counter": "0,1",
663663         "UMask": "0x1",
664664         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.MCDRAM_NEAR",
....@@ -669,18 +669,18 @@
669669     },
670670     {
671671         "EventCode": "0xB7",
672
-        "MSRValue": "0x0101000004 ",
672
+        "MSRValue": "0x0101000004",
673673         "Counter": "0,1",
674674         "UMask": "0x1",
675675         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.DDR_FAR",
676676         "MSRIndex": "0x1a6,0x1a7",
677677         "SampleAfterValue": "100007",
678
-        "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from DRAM Far. ",
678
+        "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from DRAM Far.",
679679         "Offcore": "1"
680680     },
681681     {
682682         "EventCode": "0xB7",
683
-        "MSRValue": "0x0080800004 ",
683
+        "MSRValue": "0x0080800004",
684684         "Counter": "0,1",
685685         "UMask": "0x1",
686686         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.DDR_NEAR",
....@@ -691,18 +691,18 @@
691691     },
692692     {
693693         "EventCode": "0xB7",
694
-        "MSRValue": "0x0100400002 ",
694
+        "MSRValue": "0x0100400002",
695695         "Counter": "0,1",
696696         "UMask": "0x1",
697697         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.MCDRAM_FAR",
698698         "MSRIndex": "0x1a6,0x1a7",
699699         "SampleAfterValue": "100007",
700
-        "BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from MCDRAM Far or Other tile L2 hit far. ",
700
+        "BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
701701         "Offcore": "1"
702702     },
703703     {
704704         "EventCode": "0xB7",
705
-        "MSRValue": "0x0080200002 ",
705
+        "MSRValue": "0x0080200002",
706706         "Counter": "0,1",
707707         "UMask": "0x1",
708708         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.MCDRAM_NEAR",
....@@ -713,18 +713,18 @@
713713     },
714714     {
715715         "EventCode": "0xB7",
716
-        "MSRValue": "0x0101000002 ",
716
+        "MSRValue": "0x0101000002",
717717         "Counter": "0,1",
718718         "UMask": "0x1",
719719         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.DDR_FAR",
720720         "MSRIndex": "0x1a6,0x1a7",
721721         "SampleAfterValue": "100007",
722
-        "BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from DRAM Far. ",
722
+        "BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from DRAM Far.",
723723         "Offcore": "1"
724724     },
725725     {
726726         "EventCode": "0xB7",
727
-        "MSRValue": "0x0080800002 ",
727
+        "MSRValue": "0x0080800002",
728728         "Counter": "0,1",
729729         "UMask": "0x1",
730730         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.DDR_NEAR",
....@@ -735,18 +735,18 @@
735735     },
736736     {
737737         "EventCode": "0xB7",
738
-        "MSRValue": "0x0100400001 ",
738
+        "MSRValue": "0x0100400001",
739739         "Counter": "0,1",
740740         "UMask": "0x1",
741741         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.MCDRAM_FAR",
742742         "MSRIndex": "0x1a6,0x1a7",
743743         "SampleAfterValue": "100007",
744
-        "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from MCDRAM Far or Other tile L2 hit far. ",
744
+        "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from MCDRAM Far or Other tile L2 hit far.",
745745         "Offcore": "1"
746746     },
747747     {
748748         "EventCode": "0xB7",
749
-        "MSRValue": "0x0080200001 ",
749
+        "MSRValue": "0x0080200001",
750750         "Counter": "0,1",
751751         "UMask": "0x1",
752752         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.MCDRAM_NEAR",
....@@ -757,18 +757,18 @@
757757     },
758758     {
759759         "EventCode": "0xB7",
760
-        "MSRValue": "0x0101000001 ",
760
+        "MSRValue": "0x0101000001",
761761         "Counter": "0,1",
762762         "UMask": "0x1",
763763         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.DDR_FAR",
764764         "MSRIndex": "0x1a6,0x1a7",
765765         "SampleAfterValue": "100007",
766
-        "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from DRAM Far. ",
766
+        "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from DRAM Far.",
767767         "Offcore": "1"
768768     },
769769     {
770770         "EventCode": "0xB7",
771
-        "MSRValue": "0x0080800001 ",
771
+        "MSRValue": "0x0080800001",
772772         "Counter": "0,1",
773773         "UMask": "0x1",
774774         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.DDR_NEAR",
....@@ -779,7 +779,7 @@
779779     },
780780     {
781781         "EventCode": "0xB7",
782
-        "MSRValue": "0x0180600001 ",
782
+        "MSRValue": "0x0180600001",
783783         "Counter": "0,1",
784784         "UMask": "0x1",
785785         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.MCDRAM",
....@@ -790,7 +790,7 @@
790790     },
791791     {
792792         "EventCode": "0xB7",
793
-        "MSRValue": "0x0180600002 ",
793
+        "MSRValue": "0x0180600002",
794794         "Counter": "0,1",
795795         "UMask": "0x1",
796796         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.MCDRAM",
....@@ -801,7 +801,7 @@
801801     },
802802     {
803803         "EventCode": "0xB7",
804
-        "MSRValue": "0x0180600004 ",
804
+        "MSRValue": "0x0180600004",
805805         "Counter": "0,1",
806806         "UMask": "0x1",
807807         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.MCDRAM",
....@@ -812,7 +812,7 @@
812812     },
813813     {
814814         "EventCode": "0xB7",
815
-        "MSRValue": "0x0180600020 ",
815
+        "MSRValue": "0x0180600020",
816816         "Counter": "0,1",
817817         "UMask": "0x1",
818818         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.MCDRAM",
....@@ -823,7 +823,7 @@
823823     },
824824     {
825825         "EventCode": "0xB7",
826
-        "MSRValue": "0x0180600080 ",
826
+        "MSRValue": "0x0180600080",
827827         "Counter": "0,1",
828828         "UMask": "0x1",
829829         "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.MCDRAM",
....@@ -834,7 +834,7 @@
834834     },
835835     {
836836         "EventCode": "0xB7",
837
-        "MSRValue": "0x0180600100 ",
837
+        "MSRValue": "0x0180600100",
838838         "Counter": "0,1",
839839         "UMask": "0x1",
840840         "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.MCDRAM",
....@@ -845,7 +845,7 @@
845845     },
846846     {
847847         "EventCode": "0xB7",
848
-        "MSRValue": "0x0180600200 ",
848
+        "MSRValue": "0x0180600200",
849849         "Counter": "0,1",
850850         "UMask": "0x1",
851851         "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.MCDRAM",
....@@ -856,7 +856,7 @@
856856     },
857857     {
858858         "EventCode": "0xB7",
859
-        "MSRValue": "0x0180600400 ",
859
+        "MSRValue": "0x0180600400",
860860         "Counter": "0,1",
861861         "UMask": "0x1",
862862         "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.MCDRAM",
....@@ -867,7 +867,7 @@
867867     },
868868     {
869869         "EventCode": "0xB7",
870
-        "MSRValue": "0x0180601000 ",
870
+        "MSRValue": "0x0180601000",
871871         "Counter": "0,1",
872872         "UMask": "0x1",
873873         "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.MCDRAM",
....@@ -878,7 +878,7 @@
878878     },
879879     {
880880         "EventCode": "0xB7",
881
-        "MSRValue": "0x0180608000 ",
881
+        "MSRValue": "0x0180608000",
882882         "Counter": "0,1",
883883         "UMask": "0x1",
884884         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.MCDRAM",
....@@ -889,7 +889,7 @@
889889     },
890890     {
891891         "EventCode": "0xB7",
892
-        "MSRValue": "0x0180603091 ",
892
+        "MSRValue": "0x0180603091",
893893         "Counter": "0,1",
894894         "UMask": "0x1",
895895         "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.MCDRAM",
....@@ -900,7 +900,7 @@
900900     },
901901     {
902902         "EventCode": "0xB7",
903
-        "MSRValue": "0x0180600022 ",
903
+        "MSRValue": "0x0180600022",
904904         "Counter": "0,1",
905905         "UMask": "0x1",
906906         "EventName": "OFFCORE_RESPONSE.ANY_RFO.MCDRAM",
....@@ -911,7 +911,7 @@
911911     },
912912     {
913913         "EventCode": "0xB7",
914
-        "MSRValue": "0x0180600044 ",
914
+        "MSRValue": "0x0180600044",
915915         "Counter": "0,1",
916916         "UMask": "0x1",
917917         "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.MCDRAM",
....@@ -922,7 +922,7 @@
922922     },
923923     {
924924         "EventCode": "0xB7",
925
-        "MSRValue": "0x01806032f7 ",
925
+        "MSRValue": "0x01806032f7",
926926         "Counter": "0,1",
927927         "UMask": "0x1",
928928         "EventName": "OFFCORE_RESPONSE.ANY_READ.MCDRAM",
....@@ -933,7 +933,7 @@
933933     },
934934     {
935935         "EventCode": "0xB7",
936
-        "MSRValue": "0x0180600070 ",
936
+        "MSRValue": "0x0180600070",
937937         "Counter": "0,1",
938938         "UMask": "0x1",
939939         "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.MCDRAM",
....@@ -944,7 +944,7 @@
944944     },
945945     {
946946         "EventCode": "0xB7",
947
-        "MSRValue": "0x0181800001 ",
947
+        "MSRValue": "0x0181800001",
948948         "Counter": "0,1",
949949         "UMask": "0x1",
950950         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.DDR",
....@@ -955,7 +955,7 @@
955955     },
956956     {
957957         "EventCode": "0xB7",
958
-        "MSRValue": "0x0181800002 ",
958
+        "MSRValue": "0x0181800002",
959959         "Counter": "0,1",
960960         "UMask": "0x1",
961961         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.DDR",
....@@ -966,7 +966,7 @@
966966     },
967967     {
968968         "EventCode": "0xB7",
969
-        "MSRValue": "0x0181800004 ",
969
+        "MSRValue": "0x0181800004",
970970         "Counter": "0,1",
971971         "UMask": "0x1",
972972         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.DDR",
....@@ -977,7 +977,7 @@
977977     },
978978     {
979979         "EventCode": "0xB7",
980
-        "MSRValue": "0x0181800020 ",
980
+        "MSRValue": "0x0181800020",
981981         "Counter": "0,1",
982982         "UMask": "0x1",
983983         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.DDR",
....@@ -988,7 +988,7 @@
988988     },
989989     {
990990         "EventCode": "0xB7",
991
-        "MSRValue": "0x0181800040 ",
991
+        "MSRValue": "0x0181800040",
992992         "Counter": "0,1",
993993         "UMask": "0x1",
994994         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.DDR",
....@@ -999,7 +999,7 @@
999999     },
10001000     {
10011001         "EventCode": "0xB7",
1002
-        "MSRValue": "0x0181800080 ",
1002
+        "MSRValue": "0x0181800080",
10031003         "Counter": "0,1",
10041004         "UMask": "0x1",
10051005         "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.DDR",
....@@ -1010,7 +1010,7 @@
10101010     },
10111011     {
10121012         "EventCode": "0xB7",
1013
-        "MSRValue": "0x0181800200 ",
1013
+        "MSRValue": "0x0181800200",
10141014         "Counter": "0,1",
10151015         "UMask": "0x1",
10161016         "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.DDR",
....@@ -1021,7 +1021,7 @@
10211021     },
10221022     {
10231023         "EventCode": "0xB7",
1024
-        "MSRValue": "0x0181800400 ",
1024
+        "MSRValue": "0x0181800400",
10251025         "Counter": "0,1",
10261026         "UMask": "0x1",
10271027         "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.DDR",
....@@ -1032,7 +1032,7 @@
10321032     },
10331033     {
10341034         "EventCode": "0xB7",
1035
-        "MSRValue": "0x0181801000 ",
1035
+        "MSRValue": "0x0181801000",
10361036         "Counter": "0,1",
10371037         "UMask": "0x1",
10381038         "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.DDR",
....@@ -1043,7 +1043,7 @@
10431043     },
10441044     {
10451045         "EventCode": "0xB7",
1046
-        "MSRValue": "0x0181802000 ",
1046
+        "MSRValue": "0x0181802000",
10471047         "Counter": "0,1",
10481048         "UMask": "0x1",
10491049         "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.DDR",
....@@ -1054,7 +1054,7 @@
10541054     },
10551055     {
10561056         "EventCode": "0xB7",
1057
-        "MSRValue": "0x0181808000 ",
1057
+        "MSRValue": "0x0181808000",
10581058         "Counter": "0,1",
10591059         "UMask": "0x1",
10601060         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.DDR",
....@@ -1065,7 +1065,7 @@
10651065     },
10661066     {
10671067         "EventCode": "0xB7",
1068
-        "MSRValue": "0x0181803091 ",
1068
+        "MSRValue": "0x0181803091",
10691069         "Counter": "0,1",
10701070         "UMask": "0x1",
10711071         "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.DDR",
....@@ -1076,7 +1076,7 @@
10761076     },
10771077     {
10781078         "EventCode": "0xB7",
1079
-        "MSRValue": "0x0181800022 ",
1079
+        "MSRValue": "0x0181800022",
10801080         "Counter": "0,1",
10811081         "UMask": "0x1",
10821082         "EventName": "OFFCORE_RESPONSE.ANY_RFO.DDR",
....@@ -1087,7 +1087,7 @@
10871087     },
10881088     {
10891089         "EventCode": "0xB7",
1090
-        "MSRValue": "0x0181800044 ",
1090
+        "MSRValue": "0x0181800044",
10911091         "Counter": "0,1",
10921092         "UMask": "0x1",
10931093         "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.DDR",
....@@ -1098,7 +1098,7 @@
10981098     },
10991099     {
11001100         "EventCode": "0xB7",
1101
-        "MSRValue": "0x01818032f7 ",
1101
+        "MSRValue": "0x01818032f7",
11021102         "Counter": "0,1",
11031103         "UMask": "0x1",
11041104         "EventName": "OFFCORE_RESPONSE.ANY_READ.DDR",