disable pwm7

hc

2024-05-10 23fa18eaa71266feff7ba8d83022d9e1cc83c65a

 kernel/tools/perf/pmu-events/arch/x86/haswell/memory.json
..
..
@@ -298,7 +298,7 @@
298
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         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
299
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         "MSRIndex": "0x3F6",
300
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         "SampleAfterValue": "100003",
301
-        "BriefDescription": "Loads with latency value being above 4.",
301
+        "BriefDescription": "Randomly selected loads with latency value being above 4.",
302
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         "TakenAlone": "1",
303
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         "CounterHTOff": "3"
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     },
..
..
@@ -312,7 +312,7 @@
312
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         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
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         "MSRIndex": "0x3F6",
314
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         "SampleAfterValue": "50021",
315
-        "BriefDescription": "Loads with latency value being above 8.",
315
+        "BriefDescription": "Randomly selected loads with latency value being above 8.",
316
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         "TakenAlone": "1",
317
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         "CounterHTOff": "3"
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     },
..
..
@@ -326,7 +326,7 @@
326
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         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
327
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         "MSRIndex": "0x3F6",
328
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         "SampleAfterValue": "20011",
329
-        "BriefDescription": "Loads with latency value being above 16.",
329
+        "BriefDescription": "Randomly selected loads with latency value being above 16.",
330
330
         "TakenAlone": "1",
331
331
         "CounterHTOff": "3"
332
332
     },
..
..
@@ -340,7 +340,7 @@
340
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         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
341
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         "MSRIndex": "0x3F6",
342
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         "SampleAfterValue": "100003",
343
-        "BriefDescription": "Loads with latency value being above 32.",
343
+        "BriefDescription": "Randomly selected loads with latency value being above 32.",
344
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         "TakenAlone": "1",
345
345
         "CounterHTOff": "3"
346
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     },
..
..
@@ -354,7 +354,7 @@
354
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         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
355
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         "MSRIndex": "0x3F6",
356
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         "SampleAfterValue": "2003",
357
-        "BriefDescription": "Loads with latency value being above 64.",
357
+        "BriefDescription": "Randomly selected loads with latency value being above 64.",
358
358
         "TakenAlone": "1",
359
359
         "CounterHTOff": "3"
360
360
     },
..
..
@@ -368,7 +368,7 @@
368
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         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
369
369
         "MSRIndex": "0x3F6",
370
370
         "SampleAfterValue": "1009",
371
-        "BriefDescription": "Loads with latency value being above 128.",
371
+        "BriefDescription": "Randomly selected loads with latency value being above 128.",
372
372
         "TakenAlone": "1",
373
373
         "CounterHTOff": "3"
374
374
     },
..
..
@@ -382,7 +382,7 @@
382
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         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
383
383
         "MSRIndex": "0x3F6",
384
384
         "SampleAfterValue": "503",
385
-        "BriefDescription": "Loads with latency value being above 256.",
385
+        "BriefDescription": "Randomly selected loads with latency value being above 256.",
386
386
         "TakenAlone": "1",
387
387
         "CounterHTOff": "3"
388
388
     },
..
..
@@ -396,280 +396,280 @@
396
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         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
397
397
         "MSRIndex": "0x3F6",
398
398
         "SampleAfterValue": "101",
399
-        "BriefDescription": "Loads with latency value being above 512.",
399
+        "BriefDescription": "Randomly selected loads with latency value being above 512.",
400
400
         "TakenAlone": "1",
401
401
         "CounterHTOff": "3"
402
402
     },
403
403
     {
404
-        "PublicDescription": "Counts all requests that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
404
+        "PublicDescription": "Counts all requests miss in the L3",
405
405
         "EventCode": "0xB7, 0xBB",
406
-        "MSRValue": "0x3fffc08fff",
406
+        "MSRValue": "0x3FFFC08FFF",
407
407
         "Counter": "0,1,2,3",
408
408
         "UMask": "0x1",
409
409
         "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.L3_MISS.ANY_RESPONSE",
410
-        "MSRIndex": "0x1a6,0x1a7",
410
+        "MSRIndex": "0x1a6, 0x1a7",
411
411
         "SampleAfterValue": "100003",
412
-        "BriefDescription": "Counts all requests that miss in the L3",
412
+        "BriefDescription": "Counts all requests miss in the L3",
413
413
         "Offcore": "1",
414
414
         "CounterHTOff": "0,1,2,3"
415
415
     },
416
416
     {
417
-        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
417
+        "PublicDescription": "miss the L3 and the data is returned from local dram",
418
418
         "EventCode": "0xB7, 0xBB",
419
-        "MSRValue": "0x01004007f7",
419
+        "MSRValue": "0x01004007F7",
420
420
         "Counter": "0,1,2,3",
421
421
         "UMask": "0x1",
422
422
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.LOCAL_DRAM",
423
-        "MSRIndex": "0x1a6,0x1a7",
423
+        "MSRIndex": "0x1a6, 0x1a7",
424
424
         "SampleAfterValue": "100003",
425
-        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the L3 and the data is returned from local dram",
425
+        "BriefDescription": "miss the L3 and the data is returned from local dram",
426
426
         "Offcore": "1",
427
427
         "CounterHTOff": "0,1,2,3"
428
428
     },
429
429
     {
430
-        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
430
+        "PublicDescription": "miss in the L3",
431
431
         "EventCode": "0xB7, 0xBB",
432
-        "MSRValue": "0x3fffc007f7",
432
+        "MSRValue": "0x3FFFC007F7",
433
433
         "Counter": "0,1,2,3",
434
434
         "UMask": "0x1",
435
435
         "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.ANY_RESPONSE",
436
-        "MSRIndex": "0x1a6,0x1a7",
436
+        "MSRIndex": "0x1a6, 0x1a7",
437
437
         "SampleAfterValue": "100003",
438
-        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss in the L3",
438
+        "BriefDescription": "miss in the L3",
439
439
         "Offcore": "1",
440
440
         "CounterHTOff": "0,1,2,3"
441
441
     },
442
442
     {
443
-        "PublicDescription": "Counts all demand & prefetch code reads that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
443
+        "PublicDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram",
444
444
         "EventCode": "0xB7, 0xBB",
445
445
         "MSRValue": "0x0100400244",
446
446
         "Counter": "0,1,2,3",
447
447
         "UMask": "0x1",
448
448
         "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.L3_MISS.LOCAL_DRAM",
449
-        "MSRIndex": "0x1a6,0x1a7",
449
+        "MSRIndex": "0x1a6, 0x1a7",
450
450
         "SampleAfterValue": "100003",
451
-        "BriefDescription": "Counts all demand & prefetch code reads that miss the L3 and the data is returned from local dram",
451
+        "BriefDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram",
452
452
         "Offcore": "1",
453
453
         "CounterHTOff": "0,1,2,3"
454
454
     },
455
455
     {
456
-        "PublicDescription": "Counts all demand & prefetch code reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
456
+        "PublicDescription": "Counts all demand & prefetch code reads miss in the L3",
457
457
         "EventCode": "0xB7, 0xBB",
458
-        "MSRValue": "0x3fffc00244",
458
+        "MSRValue": "0x3FFFC00244",
459
459
         "Counter": "0,1,2,3",
460
460
         "UMask": "0x1",
461
461
         "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.L3_MISS.ANY_RESPONSE",
462
-        "MSRIndex": "0x1a6,0x1a7",
462
+        "MSRIndex": "0x1a6, 0x1a7",
463
463
         "SampleAfterValue": "100003",
464
-        "BriefDescription": "Counts all demand & prefetch code reads that miss in the L3",
464
+        "BriefDescription": "Counts all demand & prefetch code reads miss in the L3",
465
465
         "Offcore": "1",
466
466
         "CounterHTOff": "0,1,2,3"
467
467
     },
468
468
     {
469
-        "PublicDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
469
+        "PublicDescription": "Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram",
470
470
         "EventCode": "0xB7, 0xBB",
471
471
         "MSRValue": "0x0100400122",
472
472
         "Counter": "0,1,2,3",
473
473
         "UMask": "0x1",
474
474
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.LOCAL_DRAM",
475
-        "MSRIndex": "0x1a6,0x1a7",
475
+        "MSRIndex": "0x1a6, 0x1a7",
476
476
         "SampleAfterValue": "100003",
477
-        "BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned from local dram",
477
+        "BriefDescription": "Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram",
478
478
         "Offcore": "1",
479
479
         "CounterHTOff": "0,1,2,3"
480
480
     },
481
481
     {
482
-        "PublicDescription": "Counts all demand & prefetch RFOs that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
482
+        "PublicDescription": "Counts all demand & prefetch RFOs miss in the L3",
483
483
         "EventCode": "0xB7, 0xBB",
484
-        "MSRValue": "0x3fffc00122",
484
+        "MSRValue": "0x3FFFC00122",
485
485
         "Counter": "0,1,2,3",
486
486
         "UMask": "0x1",
487
487
         "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.ANY_RESPONSE",
488
-        "MSRIndex": "0x1a6,0x1a7",
488
+        "MSRIndex": "0x1a6, 0x1a7",
489
489
         "SampleAfterValue": "100003",
490
-        "BriefDescription": "Counts all demand & prefetch RFOs that miss in the L3",
490
+        "BriefDescription": "Counts all demand & prefetch RFOs miss in the L3",
491
491
         "Offcore": "1",
492
492
         "CounterHTOff": "0,1,2,3"
493
493
     },
494
494
     {
495
-        "PublicDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
495
+        "PublicDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram",
496
496
         "EventCode": "0xB7, 0xBB",
497
497
         "MSRValue": "0x0100400091",
498
498
         "Counter": "0,1,2,3",
499
499
         "UMask": "0x1",
500
500
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.LOCAL_DRAM",
501
-        "MSRIndex": "0x1a6,0x1a7",
501
+        "MSRIndex": "0x1a6, 0x1a7",
502
502
         "SampleAfterValue": "100003",
503
-        "BriefDescription": "Counts all demand & prefetch data reads that miss the L3 and the data is returned from local dram",
503
+        "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram",
504
504
         "Offcore": "1",
505
505
         "CounterHTOff": "0,1,2,3"
506
506
     },
507
507
     {
508
-        "PublicDescription": "Counts all demand & prefetch data reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
508
+        "PublicDescription": "Counts all demand & prefetch data reads miss in the L3",
509
509
         "EventCode": "0xB7, 0xBB",
510
-        "MSRValue": "0x3fffc00091",
510
+        "MSRValue": "0x3FFFC00091",
511
511
         "Counter": "0,1,2,3",
512
512
         "UMask": "0x1",
513
513
         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.ANY_RESPONSE",
514
-        "MSRIndex": "0x1a6,0x1a7",
514
+        "MSRIndex": "0x1a6, 0x1a7",
515
515
         "SampleAfterValue": "100003",
516
-        "BriefDescription": "Counts all demand & prefetch data reads that miss in the L3",
516
+        "BriefDescription": "Counts all demand & prefetch data reads miss in the L3",
517
517
         "Offcore": "1",
518
518
         "CounterHTOff": "0,1,2,3"
519
519
     },
520
520
     {
521
-        "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
521
+        "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads miss in the L3",
522
522
         "EventCode": "0xB7, 0xBB",
523
-        "MSRValue": "0x3fffc00200",
523
+        "MSRValue": "0x3FFFC00200",
524
524
         "Counter": "0,1,2,3",
525
525
         "UMask": "0x1",
526
526
         "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.ANY_RESPONSE",
527
-        "MSRIndex": "0x1a6,0x1a7",
527
+        "MSRIndex": "0x1a6, 0x1a7",
528
528
         "SampleAfterValue": "100003",
529
-        "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that miss in the L3",
529
+        "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads miss in the L3",
530
530
         "Offcore": "1",
531
531
         "CounterHTOff": "0,1,2,3"
532
532
     },
533
533
     {
534
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs  that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
534
+        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs miss in the L3",
535
535
         "EventCode": "0xB7, 0xBB",
536
-        "MSRValue": "0x3fffc00100",
536
+        "MSRValue": "0x3FFFC00100",
537
537
         "Counter": "0,1,2,3",
538
538
         "UMask": "0x1",
539
539
         "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.ANY_RESPONSE",
540
-        "MSRIndex": "0x1a6,0x1a7",
540
+        "MSRIndex": "0x1a6, 0x1a7",
541
541
         "SampleAfterValue": "100003",
542
-        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  that miss in the L3",
542
+        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs miss in the L3",
543
543
         "Offcore": "1",
544
544
         "CounterHTOff": "0,1,2,3"
545
545
     },
546
546
     {
547
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
547
+        "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads miss in the L3",
548
548
         "EventCode": "0xB7, 0xBB",
549
-        "MSRValue": "0x3fffc00080",
549
+        "MSRValue": "0x3FFFC00080",
550
550
         "Counter": "0,1,2,3",
551
551
         "UMask": "0x1",
552
552
         "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.ANY_RESPONSE",
553
-        "MSRIndex": "0x1a6,0x1a7",
553
+        "MSRIndex": "0x1a6, 0x1a7",
554
554
         "SampleAfterValue": "100003",
555
-        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss in the L3",
555
+        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads miss in the L3",
556
556
         "Offcore": "1",
557
557
         "CounterHTOff": "0,1,2,3"
558
558
     },
559
559
     {
560
-        "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
560
+        "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads miss in the L3",
561
561
         "EventCode": "0xB7, 0xBB",
562
-        "MSRValue": "0x3fffc00040",
562
+        "MSRValue": "0x3FFFC00040",
563
563
         "Counter": "0,1,2,3",
564
564
         "UMask": "0x1",
565
565
         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS.ANY_RESPONSE",
566
-        "MSRIndex": "0x1a6,0x1a7",
566
+        "MSRIndex": "0x1a6, 0x1a7",
567
567
         "SampleAfterValue": "100003",
568
-        "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss in the L3",
568
+        "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads miss in the L3",
569
569
         "Offcore": "1",
570
570
         "CounterHTOff": "0,1,2,3"
571
571
     },
572
572
     {
573
-        "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
573
+        "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs miss in the L3",
574
574
         "EventCode": "0xB7, 0xBB",
575
-        "MSRValue": "0x3fffc00020",
575
+        "MSRValue": "0x3FFFC00020",
576
576
         "Counter": "0,1,2,3",
577
577
         "UMask": "0x1",
578
578
         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.ANY_RESPONSE",
579
-        "MSRIndex": "0x1a6,0x1a7",
579
+        "MSRIndex": "0x1a6, 0x1a7",
580
580
         "SampleAfterValue": "100003",
581
-        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss in the L3",
581
+        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs miss in the L3",
582
582
         "Offcore": "1",
583
583
         "CounterHTOff": "0,1,2,3"
584
584
     },
585
585
     {
586
-        "PublicDescription": "Counts prefetch (that bring data to L2) data reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
586
+        "PublicDescription": "Counts prefetch (that bring data to L2) data reads miss in the L3",
587
587
         "EventCode": "0xB7, 0xBB",
588
-        "MSRValue": "0x3fffc00010",
588
+        "MSRValue": "0x3FFFC00010",
589
589
         "Counter": "0,1,2,3",
590
590
         "UMask": "0x1",
591
591
         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.ANY_RESPONSE",
592
-        "MSRIndex": "0x1a6,0x1a7",
592
+        "MSRIndex": "0x1a6, 0x1a7",
593
593
         "SampleAfterValue": "100003",
594
-        "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the L3",
594
+        "BriefDescription": "Counts prefetch (that bring data to L2) data reads miss in the L3",
595
595
         "Offcore": "1",
596
596
         "CounterHTOff": "0,1,2,3"
597
597
     },
598
598
     {
599
-        "PublicDescription": "Counts all demand code reads that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
599
+        "PublicDescription": "Counts all demand code reads miss the L3 and the data is returned from local dram",
600
600
         "EventCode": "0xB7, 0xBB",
601
601
         "MSRValue": "0x0100400004",
602
602
         "Counter": "0,1,2,3",
603
603
         "UMask": "0x1",
604
604
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.LOCAL_DRAM",
605
-        "MSRIndex": "0x1a6,0x1a7",
605
+        "MSRIndex": "0x1a6, 0x1a7",
606
606
         "SampleAfterValue": "100003",
607
-        "BriefDescription": "Counts all demand code reads that miss the L3 and the data is returned from local dram",
607
+        "BriefDescription": "Counts all demand code reads miss the L3 and the data is returned from local dram",
608
608
         "Offcore": "1",
609
609
         "CounterHTOff": "0,1,2,3"
610
610
     },
611
611
     {
612
-        "PublicDescription": "Counts all demand code reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
612
+        "PublicDescription": "Counts all demand code reads miss in the L3",
613
613
         "EventCode": "0xB7, 0xBB",
614
-        "MSRValue": "0x3fffc00004",
614
+        "MSRValue": "0x3FFFC00004",
615
615
         "Counter": "0,1,2,3",
616
616
         "UMask": "0x1",
617
617
         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_RESPONSE",
618
-        "MSRIndex": "0x1a6,0x1a7",
618
+        "MSRIndex": "0x1a6, 0x1a7",
619
619
         "SampleAfterValue": "100003",
620
-        "BriefDescription": "Counts all demand code reads that miss in the L3",
620
+        "BriefDescription": "Counts all demand code reads miss in the L3",
621
621
         "Offcore": "1",
622
622
         "CounterHTOff": "0,1,2,3"
623
623
     },
624
624
     {
625
-        "PublicDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
625
+        "PublicDescription": "Counts all demand data writes (RFOs) miss the L3 and the data is returned from local dram",
626
626
         "EventCode": "0xB7, 0xBB",
627
627
         "MSRValue": "0x0100400002",
628
628
         "Counter": "0,1,2,3",
629
629
         "UMask": "0x1",
630
630
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.LOCAL_DRAM",
631
-        "MSRIndex": "0x1a6,0x1a7",
631
+        "MSRIndex": "0x1a6, 0x1a7",
632
632
         "SampleAfterValue": "100003",
633
-        "BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the data is returned from local dram",
633
+        "BriefDescription": "Counts all demand data writes (RFOs) miss the L3 and the data is returned from local dram",
634
634
         "Offcore": "1",
635
635
         "CounterHTOff": "0,1,2,3"
636
636
     },
637
637
     {
638
-        "PublicDescription": "Counts all demand data writes (RFOs) that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
638
+        "PublicDescription": "Counts all demand data writes (RFOs) miss in the L3",
639
639
         "EventCode": "0xB7, 0xBB",
640
-        "MSRValue": "0x3fffc00002",
640
+        "MSRValue": "0x3FFFC00002",
641
641
         "Counter": "0,1,2,3",
642
642
         "UMask": "0x1",
643
643
         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_RESPONSE",
644
-        "MSRIndex": "0x1a6,0x1a7",
644
+        "MSRIndex": "0x1a6, 0x1a7",
645
645
         "SampleAfterValue": "100003",
646
-        "BriefDescription": "Counts all demand data writes (RFOs) that miss in the L3",
646
+        "BriefDescription": "Counts all demand data writes (RFOs) miss in the L3",
647
647
         "Offcore": "1",
648
648
         "CounterHTOff": "0,1,2,3"
649
649
     },
650
650
     {
651
-        "PublicDescription": "Counts demand data reads that miss the L3 and the data is returned from local dram Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
651
+        "PublicDescription": "Counts demand data reads miss the L3 and the data is returned from local dram",
652
652
         "EventCode": "0xB7, 0xBB",
653
653
         "MSRValue": "0x0100400001",
654
654
         "Counter": "0,1,2,3",
655
655
         "UMask": "0x1",
656
656
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.LOCAL_DRAM",
657
-        "MSRIndex": "0x1a6,0x1a7",
657
+        "MSRIndex": "0x1a6, 0x1a7",
658
658
         "SampleAfterValue": "100003",
659
-        "BriefDescription": "Counts demand data reads that miss the L3 and the data is returned from local dram",
659
+        "BriefDescription": "Counts demand data reads miss the L3 and the data is returned from local dram",
660
660
         "Offcore": "1",
661
661
         "CounterHTOff": "0,1,2,3"
662
662
     },
663
663
     {
664
-        "PublicDescription": "Counts demand data reads that miss in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
664
+        "PublicDescription": "Counts demand data reads miss in the L3",
665
665
         "EventCode": "0xB7, 0xBB",
666
-        "MSRValue": "0x3fffc00001",
666
+        "MSRValue": "0x3FFFC00001",
667
667
         "Counter": "0,1,2,3",
668
668
         "UMask": "0x1",
669
669
         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_RESPONSE",
670
-        "MSRIndex": "0x1a6,0x1a7",
670
+        "MSRIndex": "0x1a6, 0x1a7",
671
671
         "SampleAfterValue": "100003",
672
-        "BriefDescription": "Counts demand data reads that miss in the L3",
672
+        "BriefDescription": "Counts demand data reads miss in the L3",
673
673
         "Offcore": "1",
674
674
         "CounterHTOff": "0,1,2,3"
675
675
     }