forked from ~ljy/RK356X_SDK_RELEASE
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hc
2024-05-10 23fa18eaa71266feff7ba8d83022d9e1cc83c65a 
 kernel/tools/perf/pmu-events/arch/x86/goldmontplus/cache.json
....@@ -92,7 +92,8 @@
9292         "PEBScounters": "0,1,2,3",
9393         "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
9494         "SampleAfterValue": "200003",
95
-        "BriefDescription": "Locked load uops retired (Precise event capable)"
95
+        "BriefDescription": "Locked load uops retired (Precise event capable)",
96
+        "Data_LA": "1"
9697     },
9798     {
9899         "PEBS": "2",
....@@ -104,7 +105,8 @@
104105         "PEBScounters": "0,1,2,3",
105106         "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
106107         "SampleAfterValue": "200003",
107
-        "BriefDescription": "Load uops retired that split a cache-line (Precise event capable)"
108
+        "BriefDescription": "Load uops retired that split a cache-line (Precise event capable)",
109
+        "Data_LA": "1"
108110     },
109111     {
110112         "PEBS": "2",
....@@ -116,7 +118,8 @@
116118         "PEBScounters": "0,1,2,3",
117119         "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
118120         "SampleAfterValue": "200003",
119
-        "BriefDescription": "Stores uops retired that split a cache-line (Precise event capable)"
121
+        "BriefDescription": "Stores uops retired that split a cache-line (Precise event capable)",
122
+        "Data_LA": "1"
120123     },
121124     {
122125         "PEBS": "2",
....@@ -128,7 +131,8 @@
128131         "PEBScounters": "0,1,2,3",
129132         "EventName": "MEM_UOPS_RETIRED.SPLIT",
130133         "SampleAfterValue": "200003",
131
-        "BriefDescription": "Memory uops retired that split a cache-line (Precise event capable)"
134
+        "BriefDescription": "Memory uops retired that split a cache-line (Precise event capable)",
135
+        "Data_LA": "1"
132136     },
133137     {
134138         "PEBS": "2",
....@@ -140,7 +144,8 @@
140144         "PEBScounters": "0,1,2,3",
141145         "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
142146         "SampleAfterValue": "200003",
143
-        "BriefDescription": "Load uops retired (Precise event capable)"
147
+        "BriefDescription": "Load uops retired (Precise event capable)",
148
+        "Data_LA": "1"
144149     },
145150     {
146151         "PEBS": "2",
....@@ -152,7 +157,8 @@
152157         "PEBScounters": "0,1,2,3",
153158         "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
154159         "SampleAfterValue": "200003",
155
-        "BriefDescription": "Store uops retired (Precise event capable)"
160
+        "BriefDescription": "Store uops retired (Precise event capable)",
161
+        "Data_LA": "1"
156162     },
157163     {
158164         "PEBS": "2",
....@@ -164,7 +170,8 @@
164170         "PEBScounters": "0,1,2,3",
165171         "EventName": "MEM_UOPS_RETIRED.ALL",
166172         "SampleAfterValue": "200003",
167
-        "BriefDescription": "Memory uops retired (Precise event capable)"
173
+        "BriefDescription": "Memory uops retired (Precise event capable)",
174
+        "Data_LA": "1"
168175     },
169176     {
170177         "PEBS": "2",
....@@ -176,7 +183,8 @@
176183         "PEBScounters": "0,1,2,3",
177184         "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
178185         "SampleAfterValue": "200003",
179
-        "BriefDescription": "Load uops retired that hit L1 data cache (Precise event capable)"
186
+        "BriefDescription": "Load uops retired that hit L1 data cache (Precise event capable)",
187
+        "Data_LA": "1"
180188     },
181189     {
182190         "PEBS": "2",
....@@ -188,7 +196,8 @@
188196         "PEBScounters": "0,1,2,3",
189197         "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
190198         "SampleAfterValue": "200003",
191
-        "BriefDescription": "Load uops retired that hit L2 (Precise event capable)"
199
+        "BriefDescription": "Load uops retired that hit L2 (Precise event capable)",
200
+        "Data_LA": "1"
192201     },
193202     {
194203         "PEBS": "2",
....@@ -200,7 +209,8 @@
200209         "PEBScounters": "0,1,2,3",
201210         "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
202211         "SampleAfterValue": "200003",
203
-        "BriefDescription": "Load uops retired that missed L1 data cache (Precise event capable)"
212
+        "BriefDescription": "Load uops retired that missed L1 data cache (Precise event capable)",
213
+        "Data_LA": "1"
204214     },
205215     {
206216         "PEBS": "2",
....@@ -212,7 +222,8 @@
212222         "PEBScounters": "0,1,2,3",
213223         "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
214224         "SampleAfterValue": "200003",
215
-        "BriefDescription": "Load uops retired that missed L2 (Precise event capable)"
225
+        "BriefDescription": "Load uops retired that missed L2 (Precise event capable)",
226
+        "Data_LA": "1"
216227     },
217228     {
218229         "PEBS": "2",
....@@ -224,7 +235,8 @@
224235         "PEBScounters": "0,1,2,3",
225236         "EventName": "MEM_LOAD_UOPS_RETIRED.HITM",
226237         "SampleAfterValue": "200003",
227
-        "BriefDescription": "Memory uop retired where cross core or cross module HITM occurred (Precise event capable)"
238
+        "BriefDescription": "Memory uop retired where cross core or cross module HITM occurred (Precise event capable)",
239
+        "Data_LA": "1"
228240     },
229241     {
230242         "PEBS": "2",
....@@ -236,7 +248,8 @@
236248         "PEBScounters": "0,1,2,3",
237249         "EventName": "MEM_LOAD_UOPS_RETIRED.WCB_HIT",
238250         "SampleAfterValue": "200003",
239
-        "BriefDescription": "Loads retired that hit WCB (Precise event capable)"
251
+        "BriefDescription": "Loads retired that hit WCB (Precise event capable)",
252
+        "Data_LA": "1"
240253     },
241254     {
242255         "PEBS": "2",
....@@ -248,7 +261,8 @@
248261         "PEBScounters": "0,1,2,3",
249262         "EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT",
250263         "SampleAfterValue": "200003",
251
-        "BriefDescription": "Loads retired that came from DRAM (Precise event capable)"
264
+        "BriefDescription": "Loads retired that came from DRAM (Precise event capable)",
265
+        "Data_LA": "1"
252266     },
253267     {
254268         "CollectPEBSRecord": "1",
....@@ -292,7 +306,7 @@
292306         "PDIR_COUNTER": "na",
293307         "MSRIndex": "0x1a6, 0x1a7",
294308         "SampleAfterValue": "100007",
295
-        "BriefDescription": "Counts demand cacheable data reads of full cache lines true miss for the L2 cache with a snoop miss in the other processor module. ",
309
+        "BriefDescription": "Counts demand cacheable data reads of full cache lines true miss for the L2 cache with a snoop miss in the other processor module.",
296310         "Offcore": "1"
297311     },
298312     {
....@@ -367,7 +381,7 @@
367381         "PDIR_COUNTER": "na",
368382         "MSRIndex": "0x1a6, 0x1a7",
369383         "SampleAfterValue": "100007",
370
-        "BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line true miss for the L2 cache with a snoop miss in the other processor module. ",
384
+        "BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line true miss for the L2 cache with a snoop miss in the other processor module.",
371385         "Offcore": "1"
372386     },
373387     {
....@@ -442,7 +456,7 @@
442456         "PDIR_COUNTER": "na",
443457         "MSRIndex": "0x1a6, 0x1a7",
444458         "SampleAfterValue": "100007",
445
-        "BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache true miss for the L2 cache with a snoop miss in the other processor module. ",
459
+        "BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache true miss for the L2 cache with a snoop miss in the other processor module.",
446460         "Offcore": "1"
447461     },
448462     {
....@@ -517,7 +531,7 @@
517531         "PDIR_COUNTER": "na",
518532         "MSRIndex": "0x1a6, 0x1a7",
519533         "SampleAfterValue": "100007",
520
-        "BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions true miss for the L2 cache with a snoop miss in the other processor module. ",
534
+        "BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions true miss for the L2 cache with a snoop miss in the other processor module.",
521535         "Offcore": "1"
522536     },
523537     {
....@@ -592,7 +606,7 @@
592606         "PDIR_COUNTER": "na",
593607         "MSRIndex": "0x1a6, 0x1a7",
594608         "SampleAfterValue": "100007",
595
-        "BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module. ",
609
+        "BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module.",
596610         "Offcore": "1"
597611     },
598612     {
....@@ -667,7 +681,7 @@
667681         "PDIR_COUNTER": "na",
668682         "MSRIndex": "0x1a6, 0x1a7",
669683         "SampleAfterValue": "100007",
670
-        "BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher true miss for the L2 cache with a snoop miss in the other processor module. ",
684
+        "BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher true miss for the L2 cache with a snoop miss in the other processor module.",
671685         "Offcore": "1"
672686     },
673687     {
....@@ -742,7 +756,7 @@
742756         "PDIR_COUNTER": "na",
743757         "MSRIndex": "0x1a6, 0x1a7",
744758         "SampleAfterValue": "100007",
745
-        "BriefDescription": "Counts bus lock and split lock requests true miss for the L2 cache with a snoop miss in the other processor module. ",
759
+        "BriefDescription": "Counts bus lock and split lock requests true miss for the L2 cache with a snoop miss in the other processor module.",
746760         "Offcore": "1"
747761     },
748762     {
....@@ -817,7 +831,7 @@
817831         "PDIR_COUNTER": "na",
818832         "MSRIndex": "0x1a6, 0x1a7",
819833         "SampleAfterValue": "100007",
820
-        "BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes true miss for the L2 cache with a snoop miss in the other processor module. ",
834
+        "BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes true miss for the L2 cache with a snoop miss in the other processor module.",
821835         "Offcore": "1"
822836     },
823837     {
....@@ -892,7 +906,7 @@
892906         "PDIR_COUNTER": "na",
893907         "MSRIndex": "0x1a6, 0x1a7",
894908         "SampleAfterValue": "100007",
895
-        "BriefDescription": "Counts data cache lines requests by software prefetch instructions true miss for the L2 cache with a snoop miss in the other processor module. ",
909
+        "BriefDescription": "Counts data cache lines requests by software prefetch instructions true miss for the L2 cache with a snoop miss in the other processor module.",
896910         "Offcore": "1"
897911     },
898912     {
....@@ -967,7 +981,7 @@
967981         "PDIR_COUNTER": "na",
968982         "MSRIndex": "0x1a6, 0x1a7",
969983         "SampleAfterValue": "100007",
970
-        "BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module. ",
984
+        "BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module.",
971985         "Offcore": "1"
972986     },
973987     {
....@@ -1042,7 +1056,7 @@
10421056         "PDIR_COUNTER": "na",
10431057         "MSRIndex": "0x1a6, 0x1a7",
10441058         "SampleAfterValue": "100007",
1045
-        "BriefDescription": "Counts any data writes to uncacheable write combining (USWC) memory region  true miss for the L2 cache with a snoop miss in the other processor module. ",
1059
+        "BriefDescription": "Counts any data writes to uncacheable write combining (USWC) memory region  true miss for the L2 cache with a snoop miss in the other processor module.",
10461060         "Offcore": "1"
10471061     },
10481062     {
....@@ -1117,7 +1131,7 @@
11171131         "PDIR_COUNTER": "na",
11181132         "MSRIndex": "0x1a6, 0x1a7",
11191133         "SampleAfterValue": "100007",
1120
-        "BriefDescription": "Counts requests to the uncore subsystem true miss for the L2 cache with a snoop miss in the other processor module. ",
1134
+        "BriefDescription": "Counts requests to the uncore subsystem true miss for the L2 cache with a snoop miss in the other processor module.",
11211135         "Offcore": "1"
11221136     },
11231137     {
....@@ -1192,7 +1206,7 @@
11921206         "PDIR_COUNTER": "na",
11931207         "MSRIndex": "0x1a6, 0x1a7",
11941208         "SampleAfterValue": "100007",
1195
-        "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers true miss for the L2 cache with a snoop miss in the other processor module. ",
1209
+        "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers true miss for the L2 cache with a snoop miss in the other processor module.",
11961210         "Offcore": "1"
11971211     },
11981212     {
....@@ -1267,7 +1281,7 @@
12671281         "PDIR_COUNTER": "na",
12681282         "MSRIndex": "0x1a6, 0x1a7",
12691283         "SampleAfterValue": "100007",
1270
-        "BriefDescription": "Counts data reads (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module. ",
1284
+        "BriefDescription": "Counts data reads (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module.",
12711285         "Offcore": "1"
12721286     },
12731287     {
....@@ -1342,7 +1356,7 @@
13421356         "PDIR_COUNTER": "na",
13431357         "MSRIndex": "0x1a6, 0x1a7",
13441358         "SampleAfterValue": "100007",
1345
-        "BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module. ",
1359
+        "BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module.",
13461360         "Offcore": "1"
13471361     },
13481362     {
....@@ -1417,7 +1431,7 @@
14171431         "PDIR_COUNTER": "na",
14181432         "MSRIndex": "0x1a6, 0x1a7",
14191433         "SampleAfterValue": "100007",
1420
-        "BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module. ",
1434
+        "BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module.",
14211435         "Offcore": "1"
14221436     },
14231437     {