| .. | .. |
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| 1 | 1 | [ |
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| 2 | 2 | { |
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| 3 | | - "EventCode": "0x00", |
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| 4 | 3 | "UMask": "0x1", |
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| 5 | 4 | "BriefDescription": "Instructions retired from execution.", |
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| 6 | 5 | "Counter": "Fixed counter 0", |
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| .. | .. |
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| 10 | 9 | "CounterHTOff": "Fixed counter 0" |
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| 11 | 10 | }, |
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| 12 | 11 | { |
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| 13 | | - "EventCode": "0x00", |
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| 14 | 12 | "UMask": "0x2", |
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| 15 | 13 | "BriefDescription": "Core cycles when the thread is not in halt state", |
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| 16 | 14 | "Counter": "Fixed counter 1", |
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| .. | .. |
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| 20 | 18 | "CounterHTOff": "Fixed counter 1" |
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| 21 | 19 | }, |
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| 22 | 20 | { |
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| 23 | | - "EventCode": "0x00", |
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| 24 | 21 | "UMask": "0x2", |
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| 25 | 22 | "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", |
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| 26 | 23 | "Counter": "Fixed counter 1", |
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| .. | .. |
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| 30 | 27 | "CounterHTOff": "Fixed counter 1" |
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| 31 | 28 | }, |
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| 32 | 29 | { |
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| 33 | | - "EventCode": "0x00", |
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| 34 | 30 | "UMask": "0x3", |
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| 35 | 31 | "BriefDescription": "Reference cycles when the core is not in halt state.", |
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| 36 | 32 | "Counter": "Fixed counter 2", |
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