forked from ~ljy/RK356X_SDK_RELEASE
blame | history | patch | commit | commitdiff
hc
2024-05-10 23fa18eaa71266feff7ba8d83022d9e1cc83c65a 
 kernel/tools/perf/pmu-events/arch/powerpc/power8/pipeline.json
....@@ -1,350 +1,350 @@
11 [
2
-  {,
2
+  {
33     "EventCode": "0x100f2",
44     "EventName": "PM_1PLUS_PPC_CMPL",
55     "BriefDescription": "1 or more ppc insts finished",
66     "PublicDescription": "1 or more ppc insts finished (completed)"
77   },
8
-  {,
8
+  {
99     "EventCode": "0x400f2",
1010     "EventName": "PM_1PLUS_PPC_DISP",
1111     "BriefDescription": "Cycles at least one Instr Dispatched",
1212     "PublicDescription": "Cycles at least one Instr Dispatched. Could be a group with only microcode. Issue HW016521"
1313   },
14
-  {,
14
+  {
1515     "EventCode": "0x100fa",
1616     "EventName": "PM_ANY_THRD_RUN_CYC",
1717     "BriefDescription": "One of threads in run_cycles",
1818     "PublicDescription": "Any thread in run_cycles (was one thread in run_cycles)"
1919   },
20
-  {,
20
+  {
2121     "EventCode": "0x4000a",
2222     "EventName": "PM_CMPLU_STALL",
2323     "BriefDescription": "Completion stall",
2424     "PublicDescription": ""
2525   },
26
-  {,
26
+  {
2727     "EventCode": "0x4d018",
2828     "EventName": "PM_CMPLU_STALL_BRU",
2929     "BriefDescription": "Completion stall due to a Branch Unit",
3030     "PublicDescription": ""
3131   },
32
-  {,
32
+  {
3333     "EventCode": "0x2c012",
3434     "EventName": "PM_CMPLU_STALL_DCACHE_MISS",
3535     "BriefDescription": "Completion stall by Dcache miss",
3636     "PublicDescription": ""
3737   },
38
-  {,
38
+  {
3939     "EventCode": "0x2c018",
4040     "EventName": "PM_CMPLU_STALL_DMISS_L21_L31",
4141     "BriefDescription": "Completion stall by Dcache miss which resolved on chip ( excluding local L2/L3)",
4242     "PublicDescription": ""
4343   },
44
-  {,
44
+  {
4545     "EventCode": "0x2c016",
4646     "EventName": "PM_CMPLU_STALL_DMISS_L2L3",
4747     "BriefDescription": "Completion stall by Dcache miss which resolved in L2/L3",
4848     "PublicDescription": ""
4949   },
50
-  {,
50
+  {
5151     "EventCode": "0x4c016",
5252     "EventName": "PM_CMPLU_STALL_DMISS_L2L3_CONFLICT",
5353     "BriefDescription": "Completion stall due to cache miss that resolves in the L2 or L3 with a conflict",
5454     "PublicDescription": "Completion stall due to cache miss resolving in core's L2/L3 with a conflict"
5555   },
56
-  {,
56
+  {
5757     "EventCode": "0x4c01a",
5858     "EventName": "PM_CMPLU_STALL_DMISS_L3MISS",
5959     "BriefDescription": "Completion stall due to cache miss resolving missed the L3",
6060     "PublicDescription": ""
6161   },
62
-  {,
62
+  {
6363     "EventCode": "0x4c018",
6464     "EventName": "PM_CMPLU_STALL_DMISS_LMEM",
6565     "BriefDescription": "Completion stall due to cache miss that resolves in local memory",
6666     "PublicDescription": "Completion stall due to cache miss resolving in core's Local Memory"
6767   },
68
-  {,
68
+  {
6969     "EventCode": "0x2c01c",
7070     "EventName": "PM_CMPLU_STALL_DMISS_REMOTE",
7171     "BriefDescription": "Completion stall by Dcache miss which resolved from remote chip (cache or memory)",
7272     "PublicDescription": "Completion stall by Dcache miss which resolved on chip ( excluding local L2/L3)"
7373   },
74
-  {,
74
+  {
7575     "EventCode": "0x4c012",
7676     "EventName": "PM_CMPLU_STALL_ERAT_MISS",
7777     "BriefDescription": "Completion stall due to LSU reject ERAT miss",
7878     "PublicDescription": ""
7979   },
80
-  {,
80
+  {
8181     "EventCode": "0x4d016",
8282     "EventName": "PM_CMPLU_STALL_FXLONG",
8383     "BriefDescription": "Completion stall due to a long latency fixed point instruction",
8484     "PublicDescription": ""
8585   },
86
-  {,
86
+  {
8787     "EventCode": "0x2d016",
8888     "EventName": "PM_CMPLU_STALL_FXU",
8989     "BriefDescription": "Completion stall due to FXU",
9090     "PublicDescription": ""
9191   },
92
-  {,
92
+  {
9393     "EventCode": "0x30036",
9494     "EventName": "PM_CMPLU_STALL_HWSYNC",
9595     "BriefDescription": "completion stall due to hwsync",
9696     "PublicDescription": ""
9797   },
98
-  {,
98
+  {
9999     "EventCode": "0x4d014",
100100     "EventName": "PM_CMPLU_STALL_LOAD_FINISH",
101101     "BriefDescription": "Completion stall due to a Load finish",
102102     "PublicDescription": ""
103103   },
104
-  {,
104
+  {
105105     "EventCode": "0x2c010",
106106     "EventName": "PM_CMPLU_STALL_LSU",
107107     "BriefDescription": "Completion stall by LSU instruction",
108108     "PublicDescription": ""
109109   },
110
-  {,
110
+  {
111111     "EventCode": "0x10036",
112112     "EventName": "PM_CMPLU_STALL_LWSYNC",
113113     "BriefDescription": "completion stall due to isync/lwsync",
114114     "PublicDescription": ""
115115   },
116
-  {,
116
+  {
117117     "EventCode": "0x30006",
118118     "EventName": "PM_CMPLU_STALL_OTHER_CMPL",
119119     "BriefDescription": "Instructions core completed while this tread was stalled",
120120     "PublicDescription": "Instructions core completed while this thread was stalled"
121121   },
122
-  {,
122
+  {
123123     "EventCode": "0x4c01c",
124124     "EventName": "PM_CMPLU_STALL_ST_FWD",
125125     "BriefDescription": "Completion stall due to store forward",
126126     "PublicDescription": ""
127127   },
128
-  {,
128
+  {
129129     "EventCode": "0x1001c",
130130     "EventName": "PM_CMPLU_STALL_THRD",
131131     "BriefDescription": "Completion Stalled due to thread conflict. Group ready to complete but it was another thread's turn",
132132     "PublicDescription": "Completion stall due to thread conflict"
133133   },
134
-  {,
134
+  {
135135     "EventCode": "0x1e",
136136     "EventName": "PM_CYC",
137137     "BriefDescription": "Cycles",
138138     "PublicDescription": ""
139139   },
140
-  {,
140
+  {
141141     "EventCode": "0x10006",
142142     "EventName": "PM_DISP_HELD",
143143     "BriefDescription": "Dispatch Held",
144144     "PublicDescription": ""
145145   },
146
-  {,
146
+  {
147147     "EventCode": "0x4003c",
148148     "EventName": "PM_DISP_HELD_SYNC_HOLD",
149149     "BriefDescription": "Dispatch held due to SYNC hold",
150150     "PublicDescription": ""
151151   },
152
-  {,
152
+  {
153153     "EventCode": "0x200f8",
154154     "EventName": "PM_EXT_INT",
155155     "BriefDescription": "external interrupt",
156156     "PublicDescription": ""
157157   },
158
-  {,
158
+  {
159159     "EventCode": "0x400f8",
160160     "EventName": "PM_FLUSH",
161161     "BriefDescription": "Flush (any type)",
162162     "PublicDescription": ""
163163   },
164
-  {,
164
+  {
165165     "EventCode": "0x30012",
166166     "EventName": "PM_FLUSH_COMPLETION",
167167     "BriefDescription": "Completion Flush",
168168     "PublicDescription": ""
169169   },
170
-  {,
170
+  {
171171     "EventCode": "0x3000c",
172172     "EventName": "PM_FREQ_DOWN",
173173     "BriefDescription": "Power Management: Below Threshold B",
174174     "PublicDescription": "Frequency is being slewed down due to Power Management"
175175   },
176
-  {,
176
+  {
177177     "EventCode": "0x4000c",
178178     "EventName": "PM_FREQ_UP",
179179     "BriefDescription": "Power Management: Above Threshold A",
180180     "PublicDescription": "Frequency is being slewed up due to Power Management"
181181   },
182
-  {,
182
+  {
183183     "EventCode": "0x2000a",
184184     "EventName": "PM_HV_CYC",
185185     "BriefDescription": "Cycles in which msr_hv is high. Note that this event does not take msr_pr into consideration",
186186     "PublicDescription": "cycles in hypervisor mode"
187187   },
188
-  {,
188
+  {
189189     "EventCode": "0x3405e",
190190     "EventName": "PM_IFETCH_THROTTLE",
191191     "BriefDescription": "Cycles in which Instruction fetch throttle was active",
192192     "PublicDescription": "Cycles instruction fecth was throttled in IFU"
193193   },
194
-  {,
194
+  {
195195     "EventCode": "0x10014",
196196     "EventName": "PM_IOPS_CMPL",
197197     "BriefDescription": "Internal Operations completed",
198198     "PublicDescription": "IOPS Completed"
199199   },
200
-  {,
200
+  {
201201     "EventCode": "0x3c058",
202202     "EventName": "PM_LARX_FIN",
203203     "BriefDescription": "Larx finished",
204204     "PublicDescription": ""
205205   },
206
-  {,
206
+  {
207207     "EventCode": "0x1002e",
208208     "EventName": "PM_LD_CMPL",
209209     "BriefDescription": "count of Loads completed",
210210     "PublicDescription": ""
211211   },
212
-  {,
212
+  {
213213     "EventCode": "0x10062",
214214     "EventName": "PM_LD_L3MISS_PEND_CYC",
215215     "BriefDescription": "Cycles L3 miss was pending for this thread",
216216     "PublicDescription": ""
217217   },
218
-  {,
218
+  {
219219     "EventCode": "0x30066",
220220     "EventName": "PM_LSU_FIN",
221221     "BriefDescription": "LSU Finished an instruction (up to 2 per cycle)",
222222     "PublicDescription": ""
223223   },
224
-  {,
224
+  {
225225     "EventCode": "0x2003e",
226226     "EventName": "PM_LSU_LMQ_SRQ_EMPTY_CYC",
227227     "BriefDescription": "LSU empty (lmq and srq empty)",
228228     "PublicDescription": ""
229229   },
230
-  {,
230
+  {
231231     "EventCode": "0x2e05c",
232232     "EventName": "PM_LSU_REJECT_ERAT_MISS",
233233     "BriefDescription": "LSU Reject due to ERAT (up to 4 per cycles)",
234234     "PublicDescription": ""
235235   },
236
-  {,
236
+  {
237237     "EventCode": "0x4e05c",
238238     "EventName": "PM_LSU_REJECT_LHS",
239239     "BriefDescription": "LSU Reject due to LHS (up to 4 per cycle)",
240240     "PublicDescription": ""
241241   },
242
-  {,
242
+  {
243243     "EventCode": "0x1e05c",
244244     "EventName": "PM_LSU_REJECT_LMQ_FULL",
245245     "BriefDescription": "LSU reject due to LMQ full ( 4 per cycle)",
246246     "PublicDescription": ""
247247   },
248
-  {,
248
+  {
249249     "EventCode": "0x1001a",
250250     "EventName": "PM_LSU_SRQ_FULL_CYC",
251251     "BriefDescription": "Storage Queue is full and is blocking dispatch",
252252     "PublicDescription": "SRQ is Full"
253253   },
254
-  {,
254
+  {
255255     "EventCode": "0x40014",
256256     "EventName": "PM_PROBE_NOP_DISP",
257257     "BriefDescription": "ProbeNops dispatched",
258258     "PublicDescription": ""
259259   },
260
-  {,
260
+  {
261261     "EventCode": "0x600f4",
262262     "EventName": "PM_RUN_CYC",
263263     "BriefDescription": "Run_cycles",
264264     "PublicDescription": ""
265265   },
266
-  {,
266
+  {
267267     "EventCode": "0x3006c",
268268     "EventName": "PM_RUN_CYC_SMT2_MODE",
269269     "BriefDescription": "Cycles run latch is set and core is in SMT2 mode",
270270     "PublicDescription": ""
271271   },
272
-  {,
272
+  {
273273     "EventCode": "0x2006c",
274274     "EventName": "PM_RUN_CYC_SMT4_MODE",
275275     "BriefDescription": "cycles this threads run latch is set and the core is in SMT4 mode",
276276     "PublicDescription": "Cycles run latch is set and core is in SMT4 mode"
277277   },
278
-  {,
278
+  {
279279     "EventCode": "0x1006c",
280280     "EventName": "PM_RUN_CYC_ST_MODE",
281281     "BriefDescription": "Cycles run latch is set and core is in ST mode",
282282     "PublicDescription": ""
283283   },
284
-  {,
284
+  {
285285     "EventCode": "0x500fa",
286286     "EventName": "PM_RUN_INST_CMPL",
287287     "BriefDescription": "Run_Instructions",
288288     "PublicDescription": ""
289289   },
290
-  {,
290
+  {
291291     "EventCode": "0x1e058",
292292     "EventName": "PM_STCX_FAIL",
293293     "BriefDescription": "stcx failed",
294294     "PublicDescription": ""
295295   },
296
-  {,
296
+  {
297297     "EventCode": "0x20016",
298298     "EventName": "PM_ST_CMPL",
299299     "BriefDescription": "Store completion count",
300300     "PublicDescription": ""
301301   },
302
-  {,
302
+  {
303303     "EventCode": "0x200f0",
304304     "EventName": "PM_ST_FIN",
305305     "BriefDescription": "Store Instructions Finished",
306306     "PublicDescription": "Store Instructions Finished (store sent to nest)"
307307   },
308
-  {,
308
+  {
309309     "EventCode": "0x20018",
310310     "EventName": "PM_ST_FWD",
311311     "BriefDescription": "Store forwards that finished",
312312     "PublicDescription": ""
313313   },
314
-  {,
314
+  {
315315     "EventCode": "0x10026",
316316     "EventName": "PM_TABLEWALK_CYC",
317317     "BriefDescription": "Cycles when a tablewalk (I or D) is active",
318318     "PublicDescription": "Tablewalk Active"
319319   },
320
-  {,
320
+  {
321321     "EventCode": "0x300f8",
322322     "EventName": "PM_TB_BIT_TRANS",
323323     "BriefDescription": "timebase event",
324324     "PublicDescription": ""
325325   },
326
-  {,
326
+  {
327327     "EventCode": "0x2000c",
328328     "EventName": "PM_THRD_ALL_RUN_CYC",
329329     "BriefDescription": "All Threads in Run_cycles (was both threads in run_cycles)",
330330     "PublicDescription": ""
331331   },
332
-  {,
332
+  {
333333     "EventCode": "0x30058",
334334     "EventName": "PM_TLBIE_FIN",
335335     "BriefDescription": "tlbie finished",
336336     "PublicDescription": ""
337337   },
338
-  {,
338
+  {
339339     "EventCode": "0x10060",
340340     "EventName": "PM_TM_TRANS_RUN_CYC",
341341     "BriefDescription": "run cycles in transactional state",
342342     "PublicDescription": ""
343343   },
344
-  {,
344
+  {
345345     "EventCode": "0x2e012",
346346     "EventName": "PM_TM_TX_PASS_RUN_CYC",
347347     "BriefDescription": "cycles spent in successful transactions",
348348     "PublicDescription": "run cycles spent in successful transactions"
349
-  },
349
+  }
350350 ]