disable pwm7

hc

2024-05-10 23fa18eaa71266feff7ba8d83022d9e1cc83c65a

 kernel/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
..
..
@@ -1,113 +1,113 @@
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 [
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     {
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-        "ArchStdEvent": "L1D_CACHE_RD",
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+        "ArchStdEvent": "L1D_CACHE_RD"
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     },
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     {
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-        "ArchStdEvent": "L1D_CACHE_WR",
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+        "ArchStdEvent": "L1D_CACHE_WR"
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     },
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     {
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-        "ArchStdEvent": "L1D_CACHE_REFILL_RD",
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+        "ArchStdEvent": "L1D_CACHE_REFILL_RD"
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     },
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     {
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-        "ArchStdEvent": "L1D_CACHE_REFILL_WR",
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+        "ArchStdEvent": "L1D_CACHE_REFILL_WR"
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     },
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     {
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-        "ArchStdEvent": "L1D_CACHE_REFILL_INNER",
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+        "ArchStdEvent": "L1D_CACHE_REFILL_INNER"
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     },
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     {
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-        "ArchStdEvent": "L1D_CACHE_REFILL_OUTER",
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+        "ArchStdEvent": "L1D_CACHE_REFILL_OUTER"
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     },
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     {
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-        "ArchStdEvent": "L1D_CACHE_WB_VICTIM",
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+        "ArchStdEvent": "L1D_CACHE_WB_VICTIM"
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     },
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     {
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-        "ArchStdEvent": "L1D_CACHE_WB_CLEAN",
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+        "ArchStdEvent": "L1D_CACHE_WB_CLEAN"
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     },
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     {
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-        "ArchStdEvent": "L1D_CACHE_INVAL",
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+        "ArchStdEvent": "L1D_CACHE_INVAL"
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     },
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     {
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-        "ArchStdEvent": "L1D_TLB_REFILL_RD",
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+        "ArchStdEvent": "L1D_TLB_REFILL_RD"
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     },
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     {
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-        "ArchStdEvent": "L1D_TLB_REFILL_WR",
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+        "ArchStdEvent": "L1D_TLB_REFILL_WR"
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     },
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     {
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-        "ArchStdEvent": "L1D_TLB_RD",
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+        "ArchStdEvent": "L1D_TLB_RD"
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     },
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     {
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-        "ArchStdEvent": "L1D_TLB_WR",
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+        "ArchStdEvent": "L1D_TLB_WR"
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     },
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     {
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-        "ArchStdEvent": "L2D_TLB_REFILL_RD",
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+        "ArchStdEvent": "L2D_TLB_REFILL_RD"
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     },
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     {
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-        "ArchStdEvent": "L2D_TLB_REFILL_WR",
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+        "ArchStdEvent": "L2D_TLB_REFILL_WR"
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     },
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     {
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-        "ArchStdEvent": "L2D_TLB_RD",
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+        "ArchStdEvent": "L2D_TLB_RD"
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     },
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     {
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-        "ArchStdEvent": "L2D_TLB_WR",
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+        "ArchStdEvent": "L2D_TLB_WR"
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     },
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     {
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-        "ArchStdEvent": "BUS_ACCESS_RD",
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+        "ArchStdEvent": "BUS_ACCESS_RD"
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     },
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     {
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-        "ArchStdEvent": "BUS_ACCESS_WR",
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+        "ArchStdEvent": "BUS_ACCESS_WR"
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     },
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     {
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-        "ArchStdEvent": "MEM_ACCESS_RD",
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+        "ArchStdEvent": "MEM_ACCESS_RD"
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     },
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     {
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-        "ArchStdEvent": "MEM_ACCESS_WR",
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+        "ArchStdEvent": "MEM_ACCESS_WR"
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     },
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     {
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-        "ArchStdEvent": "UNALIGNED_LD_SPEC",
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+        "ArchStdEvent": "UNALIGNED_LD_SPEC"
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     },
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     {
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-        "ArchStdEvent": "UNALIGNED_ST_SPEC",
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+        "ArchStdEvent": "UNALIGNED_ST_SPEC"
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     },
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     {
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-        "ArchStdEvent": "UNALIGNED_LDST_SPEC",
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+        "ArchStdEvent": "UNALIGNED_LDST_SPEC"
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     },
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     {
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-        "ArchStdEvent": "EXC_UNDEF",
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+        "ArchStdEvent": "EXC_UNDEF"
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     },
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     {
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-        "ArchStdEvent": "EXC_SVC",
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+        "ArchStdEvent": "EXC_SVC"
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     },
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     {
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-        "ArchStdEvent": "EXC_PABORT",
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+        "ArchStdEvent": "EXC_PABORT"
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     },
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     {
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-        "ArchStdEvent": "EXC_DABORT",
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+        "ArchStdEvent": "EXC_DABORT"
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     },
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     {
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-        "ArchStdEvent": "EXC_IRQ",
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+        "ArchStdEvent": "EXC_IRQ"
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     },
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     {
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-        "ArchStdEvent": "EXC_FIQ",
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+        "ArchStdEvent": "EXC_FIQ"
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     },
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     {
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-        "ArchStdEvent": "EXC_SMC",
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+        "ArchStdEvent": "EXC_SMC"
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     },
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     {
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-        "ArchStdEvent": "EXC_HVC",
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+        "ArchStdEvent": "EXC_HVC"
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     },
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     {
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-        "ArchStdEvent": "EXC_TRAP_PABORT",
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+        "ArchStdEvent": "EXC_TRAP_PABORT"
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     },
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     {
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-        "ArchStdEvent": "EXC_TRAP_DABORT",
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+        "ArchStdEvent": "EXC_TRAP_DABORT"
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     },
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     {
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-        "ArchStdEvent": "EXC_TRAP_OTHER",
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+        "ArchStdEvent": "EXC_TRAP_OTHER"
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     },
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     {
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-        "ArchStdEvent": "EXC_TRAP_IRQ",
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+        "ArchStdEvent": "EXC_TRAP_IRQ"
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     },
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     {
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-        "ArchStdEvent": "EXC_TRAP_FIQ",
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+        "ArchStdEvent": "EXC_TRAP_FIQ"
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     }
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 ]