disable pwm7

hc

2024-05-10 23fa18eaa71266feff7ba8d83022d9e1cc83c65a

 kernel/tools/perf/arch/powerpc/util/perf_regs.c
..
..
@@ -2,11 +2,19 @@
2
2
 #include <errno.h>
3
3
 #include <string.h>
4
4
 #include <regex.h>
5
+#include <linux/zalloc.h>
5
6
 
6
-#include "../../perf.h"
7
-#include "../../util/util.h"
8
-#include "../../util/perf_regs.h"
9
-#include "../../util/debug.h"
7
+#include "../../../util/perf_regs.h"
8
+#include "../../../util/debug.h"
9
+#include "../../../util/event.h"
10
+#include "../../../util/header.h"
11
+#include "../../../perf-sys.h"
12
+#include "utils_header.h"
13
+
14
+#include <linux/kernel.h>
15
+
16
+#define PVR_POWER9		0x004E
17
+#define PVR_POWER10		0x0080
10
18
 
11
19
 const struct sample_reg sample_reg_masks[] = {
12
20
 	SMPL_REG(r0, PERF_REG_POWERPC_R0),
..
..
@@ -52,6 +60,14 @@
52
60
 	SMPL_REG(trap, PERF_REG_POWERPC_TRAP),
53
61
 	SMPL_REG(dar, PERF_REG_POWERPC_DAR),
54
62
 	SMPL_REG(dsisr, PERF_REG_POWERPC_DSISR),
63
+	SMPL_REG(sier, PERF_REG_POWERPC_SIER),
64
+	SMPL_REG(mmcra, PERF_REG_POWERPC_MMCRA),
65
+	SMPL_REG(mmcr0, PERF_REG_POWERPC_MMCR0),
66
+	SMPL_REG(mmcr1, PERF_REG_POWERPC_MMCR1),
67
+	SMPL_REG(mmcr2, PERF_REG_POWERPC_MMCR2),
68
+	SMPL_REG(mmcr3, PERF_REG_POWERPC_MMCR3),
69
+	SMPL_REG(sier2, PERF_REG_POWERPC_SIER2),
70
+	SMPL_REG(sier3, PERF_REG_POWERPC_SIER3),
55
71
 	SMPL_REG_END
56
72
 };
57
73
 
..
..
@@ -160,3 +176,45 @@
160
176
 
161
177
 	return SDT_ARG_VALID;
162
178
 }
179
+
180
+uint64_t arch__intr_reg_mask(void)
181
+{
182
+	struct perf_event_attr attr = {
183
+		.type                   = PERF_TYPE_HARDWARE,
184
+		.config                 = PERF_COUNT_HW_CPU_CYCLES,
185
+		.sample_type            = PERF_SAMPLE_REGS_INTR,
186
+		.precise_ip             = 1,
187
+		.disabled               = 1,
188
+		.exclude_kernel         = 1,
189
+	};
190
+	int fd;
191
+	u32 version;
192
+	u64 extended_mask = 0, mask = PERF_REGS_MASK;
193
+
194
+	/*
195
+	 * Get the PVR value to set the extended
196
+	 * mask specific to platform.
197
+	 */
198
+	version = (((mfspr(SPRN_PVR)) >>  16) & 0xFFFF);
199
+	if (version == PVR_POWER9)
200
+		extended_mask = PERF_REG_PMU_MASK_300;
201
+	else if (version == PVR_POWER10)
202
+		extended_mask = PERF_REG_PMU_MASK_31;
203
+	else
204
+		return mask;
205
+
206
+	attr.sample_regs_intr = extended_mask;
207
+	attr.sample_period = 1;
208
+	event_attr_init(&attr);
209
+
210
+	/*
211
+	 * check if the pmu supports perf extended regs, before
212
+	 * returning the register mask to sample.
213
+	 */
214
+	fd = sys_perf_event_open(&attr, 0, -1, -1, 0);
215
+	if (fd != -1) {
216
+		close(fd);
217
+		mask |= extended_mask;
218
+	}
219
+	return mask;
220
+}