disable pwm7

hc

2024-05-10 23fa18eaa71266feff7ba8d83022d9e1cc83c65a

 kernel/sound/soc/codecs/rt5677.h
..
..
@@ -1,12 +1,9 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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 /*
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  * rt5677.h  --  RT5677 ALSA SoC audio driver
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  *
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  * Copyright 2013 Realtek Semiconductor Corp.
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  * Author: Oder Chiou <oder_chiou@realtek.com>
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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  */
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 #ifndef __RT5677_H__
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@@ -1339,6 +1336,8 @@
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 #define RT5677_PLL_M_SFT			12
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 #define RT5677_PLL_M_BP				(0x1 << 11)
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 #define RT5677_PLL_M_BP_SFT			11
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+#define RT5677_PLL_UPDATE_PLL1			(0x1 << 1)
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+#define RT5677_PLL_UPDATE_PLL1_SFT		1
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 /* Global Clock Control 1 (0x80) */
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 #define RT5677_SCLK_SRC_MASK			(0x3 << 14)
..
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@@ -1456,9 +1455,37 @@
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 #define RT5677_I2S4_CLK_SEL_MASK		(0xf)
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 #define RT5677_I2S4_CLK_SEL_SFT			0
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+/* VAD Function Control 1 (0x9c) */
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+#define RT5677_VAD_MIN_DUR_MASK			(0x3 << 13)
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+#define RT5677_VAD_MIN_DUR_SFT			13
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+#define RT5677_VAD_ADPCM_BYPASS			(1 << 10)
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+#define RT5677_VAD_ADPCM_BYPASS_BIT		10
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+#define RT5677_VAD_FG2ENC			(1 << 9)
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+#define RT5677_VAD_FG2ENC_BIT			9
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+#define RT5677_VAD_BUF_OW			(1 << 8)
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+#define RT5677_VAD_BUF_OW_BIT			8
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+#define RT5677_VAD_CLR_FLAG			(1 << 7)
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+#define RT5677_VAD_CLR_FLAG_BIT			7
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+#define RT5677_VAD_BUF_POP			(1 << 6)
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+#define RT5677_VAD_BUF_POP_BIT			6
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+#define RT5677_VAD_BUF_PUSH			(1 << 5)
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+#define RT5677_VAD_BUF_PUSH_BIT			5
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+#define RT5677_VAD_DET_ENABLE			(1 << 4)
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+#define RT5677_VAD_DET_ENABLE_BIT		4
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+#define RT5677_VAD_FUNC_ENABLE			(1 << 3)
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+#define RT5677_VAD_FUNC_ENABLE_BIT		3
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+#define RT5677_VAD_FUNC_RESET			(1 << 2)
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+#define RT5677_VAD_FUNC_RESET_BIT		2
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+
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 /* VAD Function Control 4 (0x9f) */
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-#define RT5677_VAD_SRC_MASK			(0x7 << 8)
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+#define RT5677_VAD_OUT_SRC_RATE_MASK		(0x1 << 11)
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+#define RT5677_VAD_OUT_SRC_RATE_SFT		11
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+#define RT5677_VAD_OUT_SRC_MASK			(0x1 << 10)
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+#define RT5677_VAD_OUT_SRC_SFT			10
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+#define RT5677_VAD_SRC_MASK			(0x3 << 8)
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 #define RT5677_VAD_SRC_SFT			8
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+#define RT5677_VAD_LV_DIFF_MASK			(0xff << 0)
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+#define RT5677_VAD_LV_DIFF_SFT			0
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 /* DSP InBound Control (0xa3) */
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 #define RT5677_IB01_SRC_MASK			(0x7 << 12)
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@@ -1636,6 +1663,12 @@
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 #define RT5677_GPIO6_P_NOR			(0x0 << 0)
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 #define RT5677_GPIO6_P_INV			(0x1 << 0)
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+/* General Control (0xfa) */
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+#define RT5677_IRQ_DEBOUNCE_SEL_MASK		(0x3 << 3)
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+#define RT5677_IRQ_DEBOUNCE_SEL_MCLK		(0x0 << 3)
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+#define RT5677_IRQ_DEBOUNCE_SEL_RC		(0x1 << 3)
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+#define RT5677_IRQ_DEBOUNCE_SEL_SLIM		(0x2 << 3)
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+
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 /* Virtual DSP Mixer Control (0xf7 0xf8 0xf9) */
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 #define RT5677_DSP_IB_01_H			(0x1 << 15)
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 #define RT5677_DSP_IB_01_H_SFT			15
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@@ -1674,6 +1707,8 @@
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 #define RT5677_FIRMWARE1	"rt5677_dsp_fw1.bin"
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 #define RT5677_FIRMWARE2	"rt5677_dsp_fw2.bin"
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+#define RT5677_DRV_NAME		"rt5677"
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+
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 /* System Clock Source */
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 enum {
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 	RT5677_SCLK_S_MCLK,
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@@ -1697,6 +1732,7 @@
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 	RT5677_AIF4,
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 	RT5677_AIF5,
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 	RT5677_AIFS,
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+	RT5677_DSPBUFF,
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 };
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 enum {
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@@ -1713,6 +1749,7 @@
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 	RT5677_IRQ_JD1,
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 	RT5677_IRQ_JD2,
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 	RT5677_IRQ_JD3,
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+	RT5677_IRQ_NUM,
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 };
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 enum rt5677_type {
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@@ -1791,6 +1828,7 @@
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 struct rt5677_priv {
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 	struct snd_soc_component *component;
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+	struct device *dev;
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 	struct rt5677_platform_data pdata;
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 	struct regmap *regmap, *regmap_physical;
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 	const struct firmware *fw1, *fw2;
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@@ -1810,10 +1848,20 @@
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 #ifdef CONFIG_GPIOLIB
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 	struct gpio_chip gpio_chip;
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 #endif
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-	bool dsp_vad_en;
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-	struct regmap_irq_chip_data *irq_data;
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+	bool dsp_vad_en_request; /* DSP VAD enable/disable request */
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+	bool dsp_vad_en; /* dsp_work parameter */
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 	bool is_dsp_mode;
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 	bool is_vref_slow;
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+	struct delayed_work dsp_work;
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+
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+	/* Interrupt handling */
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+	struct irq_domain *domain;
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+	struct mutex irq_lock;
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+	unsigned int irq_en;
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+	struct delayed_work resume_irq_check;
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+	int irq;
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+
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+	int (*set_dsp_vad)(struct snd_soc_component *component, bool on);
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 };
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 int rt5677_sel_asrc_clk_src(struct snd_soc_component *component,