forked from ~ljy/RK356X_SDK_RELEASE
blame | history | patch | commit | commitdiff
hc
2024-05-10 23fa18eaa71266feff7ba8d83022d9e1cc83c65a 
 kernel/include/soc/rockchip/rockchip_opp_select.h
....@@ -6,13 +6,92 @@
66 #ifndef __SOC_ROCKCHIP_OPP_SELECT_H
77 #define __SOC_ROCKCHIP_OPP_SELECT_H
88 
9
+#define VOLT_RM_TABLE_END	~1
10
+
11
+/*
12
+ * [0]:      set intermediate rate
13
+ *           [1]: scaling up rate or scaling down rate
14
+ * [1]:      add length for pvtpll
15
+ *           [2:5]: length
16
+ * [2]:      use low length for pvtpll
17
+ * [3:5]:    reserved
18
+ */
19
+#define OPP_RATE_MASK		0x3f
20
+
21
+/* Set intermediate rate */
22
+#define OPP_INTERMEDIATE_RATE	BIT(0)
23
+#define OPP_SCALING_UP_RATE	BIT(1)
24
+#define OPP_SCALING_UP_INTER	(OPP_INTERMEDIATE_RATE | OPP_SCALING_UP_RATE)
25
+#define OPP_SCALING_DOWN_INTER	OPP_INTERMEDIATE_RATE
26
+
27
+/* Add length for pvtpll */
28
+#define OPP_ADD_LENGTH		BIT(1)
29
+#define OPP_LENGTH_MASK		0xf
30
+#define OPP_LENGTH_SHIFT	2
31
+
32
+/* Use low length for pvtpll */
33
+#define OPP_LENGTH_LOW		BIT(2)
34
+
35
+struct rockchip_opp_info;
36
+
37
+struct volt_rm_table {
38
+	int volt;
39
+	int rm;
40
+};
41
+
42
+struct rockchip_opp_data {
43
+	int (*get_soc_info)(struct device *dev, struct device_node *np,
44
+			    int *bin, int *process);
45
+	int (*set_soc_info)(struct device *dev, struct device_node *np,
46
+			    int bin, int process, int volt_sel);
47
+	int (*set_read_margin)(struct device *dev,
48
+			       struct rockchip_opp_info *opp_info,
49
+			       u32 rm);
50
+};
51
+
52
+struct pvtpll_opp_table {
53
+	unsigned long rate;
54
+	unsigned long u_volt;
55
+	unsigned long u_volt_min;
56
+	unsigned long u_volt_max;
57
+	unsigned long u_volt_mem;
58
+	unsigned long u_volt_mem_min;
59
+	unsigned long u_volt_mem_max;
60
+};
61
+
62
+struct rockchip_opp_info {
63
+	struct device *dev;
64
+	struct pvtpll_opp_table *opp_table;
65
+	const struct rockchip_opp_data *data;
66
+	struct volt_rm_table *volt_rm_tbl;
67
+	struct regmap *grf;
68
+	struct regmap *dsu_grf;
69
+	struct clk_bulk_data *clks;
70
+	struct clk *scmi_clk;
71
+	/* The threshold frequency for set intermediate rate */
72
+	unsigned long intermediate_threshold_freq;
73
+	unsigned int pvtpll_avg_offset;
74
+	unsigned int pvtpll_min_rate;
75
+	unsigned int pvtpll_volt_step;
76
+	int num_clks;
77
+	/* The read margin for low voltage */
78
+	u32 low_rm;
79
+	u32 current_rm;
80
+	u32 target_rm;
81
+	u32 pvtpll_clk_id;
82
+	bool pvtpll_low_temp;
83
+};
84
+
985 #if IS_ENABLED(CONFIG_ROCKCHIP_OPP)
1086 int rockchip_of_get_leakage(struct device *dev, char *lkg_name, int *leakage);
1187 void rockchip_of_get_lkg_sel(struct device *dev, struct device_node *np,
1288 			     char *lkg_name, int process,
1389 			     int *volt_sel, int *scale_sel);
90
+void rockchip_pvtpll_calibrate_opp(struct rockchip_opp_info *info);
91
+void rockchip_pvtpll_add_length(struct rockchip_opp_info *info);
92
+void rockchip_init_pvtpll_table(struct rockchip_opp_info *info, int bin);
1493 void rockchip_of_get_pvtm_sel(struct device *dev, struct device_node *np,
15
-			      char *reg_name, int process,
94
+			      char *reg_name, int bin, int process,
1695 			      int *volt_sel, int *scale_sel);
1796 void rockchip_of_get_bin_sel(struct device *dev, struct device_node *np,
1897 			     int bin, int *scale_sel);
....@@ -22,23 +101,45 @@
22101 				u8 *val);
23102 int rockchip_nvmem_cell_read_u16(struct device_node *np, const char *cell_id,
24103 				 u16 *val);
25
-void rockchip_get_soc_info(struct device *dev,
26
-			   const struct of_device_id *matches,
27
-			   int *bin, int *process);
104
+int rockchip_get_volt_rm_table(struct device *dev, struct device_node *np,
105
+			       char *porp_name, struct volt_rm_table **table);
106
+void rockchip_get_opp_data(const struct of_device_id *matches,
107
+			   struct rockchip_opp_info *info);
108
+int rockchip_get_soc_info(struct device *dev, struct device_node *np, int *bin,
109
+			  int *process);
28110 void rockchip_get_scale_volt_sel(struct device *dev, char *lkg_name,
29111 				 char *reg_name, int bin, int process,
30112 				 int *scale, int *volt_sel);
31113 struct opp_table *rockchip_set_opp_prop_name(struct device *dev, int process,
32114 					     int volt_sel);
115
+struct opp_table *rockchip_set_opp_supported_hw(struct device *dev,
116
+						struct device_node *np,
117
+						int bin, int volt_sel);
33118 int rockchip_adjust_power_scale(struct device *dev, int scale);
119
+int rockchip_get_read_margin(struct device *dev,
120
+			     struct rockchip_opp_info *opp_info,
121
+			     unsigned long volt, u32 *target_rm);
122
+int rockchip_set_read_margin(struct device *dev,
123
+			     struct rockchip_opp_info *opp_info, u32 rm,
124
+			     bool is_set_rm);
125
+int rockchip_init_read_margin(struct device *dev,
126
+			      struct rockchip_opp_info *opp_info,
127
+			      char *reg_name);
128
+int rockchip_set_intermediate_rate(struct device *dev,
129
+				   struct rockchip_opp_info *opp_info,
130
+				   struct clk *clk, unsigned long old_freq,
131
+				   unsigned long new_freq, bool is_scaling_up,
132
+				   bool is_set_clk);
34133 int rockchip_init_opp_table(struct device *dev,
35
-			    const struct of_device_id *matches,
134
+			    struct rockchip_opp_info *info,
36135 			    char *lkg_name, char *reg_name);
136
+void rockchip_uninit_opp_table(struct device *dev,
137
+			       struct rockchip_opp_info *info);
37138 #else
38139 static inline int rockchip_of_get_leakage(struct device *dev, char *lkg_name,
39140 					  int *leakage)
40141 {
41
-	return -ENOTSUPP;
142
+	return -EOPNOTSUPP;
42143 }
43144 
44145 static inline void rockchip_of_get_lkg_sel(struct device *dev,
....@@ -48,9 +149,22 @@
48149 {
49150 }
50151 
152
+static inline void rockchip_pvtpll_calibrate_opp(struct rockchip_opp_info *info)
153
+{
154
+}
155
+
156
+static inline void rockchip_pvtpll_add_length(struct rockchip_opp_info *info)
157
+{
158
+}
159
+
160
+static inline void rockchip_init_pvtpll_table(struct rockchip_opp_info *info,
161
+					      int bin)
162
+{
163
+}
164
+
51165 static inline void rockchip_of_get_pvtm_sel(struct device *dev,
52166 					    struct device_node *np,
53
-					    char *reg_name, int process,
167
+					    char *reg_name, int bin, int process,
54168 					    int *volt_sel, int *scale_sel)
55169 {
56170 }
....@@ -79,10 +193,24 @@
79193 	return -EOPNOTSUPP;
80194 }
81195 
82
-static inline void rockchip_get_soc_info(struct device *dev,
83
-					 const struct of_device_id *matches,
84
-					 int *bin, int *process)
196
+static inline int rockchip_get_volt_rm_table(struct device *dev,
197
+					     struct device_node *np,
198
+					     char *porp_name,
199
+					     struct volt_rm_table **table)
85200 {
201
+	return -EOPNOTSUPP;
202
+
203
+}
204
+
205
+static inline void rockchip_get_opp_data(const struct of_device_id *matches,
206
+					 struct rockchip_opp_info *info)
207
+{
208
+}
209
+static inline int rockchip_get_soc_info(struct device *dev,
210
+					struct device_node *np, int *bin,
211
+					int *process)
212
+{
213
+	return -EOPNOTSUPP;
86214 }
87215 
88216 static inline void rockchip_get_scale_volt_sel(struct device *dev,
....@@ -96,19 +224,61 @@
96224 							   int process,
97225 							   int volt_sel)
98226 {
99
-	return ERR_PTR(-ENOTSUPP);
227
+	return ERR_PTR(-EOPNOTSUPP);
228
+}
229
+
230
+static inline struct opp_table *rockchip_set_opp_supported_hw(struct device *dev,
231
+							      struct device_node *np,
232
+							      int bin, int volt_sel)
233
+{
234
+	return ERR_PTR(-EOPNOTSUPP);
100235 }
101236 
102237 static inline int rockchip_adjust_power_scale(struct device *dev, int scale)
103238 {
104
-	return -ENOTSUPP;
239
+	return -EOPNOTSUPP;
240
+}
241
+
242
+static inline int rockchip_get_read_margin(struct device *dev,
243
+					   struct rockchip_opp_info *opp_info,
244
+					   unsigned long volt, u32 *target_rm)
245
+{
246
+	return -EOPNOTSUPP;
247
+}
248
+static inline int rockchip_set_read_margin(struct device *dev,
249
+					   struct rockchip_opp_info *opp_info,
250
+					   u32 rm, bool is_set_rm)
251
+{
252
+	return -EOPNOTSUPP;
253
+}
254
+
255
+static inline int rockchip_init_read_margin(struct device *dev,
256
+					    struct rockchip_opp_info *opp_info,
257
+					    char *reg_name)
258
+{
259
+	return -EOPNOTSUPP;
260
+}
261
+
262
+static inline int
263
+rockchip_set_intermediate_rate(struct device *dev,
264
+			       struct rockchip_opp_info *opp_info,
265
+			       struct clk *clk, unsigned long old_freq,
266
+			       unsigned long new_freq, bool is_scaling_up,
267
+			       bool is_set_clk)
268
+{
269
+	return -EOPNOTSUPP;
105270 }
106271 
107272 static inline int rockchip_init_opp_table(struct device *dev,
108
-					  const struct of_device_id *matches,
273
+					  struct rockchip_opp_info *info,
109274 					  char *lkg_name, char *reg_name)
110275 {
111
-	return -ENOTSUPP;
276
+	return -EOPNOTSUPP;
277
+}
278
+
279
+static inline void rockchip_uninit_opp_table(struct device *dev,
280
+					     struct rockchip_opp_info *info)
281
+{
112282 }
113283 
114284 #endif /* CONFIG_ROCKCHIP_OPP */