forked from ~ljy/RK356X_SDK_RELEASE

blame | history | patch | commit | commitdiff
hc
2024-05-10 23fa18eaa71266feff7ba8d83022d9e1cc83c65a 
 kernel/include/linux/qed/qed_if.h
....@@ -1,33 +1,7 @@
1
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
12 /* QLogic qed NIC Driver
23  * Copyright (c) 2015-2017  QLogic Corporation
3
- *
4
- * This software is available to you under a choice of one of two
5
- * licenses.  You may choose to be licensed under the terms of the GNU
6
- * General Public License (GPL) Version 2, available from the file
7
- * COPYING in the main directory of this source tree, or the
8
- * OpenIB.org BSD license below:
9
- *
10
- *     Redistribution and use in source and binary forms, with or
11
- *     without modification, are permitted provided that the following
12
- *     conditions are met:
13
- *
14
- *      - Redistributions of source code must retain the above
15
- *        copyright notice, this list of conditions and the following
16
- *        disclaimer.
17
- *
18
- *      - Redistributions in binary form must reproduce the above
19
- *        copyright notice, this list of conditions and the following
20
- *        disclaimer in the documentation and /or other materials
21
- *        provided with the distribution.
22
- *
23
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30
- * SOFTWARE.
4
+ * Copyright (c) 2019-2020 Marvell International Ltd.
315  */
326 
337 #ifndef _QED_IF_H
....@@ -38,7 +12,6 @@
3812 #include <linux/netdevice.h>
3913 #include <linux/pci.h>
4014 #include <linux/skbuff.h>
41
-#include <linux/types.h>
4215 #include <asm/byteorder.h>
4316 #include <linux/io.h>
4417 #include <linux/compiler.h>
....@@ -47,6 +20,8 @@
4720 #include <linux/slab.h>
4821 #include <linux/qed/common_hsi.h>
4922 #include <linux/qed/qed_chain.h>
23
+#include <linux/io-64-nonatomic-lo-hi.h>
24
+#include <net/devlink.h>
5025 
5126 enum dcbx_protocol_type {
5227 	DCBX_PROTOCOL_ISCSI,
....@@ -159,6 +134,7 @@
159134 enum qed_nvm_images {
160135 	QED_NVM_IMAGE_ISCSI_CFG,
161136 	QED_NVM_IMAGE_FCOE_CFG,
137
+	QED_NVM_IMAGE_MDUMP,
162138 	QED_NVM_IMAGE_NVM_CFG1,
163139 	QED_NVM_IMAGE_DEFAULT_CFG,
164140 	QED_NVM_IMAGE_NVM_META,
....@@ -448,10 +424,23 @@
448424 	bool tx_bytes_set;
449425 };
450426 
427
+enum qed_db_rec_width {
428
+	DB_REC_WIDTH_32B,
429
+	DB_REC_WIDTH_64B,
430
+};
431
+
432
+enum qed_db_rec_space {
433
+	DB_REC_KERNEL,
434
+	DB_REC_USER,
435
+};
436
+
451437 #define DIRECT_REG_WR(reg_addr, val) writel((u32)val, \
452438 					    (void __iomem *)(reg_addr))
453439 
454440 #define DIRECT_REG_RD(reg_addr) readl((void __iomem *)(reg_addr))
441
+
442
+#define DIRECT_REG_WR64(reg_addr, val) writeq((u64)val,	\
443
+					      (void __iomem *)(reg_addr))
455444 
456445 #define QED_COALESCE_MAX 0x1FF
457446 #define QED_DEFAULT_RX_USECS 12
....@@ -510,7 +499,7 @@
510499 	u8 bdq_pbl_num_entries[2];
511500 };
512501 
513
-/* Most of the the parameters below are described in the FW iSCSI / TCP HSI */
502
+/* Most of the parameters below are described in the FW iSCSI / TCP HSI */
514503 struct qed_iscsi_pf_params {
515504 	u64 glbl_q_params_addr;
516505 	u64 bdq_pbl_base_addr[3];
....@@ -593,9 +582,20 @@
593582 	struct qed_dev *cdev;
594583 };
595584 
585
+enum qed_hw_err_type {
586
+	QED_HW_ERR_FAN_FAIL,
587
+	QED_HW_ERR_MFW_RESP_FAIL,
588
+	QED_HW_ERR_HW_ATTN,
589
+	QED_HW_ERR_DMAE_FAIL,
590
+	QED_HW_ERR_RAMROD_FAIL,
591
+	QED_HW_ERR_FW_ASSERT,
592
+	QED_HW_ERR_LAST,
593
+};
594
+
596595 enum qed_dev_type {
597596 	QED_DEV_TYPE_BB,
598597 	QED_DEV_TYPE_AH,
598
+	QED_DEV_TYPE_E5,
599599 };
600600 
601601 struct qed_dev_info {
....@@ -624,12 +624,14 @@
624624 #define QED_MFW_VERSION_3_OFFSET	24
625625 
626626 	u32		flash_size;
627
+	bool		b_arfs_capable;
627628 	bool		b_inter_pf_switch;
628629 	bool		tx_switching;
629630 	bool		rdma_supported;
630631 	u16		mtu;
631632 
632633 	bool wol_support;
634
+	bool smart_an;
633635 
634636 	/* MBI version */
635637 	u32 mbi_version;
....@@ -662,66 +664,72 @@
662664 	QED_PROTOCOL_FCOE,
663665 };
664666 
665
-enum qed_link_mode_bits {
666
-	QED_LM_FIBRE_BIT = BIT(0),
667
-	QED_LM_Autoneg_BIT = BIT(1),
668
-	QED_LM_Asym_Pause_BIT = BIT(2),
669
-	QED_LM_Pause_BIT = BIT(3),
670
-	QED_LM_1000baseT_Half_BIT = BIT(4),
671
-	QED_LM_1000baseT_Full_BIT = BIT(5),
672
-	QED_LM_10000baseKR_Full_BIT = BIT(6),
673
-	QED_LM_25000baseKR_Full_BIT = BIT(7),
674
-	QED_LM_40000baseLR4_Full_BIT = BIT(8),
675
-	QED_LM_50000baseKR2_Full_BIT = BIT(9),
676
-	QED_LM_100000baseKR4_Full_BIT = BIT(10),
677
-	QED_LM_COUNT = 11
667
+enum qed_fec_mode {
668
+	QED_FEC_MODE_NONE			= BIT(0),
669
+	QED_FEC_MODE_FIRECODE			= BIT(1),
670
+	QED_FEC_MODE_RS				= BIT(2),
671
+	QED_FEC_MODE_AUTO			= BIT(3),
672
+	QED_FEC_MODE_UNSUPPORTED		= BIT(4),
678673 };
679674 
680675 struct qed_link_params {
681
-	bool	link_up;
676
+	bool					link_up;
682677 
683
-#define QED_LINK_OVERRIDE_SPEED_AUTONEG         BIT(0)
684
-#define QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS      BIT(1)
685
-#define QED_LINK_OVERRIDE_SPEED_FORCED_SPEED    BIT(2)
686
-#define QED_LINK_OVERRIDE_PAUSE_CONFIG          BIT(3)
687
-#define QED_LINK_OVERRIDE_LOOPBACK_MODE         BIT(4)
688
-#define QED_LINK_OVERRIDE_EEE_CONFIG            BIT(5)
689
-	u32	override_flags;
690
-	bool	autoneg;
691
-	u32	adv_speeds;
692
-	u32	forced_speed;
693
-#define QED_LINK_PAUSE_AUTONEG_ENABLE           BIT(0)
694
-#define QED_LINK_PAUSE_RX_ENABLE                BIT(1)
695
-#define QED_LINK_PAUSE_TX_ENABLE                BIT(2)
696
-	u32	pause_config;
697
-#define QED_LINK_LOOPBACK_NONE                  BIT(0)
698
-#define QED_LINK_LOOPBACK_INT_PHY               BIT(1)
699
-#define QED_LINK_LOOPBACK_EXT_PHY               BIT(2)
700
-#define QED_LINK_LOOPBACK_EXT                   BIT(3)
701
-#define QED_LINK_LOOPBACK_MAC                   BIT(4)
702
-	u32	loopback_mode;
703
-	struct qed_link_eee_params eee;
678
+	u32					override_flags;
679
+#define QED_LINK_OVERRIDE_SPEED_AUTONEG		BIT(0)
680
+#define QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS	BIT(1)
681
+#define QED_LINK_OVERRIDE_SPEED_FORCED_SPEED	BIT(2)
682
+#define QED_LINK_OVERRIDE_PAUSE_CONFIG		BIT(3)
683
+#define QED_LINK_OVERRIDE_LOOPBACK_MODE		BIT(4)
684
+#define QED_LINK_OVERRIDE_EEE_CONFIG		BIT(5)
685
+#define QED_LINK_OVERRIDE_FEC_CONFIG		BIT(6)
686
+
687
+	bool					autoneg;
688
+	__ETHTOOL_DECLARE_LINK_MODE_MASK(adv_speeds);
689
+	u32					forced_speed;
690
+
691
+	u32					pause_config;
692
+#define QED_LINK_PAUSE_AUTONEG_ENABLE		BIT(0)
693
+#define QED_LINK_PAUSE_RX_ENABLE		BIT(1)
694
+#define QED_LINK_PAUSE_TX_ENABLE		BIT(2)
695
+
696
+	u32					loopback_mode;
697
+#define QED_LINK_LOOPBACK_NONE			BIT(0)
698
+#define QED_LINK_LOOPBACK_INT_PHY		BIT(1)
699
+#define QED_LINK_LOOPBACK_EXT_PHY		BIT(2)
700
+#define QED_LINK_LOOPBACK_EXT			BIT(3)
701
+#define QED_LINK_LOOPBACK_MAC			BIT(4)
702
+#define QED_LINK_LOOPBACK_CNIG_AH_ONLY_0123	BIT(5)
703
+#define QED_LINK_LOOPBACK_CNIG_AH_ONLY_2301	BIT(6)
704
+#define QED_LINK_LOOPBACK_PCS_AH_ONLY		BIT(7)
705
+#define QED_LINK_LOOPBACK_REVERSE_MAC_AH_ONLY	BIT(8)
706
+#define QED_LINK_LOOPBACK_INT_PHY_FEA_AH_ONLY	BIT(9)
707
+
708
+	struct qed_link_eee_params		eee;
709
+	u32					fec;
704710 };
705711 
706712 struct qed_link_output {
707
-	bool	link_up;
713
+	bool					link_up;
708714 
709
-	/* In QED_LM_* defs */
710
-	u32	supported_caps;
711
-	u32	advertised_caps;
712
-	u32	lp_caps;
715
+	__ETHTOOL_DECLARE_LINK_MODE_MASK(supported_caps);
716
+	__ETHTOOL_DECLARE_LINK_MODE_MASK(advertised_caps);
717
+	__ETHTOOL_DECLARE_LINK_MODE_MASK(lp_caps);
713718 
714
-	u32	speed;                  /* In Mb/s */
715
-	u8	duplex;                 /* In DUPLEX defs */
716
-	u8	port;                   /* In PORT defs */
717
-	bool	autoneg;
718
-	u32	pause_config;
719
+	u32					speed;	   /* In Mb/s */
720
+	u8					duplex;	   /* In DUPLEX defs */
721
+	u8					port;	   /* In PORT defs */
722
+	bool					autoneg;
723
+	u32					pause_config;
719724 
720725 	/* EEE - capability & param */
721
-	bool eee_supported;
722
-	bool eee_active;
723
-	u8 sup_caps;
724
-	struct qed_link_eee_params eee;
726
+	bool					eee_supported;
727
+	bool					eee_active;
728
+	u8					sup_caps;
729
+	struct qed_link_eee_params		eee;
730
+
731
+	u32					sup_fec;
732
+	u32					active_fec;
725733 };
726734 
727735 struct qed_probe_params {
....@@ -729,6 +737,7 @@
729737 	u32 dp_module;
730738 	u8 dp_level;
731739 	bool is_vf;
740
+	bool recov_in_prog;
732741 };
733742 
734743 #define QED_DRV_VER_STR_SIZE 12
....@@ -768,16 +777,25 @@
768777 	QED_NVM_FLASH_CMD_FILE_DATA = 0x2,
769778 	QED_NVM_FLASH_CMD_FILE_START = 0x3,
770779 	QED_NVM_FLASH_CMD_NVM_CHANGE = 0x4,
780
+	QED_NVM_FLASH_CMD_NVM_CFG_ID = 0x5,
771781 	QED_NVM_FLASH_CMD_NVM_MAX,
782
+};
783
+
784
+struct qed_devlink {
785
+	struct qed_dev *cdev;
786
+	struct devlink_health_reporter *fw_reporter;
772787 };
773788 
774789 struct qed_common_cb_ops {
775790 	void (*arfs_filter_op)(void *dev, void *fltr, u8 fw_rc);
776
-	void	(*link_update)(void			*dev,
777
-			       struct qed_link_output	*link);
778
-	void	(*dcbx_aen)(void *dev, struct qed_dcbx_get *get, u32 mib_type);
791
+	void (*link_update)(void *dev, struct qed_link_output *link);
792
+	void (*schedule_recovery_handler)(void *dev);
793
+	void (*schedule_hw_err_handler)(void *dev,
794
+					enum qed_hw_err_type err_type);
795
+	void (*dcbx_aen)(void *dev, struct qed_dcbx_get *get, u32 mib_type);
779796 	void (*get_generic_tlv_data)(void *dev, struct qed_generic_tlvs *data);
780797 	void (*get_protocol_tlv_data)(void *dev, void *data);
798
+	void (*bw_update)(void *dev);
781799 };
782800 
783801 struct qed_selftest_ops {
....@@ -833,10 +851,9 @@
833851 	struct qed_dev*	(*probe)(struct pci_dev *dev,
834852 				 struct qed_probe_params *params);
835853 
836
-	void		(*remove)(struct qed_dev *cdev);
854
+	void (*remove)(struct qed_dev *cdev);
837855 
838
-	int		(*set_power_state)(struct qed_dev *cdev,
839
-					   pci_power_t state);
856
+	int (*set_power_state)(struct qed_dev *cdev, pci_power_t state);
840857 
841858 	void (*set_name) (struct qed_dev *cdev, char name[]);
842859 
....@@ -844,49 +861,51 @@
844861 	 * PF params required for the call before slowpath_start is
845862 	 * documented within the qed_pf_params structure definition.
846863 	 */
847
-	void		(*update_pf_params)(struct qed_dev *cdev,
848
-					    struct qed_pf_params *params);
849
-	int		(*slowpath_start)(struct qed_dev *cdev,
850
-					  struct qed_slowpath_params *params);
864
+	void (*update_pf_params)(struct qed_dev *cdev,
865
+				 struct qed_pf_params *params);
851866 
852
-	int		(*slowpath_stop)(struct qed_dev *cdev);
867
+	int (*slowpath_start)(struct qed_dev *cdev,
868
+			      struct qed_slowpath_params *params);
869
+
870
+	int (*slowpath_stop)(struct qed_dev *cdev);
853871 
854872 	/* Requests to use `cnt' interrupts for fastpath.
855873 	 * upon success, returns number of interrupts allocated for fastpath.
856874 	 */
857
-	int		(*set_fp_int)(struct qed_dev *cdev,
858
-				      u16 cnt);
875
+	int (*set_fp_int)(struct qed_dev *cdev, u16 cnt);
859876 
860877 	/* Fills `info' with pointers required for utilizing interrupts */
861
-	int		(*get_fp_int)(struct qed_dev *cdev,
862
-				      struct qed_int_info *info);
878
+	int (*get_fp_int)(struct qed_dev *cdev, struct qed_int_info *info);
863879 
864
-	u32		(*sb_init)(struct qed_dev *cdev,
865
-				   struct qed_sb_info *sb_info,
866
-				   void *sb_virt_addr,
867
-				   dma_addr_t sb_phy_addr,
868
-				   u16 sb_id,
869
-				   enum qed_sb_type type);
880
+	u32 (*sb_init)(struct qed_dev *cdev,
881
+		       struct qed_sb_info *sb_info,
882
+		       void *sb_virt_addr,
883
+		       dma_addr_t sb_phy_addr,
884
+		       u16 sb_id,
885
+		       enum qed_sb_type type);
870886 
871
-	u32		(*sb_release)(struct qed_dev *cdev,
872
-				      struct qed_sb_info *sb_info,
873
-				      u16 sb_id);
887
+	u32 (*sb_release)(struct qed_dev *cdev,
888
+			  struct qed_sb_info *sb_info,
889
+			  u16 sb_id,
890
+			  enum qed_sb_type type);
874891 
875
-	void		(*simd_handler_config)(struct qed_dev *cdev,
876
-					       void *token,
877
-					       int index,
878
-					       void (*handler)(void *));
892
+	void (*simd_handler_config)(struct qed_dev *cdev,
893
+				    void *token,
894
+				    int index,
895
+				    void (*handler)(void *));
879896 
880
-	void		(*simd_handler_clean)(struct qed_dev *cdev,
881
-					      int index);
882
-	int (*dbg_grc)(struct qed_dev *cdev,
883
-		       void *buffer, u32 *num_dumped_bytes);
897
+	void (*simd_handler_clean)(struct qed_dev *cdev, int index);
898
+
899
+	int (*dbg_grc)(struct qed_dev *cdev, void *buffer, u32 *num_dumped_bytes);
884900 
885901 	int (*dbg_grc_size)(struct qed_dev *cdev);
886902 
887
-	int (*dbg_all_data) (struct qed_dev *cdev, void *buffer);
903
+	int (*dbg_all_data)(struct qed_dev *cdev, void *buffer);
888904 
889
-	int (*dbg_all_data_size) (struct qed_dev *cdev);
905
+	int (*dbg_all_data_size)(struct qed_dev *cdev);
906
+
907
+	int (*report_fatal_error)(struct devlink *devlink,
908
+				  enum qed_hw_err_type err_type);
890909 
891910 /**
892911  * @brief can_link_change - can the instance change the link or not
....@@ -936,13 +955,8 @@
936955 					 u8 dp_level);
937956 
938957 	int		(*chain_alloc)(struct qed_dev *cdev,
939
-				       enum qed_chain_use_mode intended_use,
940
-				       enum qed_chain_mode mode,
941
-				       enum qed_chain_cnt_type cnt_type,
942
-				       u32 num_elems,
943
-				       size_t elem_size,
944
-				       struct qed_chain *p_chain,
945
-				       struct qed_chain_ext_pbl *ext_pbl);
958
+				       struct qed_chain *chain,
959
+				       struct qed_chain_init_params *params);
946960 
947961 	void		(*chain_free)(struct qed_dev *cdev,
948962 				      struct qed_chain *p_chain);
....@@ -996,6 +1010,60 @@
9961010 		       enum qed_led_mode mode);
9971011 
9981012 /**
1013
+ * @brief attn_clr_enable - Prevent attentions from being reasserted
1014
+ *
1015
+ * @param cdev
1016
+ * @param clr_enable
1017
+ */
1018
+	void (*attn_clr_enable)(struct qed_dev *cdev, bool clr_enable);
1019
+
1020
+/**
1021
+ * @brief db_recovery_add - add doorbell information to the doorbell
1022
+ * recovery mechanism.
1023
+ *
1024
+ * @param cdev
1025
+ * @param db_addr - doorbell address
1026
+ * @param db_data - address of where db_data is stored
1027
+ * @param db_is_32b - doorbell is 32b pr 64b
1028
+ * @param db_is_user - doorbell recovery addresses are user or kernel space
1029
+ */
1030
+	int (*db_recovery_add)(struct qed_dev *cdev,
1031
+			       void __iomem *db_addr,
1032
+			       void *db_data,
1033
+			       enum qed_db_rec_width db_width,
1034
+			       enum qed_db_rec_space db_space);
1035
+
1036
+/**
1037
+ * @brief db_recovery_del - remove doorbell information from the doorbell
1038
+ * recovery mechanism. db_data serves as key (db_addr is not unique).
1039
+ *
1040
+ * @param cdev
1041
+ * @param db_addr - doorbell address
1042
+ * @param db_data - address where db_data is stored. Serves as key for the
1043
+ *		    entry to delete.
1044
+ */
1045
+	int (*db_recovery_del)(struct qed_dev *cdev,
1046
+			       void __iomem *db_addr, void *db_data);
1047
+
1048
+/**
1049
+ * @brief recovery_process - Trigger a recovery process
1050
+ *
1051
+ * @param cdev
1052
+ *
1053
+ * @return 0 on success, error otherwise.
1054
+ */
1055
+	int (*recovery_process)(struct qed_dev *cdev);
1056
+
1057
+/**
1058
+ * @brief recovery_prolog - Execute the prolog operations of a recovery process
1059
+ *
1060
+ * @param cdev
1061
+ *
1062
+ * @return 0 on success, error otherwise.
1063
+ */
1064
+	int (*recovery_prolog)(struct qed_dev *cdev);
1065
+
1066
+/**
9991067  * @brief update_drv_state - API to inform the change in the driver state.
10001068  *
10011069  * @param cdev
....@@ -1041,6 +1109,45 @@
10411109  */
10421110 	int (*read_module_eeprom)(struct qed_dev *cdev,
10431111 				  char *buf, u8 dev_addr, u32 offset, u32 len);
1112
+
1113
+/**
1114
+ * @brief get_affin_hwfn_idx
1115
+ *
1116
+ * @param cdev
1117
+ */
1118
+	u8 (*get_affin_hwfn_idx)(struct qed_dev *cdev);
1119
+
1120
+/**
1121
+ * @brief read_nvm_cfg - Read NVM config attribute value.
1122
+ * @param cdev
1123
+ * @param buf - buffer
1124
+ * @param cmd - NVM CFG command id
1125
+ * @param entity_id - Entity id
1126
+ *
1127
+ */
1128
+	int (*read_nvm_cfg)(struct qed_dev *cdev, u8 **buf, u32 cmd,
1129
+			    u32 entity_id);
1130
+/**
1131
+ * @brief read_nvm_cfg - Read NVM config attribute value.
1132
+ * @param cdev
1133
+ * @param cmd - NVM CFG command id
1134
+ *
1135
+ * @return config id length, 0 on error.
1136
+ */
1137
+	int (*read_nvm_cfg_len)(struct qed_dev *cdev, u32 cmd);
1138
+
1139
+/**
1140
+ * @brief set_grc_config - Configure value for grc config id.
1141
+ * @param cdev
1142
+ * @param cfg_id - grc config id
1143
+ * @param val - grc config value
1144
+ *
1145
+ */
1146
+	int (*set_grc_config)(struct qed_dev *cdev, u32 cfg_id, u32 val);
1147
+
1148
+	struct devlink* (*devlink_register)(struct qed_dev *cdev);
1149
+
1150
+	void (*devlink_unregister)(struct devlink *devlink);
10441151 };
10451152 
10461153 #define MASK_FIELD(_name, _value) \
....@@ -1057,6 +1164,17 @@
10571164 
10581165 #define GET_FIELD(value, name) \
10591166 	(((value) >> (name ## _SHIFT)) & name ## _MASK)
1167
+
1168
+#define GET_MFW_FIELD(name, field) \
1169
+	(((name) & (field ## _MASK)) >> (field ## _OFFSET))
1170
+
1171
+#define SET_MFW_FIELD(name, field, value)				 \
1172
+	do {								 \
1173
+		(name) &= ~(field ## _MASK);				 \
1174
+		(name) |= (((value) << (field ## _OFFSET)) & (field ## _MASK));\
1175
+	} while (0)
1176
+
1177
+#define DB_ADDR_SHIFT(addr) ((addr) << DB_PWM_ADDR_OFFSET_SHIFT)
10601178 
10611179 /* Debug print definitions */
10621180 #define DP_ERR(cdev, fmt, ...)					\
....@@ -1256,7 +1374,6 @@
12561374 	}
12571375 
12581376 	/* Let SB update */
1259
-	mmiowb();
12601377 	return rc;
12611378 }
12621379 
....@@ -1278,21 +1395,19 @@
12781395 			      enum igu_int_cmd int_cmd,
12791396 			      u8 upd_flg)
12801397 {
1281
-	struct igu_prod_cons_update igu_ack = { 0 };
1398
+	u32 igu_ack;
12821399 
1283
-	igu_ack.sb_id_and_flags =
1284
-		((sb_info->sb_ack << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
1285
-		 (upd_flg << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
1286
-		 (int_cmd << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) |
1287
-		 (IGU_SEG_ACCESS_REG <<
1288
-		  IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));
1400
+	igu_ack = ((sb_info->sb_ack << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
1401
+		   (upd_flg << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
1402
+		   (int_cmd << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) |
1403
+		   (IGU_SEG_ACCESS_REG <<
1404
+		    IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));
12891405 
1290
-	DIRECT_REG_WR(sb_info->igu_addr, igu_ack.sb_id_and_flags);
1406
+	DIRECT_REG_WR(sb_info->igu_addr, igu_ack);
12911407 
12921408 	/* Both segments (interrupts & acks) are written to same place address;
12931409 	 * Need to guarantee all commands will be received (in-order) by HW.
12941410 	 */
1295
-	mmiowb();
12961411 	barrier();
12971412 }
12981413