disable pwm7

hc

2024-05-10 23fa18eaa71266feff7ba8d83022d9e1cc83c65a

 kernel/include/linux/qed/common_hsi.h
..
..
@@ -1,33 +1,7 @@
1
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
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 /* QLogic qed NIC Driver
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  * Copyright (c) 2015-2016  QLogic Corporation
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- *
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- * This software is available to you under a choice of one of two
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- * licenses.  You may choose to be licensed under the terms of the GNU
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- * General Public License (GPL) Version 2, available from the file
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- * COPYING in the main directory of this source tree, or the
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- * OpenIB.org BSD license below:
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- *
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- *     Redistribution and use in source and binary forms, with or
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- *     without modification, are permitted provided that the following
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- *     conditions are met:
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- *
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- *      - Redistributions of source code must retain the above
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- *        copyright notice, this list of conditions and the following
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- *        disclaimer.
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- *
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- *      - Redistributions in binary form must reproduce the above
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- *        copyright notice, this list of conditions and the following
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- *        disclaimer in the documentation and /or other materials
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- *        provided with the distribution.
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- *
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- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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- * SOFTWARE.
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+ * Copyright (c) 2019-2020 Marvell International Ltd.
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  */
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 #ifndef _COMMON_HSI_H
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@@ -76,7 +50,6 @@
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50
 
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 #define FW_ASSERT_GENERAL_ATTN_IDX		32
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52
 
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-#define MAX_PINNED_CCFC				32
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 /* Queue Zone sizes in bytes */
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 #define TSTORM_QZONE_SIZE	8
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@@ -105,12 +78,19 @@
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 #define CORE_SPQE_PAGE_SIZE_BYTES	4096
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-#define MAX_NUM_LL2_RX_QUEUES		48
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-#define MAX_NUM_LL2_TX_STATS_COUNTERS	48
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+/* Number of LL2 RAM based queues */
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+#define MAX_NUM_LL2_RX_RAM_QUEUES 32
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+
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+/* Number of LL2 context based queues */
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+#define MAX_NUM_LL2_RX_CTX_QUEUES 208
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+#define MAX_NUM_LL2_RX_QUEUES \
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+	(MAX_NUM_LL2_RX_RAM_QUEUES + MAX_NUM_LL2_RX_CTX_QUEUES)
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+
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+#define MAX_NUM_LL2_TX_STATS_COUNTERS  48
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 #define FW_MAJOR_VERSION	8
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-#define FW_MINOR_VERSION        37
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-#define FW_REVISION_VERSION     2
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+#define FW_MINOR_VERSION	42
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+#define FW_REVISION_VERSION	2
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 #define FW_ENGINEERING_VERSION	0
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95
 
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 /***********************/
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..
@@ -132,10 +112,10 @@
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 #define MAX_NUM_VFS	(MAX_NUM_VFS_K2)
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 #define MAX_NUM_FUNCTIONS_BB	(MAX_NUM_PFS_BB + MAX_NUM_VFS_BB)
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-#define MAX_NUM_FUNCTIONS	(MAX_NUM_PFS + MAX_NUM_VFS)
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 #define MAX_FUNCTION_NUMBER_BB	(MAX_NUM_PFS + MAX_NUM_VFS_BB)
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-#define MAX_FUNCTION_NUMBER	(MAX_NUM_PFS + MAX_NUM_VFS)
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+#define MAX_FUNCTION_NUMBER_K2  (MAX_NUM_PFS + MAX_NUM_VFS_K2)
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+#define MAX_NUM_FUNCTIONS	(MAX_FUNCTION_NUMBER_K2)
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 #define MAX_NUM_VPORTS_K2	(208)
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 #define MAX_NUM_VPORTS_BB	(160)
..
..
@@ -222,6 +202,7 @@
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 #define DQ_XCM_TOE_TX_BD_PROD_CMD		DQ_XCM_AGG_VAL_SEL_WORD4
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 #define DQ_XCM_TOE_MORE_TO_SEND_SEQ_CMD		DQ_XCM_AGG_VAL_SEL_REG3
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 #define DQ_XCM_TOE_LOCAL_ADV_WND_SEQ_CMD	DQ_XCM_AGG_VAL_SEL_REG4
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+#define DQ_XCM_ROCE_ACK_EDPM_DORQ_SEQ_CMD	DQ_XCM_AGG_VAL_SEL_WORD5
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 /* UCM agg val selection (HW) */
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 #define	DQ_UCM_AGG_VAL_SEL_WORD0	0
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@@ -340,6 +321,10 @@
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 #define DQ_PWM_OFFSET_TCM_ROCE_RQ_PROD		(DQ_PWM_OFFSET_TCM16_BASE + 1)
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 #define DQ_PWM_OFFSET_TCM_IWARP_RQ_PROD		(DQ_PWM_OFFSET_TCM16_BASE + 3)
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323
 
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+/* DQ_DEMS_AGG_VAL_BASE */
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+#define DQ_PWM_OFFSET_TCM_LL2_PROD_UPDATE \
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+	(DQ_PWM_OFFSET_TCM32_BASE + DQ_TCM_AGG_VAL_SEL_REG9 - 4)
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+
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 #define	DQ_REGION_SHIFT			(12)
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 /* DPM */
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@@ -395,6 +380,7 @@
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 /* Number of Protocol Indices per Status Block */
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 #define PIS_PER_SB_E4	12
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+#define MAX_PIS_PER_SB	PIS_PER_SB
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 #define CAU_HC_STOPPED_STATE	3
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 #define CAU_HC_DISABLE_STATE	4
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@@ -425,8 +411,6 @@
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 #define IGU_MEM_PBA_MSIX_RESERVED_UPPER	0x03ff
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 #define IGU_CMD_INT_ACK_BASE		0x0400
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-#define IGU_CMD_INT_ACK_UPPER		(IGU_CMD_INT_ACK_BASE +	\
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-					 MAX_TOT_SB_PER_PATH - 1)
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 #define IGU_CMD_INT_ACK_RESERVED_UPPER	0x05ff
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 #define IGU_CMD_ATTN_BIT_UPD_UPPER	0x05f0
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@@ -439,8 +423,6 @@
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 #define IGU_REG_SISR_MDPC_WOMASK_UPPER		0x05f6
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 #define IGU_CMD_PROD_UPD_BASE			0x0600
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-#define IGU_CMD_PROD_UPD_UPPER			(IGU_CMD_PROD_UPD_BASE +\
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-						 MAX_TOT_SB_PER_PATH - 1)
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 #define IGU_CMD_PROD_UPD_RESERVED_UPPER		0x07ff
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 /*****************/
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@@ -652,8 +634,8 @@
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 #define PBF_MAX_CMD_LINES	3328
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635
 
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 /* Number of BTB blocks. Each block is 256B. */
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-#define BTB_MAX_BLOCKS		1440
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-
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+#define BTB_MAX_BLOCKS_BB 1440
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+#define BTB_MAX_BLOCKS_K2 1840
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 /*****************/
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 /* PRS CONSTANTS */
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 /*****************/
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@@ -730,6 +712,8 @@
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 	PROTOCOLID_PREROCE,
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 	PROTOCOLID_COMMON,
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 	PROTOCOLID_RESERVED1,
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+	PROTOCOLID_RDMA,
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+	PROTOCOLID_SCSI,
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 	MAX_PROTOCOL_TYPE
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 };
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@@ -748,6 +732,10 @@
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 union rdma_eqe_data {
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 	struct regpair async_handle;
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 	struct rdma_eqe_destroy_qp rdma_destroy_qp_data;
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+};
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+
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+struct tstorm_queue_zone {
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+	__le32 reserved[2];
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 };
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 /* Ustorm Queue Zone */
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@@ -872,8 +860,8 @@
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 #define DB_L2_DPM_DATA_RESERVED0_SHIFT 27
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 #define DB_L2_DPM_DATA_SGE_NUM_MASK	0x7
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 #define DB_L2_DPM_DATA_SGE_NUM_SHIFT	28
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-#define DB_L2_DPM_DATA_GFS_SRC_EN_MASK	0x1
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-#define DB_L2_DPM_DATA_GFS_SRC_EN_SHIFT	31
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+#define DB_L2_DPM_DATA_TGFS_SRC_EN_MASK  0x1
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+#define DB_L2_DPM_DATA_TGFS_SRC_EN_SHIFT 31
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 };
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 /* Structure for SGE in a DPM doorbell of type DPM_L2_BD */
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@@ -931,12 +919,12 @@
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 #define DB_RDMA_DPM_PARAMS_WQE_SIZE_SHIFT		16
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 #define DB_RDMA_DPM_PARAMS_RESERVED0_MASK		0x1
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 #define DB_RDMA_DPM_PARAMS_RESERVED0_SHIFT		27
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-#define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_MASK		0x1
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-#define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_SHIFT		28
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+#define DB_RDMA_DPM_PARAMS_ACK_REQUEST_MASK		0x1
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+#define DB_RDMA_DPM_PARAMS_ACK_REQUEST_SHIFT		28
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 #define DB_RDMA_DPM_PARAMS_S_FLG_MASK			0x1
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 #define DB_RDMA_DPM_PARAMS_S_FLG_SHIFT			29
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-#define DB_RDMA_DPM_PARAMS_RESERVED1_MASK		0x1
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-#define DB_RDMA_DPM_PARAMS_RESERVED1_SHIFT		30
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+#define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_MASK		0x1
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+#define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_SHIFT		30
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 #define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_MASK	0x1
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 #define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_SHIFT	31
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 };