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2024-05-10 23fa18eaa71266feff7ba8d83022d9e1cc83c65a 
 kernel/include/linux/clk-provider.h
....@@ -1,22 +1,13 @@
1
+/* SPDX-License-Identifier: GPL-2.0 */
12 /*
2
- *  linux/include/linux/clk-provider.h
3
- *
43  *  Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
54  *  Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
6
- *
7
- * This program is free software; you can redistribute it and/or modify
8
- * it under the terms of the GNU General Public License version 2 as
9
- * published by the Free Software Foundation.
105  */
116 #ifndef __LINUX_CLK_PROVIDER_H
127 #define __LINUX_CLK_PROVIDER_H
138 
14
-#include <linux/io.h>
159 #include <linux/of.h>
1610 #include <linux/of_clk.h>
17
-#include <linux/mutex.h>
18
-
19
-#ifdef CONFIG_COMMON_CLK
2011 
2112 /*
2213  * flags used across common struct clk.  these flags should only affect the
....@@ -30,7 +21,7 @@
3021 #define CLK_SET_RATE_PARENT	BIT(2) /* propagate rate change up one level */
3122 #define CLK_IGNORE_UNUSED	BIT(3) /* do not gate even if unused */
3223 				/* unused */
33
-#define CLK_IS_BASIC		BIT(5) /* Basic clk, can't do a to_clk_foo() */
24
+				/* unused */
3425 #define CLK_GET_RATE_NOCACHE	BIT(6) /* do not use the cached clk rate */
3526 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
3627 #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
....@@ -42,13 +33,6 @@
4233 /* duty cycle call may be forwarded to the parent clock */
4334 #define CLK_DUTY_CYCLE_PARENT	BIT(13)
4435 #define CLK_DONT_HOLD_STATE	BIT(14) /* Don't hold state */
45
-#define CLK_ENABLE_HAND_OFF	BIT(15) /* enable clock when registered. */
46
-					/*
47
-					 * hand-off enable_count & prepare_count
48
-					 * to first consumer that enables clk
49
-					 */
50
-#define CLK_IS_MEASURE          BIT(16) /* measure clock */
51
-#define CLK_KEEP_REQ_RATE	BIT(17) /* keep reqrate on parent rate change */
5236 
5337 struct clk;
5438 struct clk_hw;
....@@ -128,6 +112,11 @@
128112  *		Called with enable_lock held.  This function must not
129113  *		sleep.
130114  *
115
+ * @save_context: Save the context of the clock in prepration for poweroff.
116
+ *
117
+ * @restore_context: Restore the context of the clock after a restoration
118
+ *		of power.
119
+ *
131120  * @recalc_rate	Recalculate the rate of this clock, by querying hardware. The
132121  *		parent rate is an input parameter.  It is up to the caller to
133122  *		ensure that the prepare_mutex is held across this call.
....@@ -201,9 +190,15 @@
201190  *              and >= numerator) Return 0 on success, otherwise -EERROR.
202191  *
203192  * @init:	Perform platform-specific initialization magic.
204
- *		This is not not used by any of the basic clock types.
205
- *		Please consider other ways of solving initialization problems
206
- *		before using this callback, as its use is discouraged.
193
+ *		This is not used by any of the basic clock types.
194
+ *		This callback exist for HW which needs to perform some
195
+ *		initialisation magic for CCF to get an accurate view of the
196
+ *		clock. It may also be used dynamic resource allocation is
197
+ *		required. It shall not used to deal with clock parameters,
198
+ *		such as rate or parents.
199
+ *		Returns 0 on success, -EERROR otherwise.
200
+ *
201
+ * @terminate:  Free any resource allocated by init.
207202  *
208203  * @debug_init:	Set up type-specific debugfs entries for this clock.  This
209204  *		is called once, after the debugfs directory entry for this
....@@ -211,18 +206,13 @@
211206  *		directory is provided as an argument.  Called with
212207  *		prepare_lock held.  Returns 0 on success, -EERROR otherwise.
213208  *
214
- * @set_flags: Set custom flags which deal with hardware specifics. Returns 0
215
- *	       on success, -EERROR otherwise.
209
+ * @pre_rate_change: Optional callback for a clock to fulfill its rate
210
+ *		change requirements before any rate change has occurred in
211
+ *		its clock tree. Returns 0 on success, -EERROR otherwise.
216212  *
217
- * @list_registers: Queries the hardware to get the current register contents.
218
- *		    This callback is optional.
219
- *
220
- * @list_rate:  On success, return the nth supported frequency for a given
221
- *		clock that is below rate_max. Return -ENXIO in case there is
222
- *		no frequency table.
223
- *
224
- * @bus_vote:	Votes for bandwidth on certain config slaves to connect
225
- *		ports in order to gain access to clock controllers.
213
+ * @post_rate_change: Optional callback for a clock to clean up any
214
+ *		requirements that were needed while the clock and its tree
215
+ *		was changing states. Returns 0 on success, -EERROR otherwise.
226216  *
227217  * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
228218  * implementations to split any work between atomic (enable) and sleepable
....@@ -244,6 +234,8 @@
244234 	void		(*disable)(struct clk_hw *hw);
245235 	int		(*is_enabled)(struct clk_hw *hw);
246236 	void		(*disable_unused)(struct clk_hw *hw);
237
+	int		(*save_context)(struct clk_hw *hw);
238
+	void		(*restore_context)(struct clk_hw *hw);
247239 	unsigned long	(*recalc_rate)(struct clk_hw *hw,
248240 					unsigned long parent_rate);
249241 	long		(*round_rate)(struct clk_hw *hw, unsigned long rate,
....@@ -265,14 +257,29 @@
265257 					  struct clk_duty *duty);
266258 	int		(*set_duty_cycle)(struct clk_hw *hw,
267259 					  struct clk_duty *duty);
268
-	void		(*init)(struct clk_hw *hw);
260
+	int		(*init)(struct clk_hw *hw);
261
+	void		(*terminate)(struct clk_hw *hw);
269262 	void		(*debug_init)(struct clk_hw *hw, struct dentry *dentry);
270
-	int		(*set_flags)(struct clk_hw *hw, unsigned int flags);
271
-	void		(*list_registers)(struct seq_file *f,
272
-							struct clk_hw *hw);
273
-	long		(*list_rate)(struct clk_hw *hw, unsigned int n,
274
-							unsigned long rate_max);
275
-	void		(*bus_vote)(struct clk_hw *hw, bool enable);
263
+	int		(*pre_rate_change)(struct clk_hw *hw,
264
+					   unsigned long rate,
265
+					   unsigned long new_rate);
266
+	int		(*post_rate_change)(struct clk_hw *hw,
267
+					    unsigned long old_rate,
268
+					    unsigned long rate);
269
+};
270
+
271
+/**
272
+ * struct clk_parent_data - clk parent information
273
+ * @hw: parent clk_hw pointer (used for clk providers with internal clks)
274
+ * @fw_name: parent name local to provider registering clk
275
+ * @name: globally unique parent name (used as a fallback)
276
+ * @index: parent index local to provider registering clk (if @fw_name absent)
277
+ */
278
+struct clk_parent_data {
279
+	const struct clk_hw	*hw;
280
+	const char		*fw_name;
281
+	const char		*name;
282
+	int			index;
276283 };
277284 
278285 /**
....@@ -282,87 +289,23 @@
282289  * @name: clock name
283290  * @ops: operations this clock supports
284291  * @parent_names: array of string names for all possible parents
292
+ * @parent_data: array of parent data for all possible parents (when some
293
+ *               parents are external to the clk controller)
294
+ * @parent_hws: array of pointers to all possible parents (when all parents
295
+ *              are internal to the clk controller)
285296  * @num_parents: number of possible parents
286297  * @flags: framework-level hints and quirks
287
- * @vdd_class: voltage scaling requirement class
288
- * @rate_max: maximum clock rate in Hz supported at each voltage level
289
- * @num_rate_max: number of maximum voltage level supported
290
- * @bus_cl_id: client id registered with the bus driver used for bw votes
291298  */
292299 struct clk_init_data {
293300 	const char		*name;
294301 	const struct clk_ops	*ops;
302
+	/* Only one of the following three should be assigned */
295303 	const char		* const *parent_names;
296
-	unsigned int		num_parents;
304
+	const struct clk_parent_data	*parent_data;
305
+	const struct clk_hw		**parent_hws;
306
+	u8			num_parents;
297307 	unsigned long		flags;
298
-	struct clk_vdd_class	*vdd_class;
299
-	unsigned long		*rate_max;
300
-	int			num_rate_max;
301
-	unsigned int		bus_cl_id;
302308 };
303
-
304
-struct regulator;
305
-
306
-/**
307
- * struct clk_vdd_class - Voltage scaling class
308
- * @class_name: name of the class
309
- * @regulator: array of regulators
310
- * @num_regulators: size of regulator array. Standard regulator APIs will be
311
-			used if this field > 0
312
- * @set_vdd: function to call when applying a new voltage setting
313
- * @vdd_uv: sorted 2D array of legal voltage settings. Indexed by level, then
314
-		regulator
315
- * @level_votes: array of votes for each level
316
- * @num_levels: specifies the size of level_votes array
317
- * @skip_handoff: do not vote for the max possible voltage during init
318
- * @cur_level: the currently set voltage level
319
- * @lock: lock to protect this struct
320
- */
321
-struct clk_vdd_class {
322
-	const char *class_name;
323
-	struct regulator **regulator;
324
-	int num_regulators;
325
-	int (*set_vdd)(struct clk_vdd_class *v_class, int level);
326
-	int *vdd_uv;
327
-	int *level_votes;
328
-	int num_levels;
329
-	bool skip_handoff;
330
-	unsigned long cur_level;
331
-	struct mutex lock;
332
-};
333
-
334
-#define DEFINE_VDD_CLASS(_name, _set_vdd, _num_levels) \
335
-	struct clk_vdd_class _name = { \
336
-		.class_name = #_name, \
337
-		.set_vdd = _set_vdd, \
338
-		.level_votes = (int [_num_levels]) {}, \
339
-		.num_levels = _num_levels, \
340
-		.cur_level = _num_levels, \
341
-		.lock = __MUTEX_INITIALIZER(_name.lock) \
342
-	}
343
-
344
-#define DEFINE_VDD_REGULATORS(_name, _num_levels, _num_regulators, _vdd_uv) \
345
-	struct clk_vdd_class _name = { \
346
-		.class_name = #_name, \
347
-		.vdd_uv = _vdd_uv, \
348
-		.regulator = (struct regulator * [_num_regulators]) {}, \
349
-		.num_regulators = _num_regulators, \
350
-		.level_votes = (int [_num_levels]) {}, \
351
-		.num_levels = _num_levels, \
352
-		.cur_level = _num_levels, \
353
-		.lock = __MUTEX_INITIALIZER(_name.lock) \
354
-	}
355
-
356
-#define DEFINE_VDD_REGS_INIT(_name, _num_regulators) \
357
-	struct clk_vdd_class _name = { \
358
-		.class_name = #_name, \
359
-		.regulator = (struct regulator * [_num_regulators]) {}, \
360
-		.num_regulators = _num_regulators, \
361
-		.lock = __MUTEX_INITIALIZER(_name.lock) \
362
-	}
363
-
364
-int clk_vote_vdd_level(struct clk_vdd_class *vdd_class, int level);
365
-int clk_unvote_vdd_level(struct clk_vdd_class *vdd_class, int level);
366309 
367310 /**
368311  * struct clk_hw - handle for traversing from a struct clk to its corresponding
....@@ -377,7 +320,8 @@
377320  * into the clk API
378321  *
379322  * @init: pointer to struct clk_init_data that contains the init data shared
380
- * with the common clock framework.
323
+ * with the common clock framework. This pointer will be set to NULL once
324
+ * a clk_register() variant is called on this clk_hw pointer.
381325  */
382326 struct clk_hw {
383327 	struct clk_core *core;
....@@ -398,30 +342,119 @@
398342  * struct clk_fixed_rate - fixed-rate clock
399343  * @hw:		handle between common and hardware-specific interfaces
400344  * @fixed_rate:	constant frequency of clock
345
+ * @fixed_accuracy: constant accuracy of clock in ppb (parts per billion)
346
+ * @flags:	hardware specific flags
347
+ *
348
+ * Flags:
349
+ * * CLK_FIXED_RATE_PARENT_ACCURACY - Use the accuracy of the parent clk
350
+ *                                    instead of what's set in @fixed_accuracy.
401351  */
402352 struct clk_fixed_rate {
403353 	struct		clk_hw hw;
404354 	unsigned long	fixed_rate;
405355 	unsigned long	fixed_accuracy;
406
-	u8		flags;
356
+	unsigned long	flags;
407357 };
408358 
409
-#define to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate, hw)
359
+#define CLK_FIXED_RATE_PARENT_ACCURACY		BIT(0)
410360 
411361 extern const struct clk_ops clk_fixed_rate_ops;
362
+struct clk_hw *__clk_hw_register_fixed_rate(struct device *dev,
363
+		struct device_node *np, const char *name,
364
+		const char *parent_name, const struct clk_hw *parent_hw,
365
+		const struct clk_parent_data *parent_data, unsigned long flags,
366
+		unsigned long fixed_rate, unsigned long fixed_accuracy,
367
+		unsigned long clk_fixed_flags);
412368 struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
413369 		const char *parent_name, unsigned long flags,
414370 		unsigned long fixed_rate);
415
-struct clk_hw *clk_hw_register_fixed_rate(struct device *dev, const char *name,
416
-		const char *parent_name, unsigned long flags,
417
-		unsigned long fixed_rate);
418
-struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev,
419
-		const char *name, const char *parent_name, unsigned long flags,
420
-		unsigned long fixed_rate, unsigned long fixed_accuracy);
371
+/**
372
+ * clk_hw_register_fixed_rate - register fixed-rate clock with the clock
373
+ * framework
374
+ * @dev: device that is registering this clock
375
+ * @name: name of this clock
376
+ * @parent_name: name of clock's parent
377
+ * @flags: framework-specific flags
378
+ * @fixed_rate: non-adjustable clock rate
379
+ */
380
+#define clk_hw_register_fixed_rate(dev, name, parent_name, flags, fixed_rate)  \
381
+	__clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), NULL, \
382
+				     NULL, (flags), (fixed_rate), 0, 0)
383
+/**
384
+ * clk_hw_register_fixed_rate_parent_hw - register fixed-rate clock with
385
+ * the clock framework
386
+ * @dev: device that is registering this clock
387
+ * @name: name of this clock
388
+ * @parent_hw: pointer to parent clk
389
+ * @flags: framework-specific flags
390
+ * @fixed_rate: non-adjustable clock rate
391
+ */
392
+#define clk_hw_register_fixed_rate_parent_hw(dev, name, parent_hw, flags,     \
393
+					     fixed_rate)		      \
394
+	__clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw),  \
395
+				     NULL, (flags), (fixed_rate), 0, 0)
396
+/**
397
+ * clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with
398
+ * the clock framework
399
+ * @dev: device that is registering this clock
400
+ * @name: name of this clock
401
+ * @parent_data: parent clk data
402
+ * @flags: framework-specific flags
403
+ * @fixed_rate: non-adjustable clock rate
404
+ */
405
+#define clk_hw_register_fixed_rate_parent_data(dev, name, parent_hw, flags,   \
406
+					     fixed_rate)		      \
407
+	__clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL,	      \
408
+				     (parent_data), (flags), (fixed_rate), 0, \
409
+				     0)
410
+/**
411
+ * clk_hw_register_fixed_rate_with_accuracy - register fixed-rate clock with
412
+ * the clock framework
413
+ * @dev: device that is registering this clock
414
+ * @name: name of this clock
415
+ * @parent_name: name of clock's parent
416
+ * @flags: framework-specific flags
417
+ * @fixed_rate: non-adjustable clock rate
418
+ * @fixed_accuracy: non-adjustable clock accuracy
419
+ */
420
+#define clk_hw_register_fixed_rate_with_accuracy(dev, name, parent_name,      \
421
+						 flags, fixed_rate,	      \
422
+						 fixed_accuracy)	      \
423
+	__clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name),      \
424
+				     NULL, NULL, (flags), (fixed_rate),       \
425
+				     (fixed_accuracy), 0)
426
+/**
427
+ * clk_hw_register_fixed_rate_with_accuracy_parent_hw - register fixed-rate
428
+ * clock with the clock framework
429
+ * @dev: device that is registering this clock
430
+ * @name: name of this clock
431
+ * @parent_hw: pointer to parent clk
432
+ * @flags: framework-specific flags
433
+ * @fixed_rate: non-adjustable clock rate
434
+ * @fixed_accuracy: non-adjustable clock accuracy
435
+ */
436
+#define clk_hw_register_fixed_rate_with_accuracy_parent_hw(dev, name,	      \
437
+		parent_hw, flags, fixed_rate, fixed_accuracy)		      \
438
+	__clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw)   \
439
+				     NULL, NULL, (flags), (fixed_rate),	      \
440
+				     (fixed_accuracy), 0)
441
+/**
442
+ * clk_hw_register_fixed_rate_with_accuracy_parent_data - register fixed-rate
443
+ * clock with the clock framework
444
+ * @dev: device that is registering this clock
445
+ * @name: name of this clock
446
+ * @parent_name: name of clock's parent
447
+ * @flags: framework-specific flags
448
+ * @fixed_rate: non-adjustable clock rate
449
+ * @fixed_accuracy: non-adjustable clock accuracy
450
+ */
451
+#define clk_hw_register_fixed_rate_with_accuracy_parent_data(dev, name,	      \
452
+		parent_data, flags, fixed_rate, fixed_accuracy)		      \
453
+	__clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL,	      \
454
+				     (parent_data), NULL, (flags),	      \
455
+				     (fixed_rate), (fixed_accuracy), 0)
456
+
421457 void clk_unregister_fixed_rate(struct clk *clk);
422
-struct clk_hw *clk_hw_register_fixed_rate_with_accuracy(struct device *dev,
423
-		const char *name, const char *parent_name, unsigned long flags,
424
-		unsigned long fixed_rate, unsigned long fixed_accuracy);
425458 void clk_hw_unregister_fixed_rate(struct clk_hw *hw);
426459 
427460 void of_fixed_clk_setup(struct device_node *np);
....@@ -445,8 +478,9 @@
445478  *	of this register, and mask of gate bits are in higher 16-bit of this
446479  *	register.  While setting the gate bits, higher 16-bit should also be
447480  *	updated to indicate changing gate bits.
448
- * CLK_GATE_NO_SET_RATE - The Gate not allowed to set rate.
449
- *	And not allowed to set parent rate.
481
+ * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for
482
+ *	the gate register.  Setting this flag makes the register accesses big
483
+ *	endian.
450484  */
451485 struct clk_gate {
452486 	struct clk_hw hw;
....@@ -460,17 +494,70 @@
460494 
461495 #define CLK_GATE_SET_TO_DISABLE		BIT(0)
462496 #define CLK_GATE_HIWORD_MASK		BIT(1)
463
-#define CLK_GATE_NO_SET_RATE		BIT(3)
497
+#define CLK_GATE_BIG_ENDIAN		BIT(2)
464498 
465499 extern const struct clk_ops clk_gate_ops;
500
+struct clk_hw *__clk_hw_register_gate(struct device *dev,
501
+		struct device_node *np, const char *name,
502
+		const char *parent_name, const struct clk_hw *parent_hw,
503
+		const struct clk_parent_data *parent_data,
504
+		unsigned long flags,
505
+		void __iomem *reg, u8 bit_idx,
506
+		u8 clk_gate_flags, spinlock_t *lock);
466507 struct clk *clk_register_gate(struct device *dev, const char *name,
467508 		const char *parent_name, unsigned long flags,
468509 		void __iomem *reg, u8 bit_idx,
469510 		u8 clk_gate_flags, spinlock_t *lock);
470
-struct clk_hw *clk_hw_register_gate(struct device *dev, const char *name,
471
-		const char *parent_name, unsigned long flags,
472
-		void __iomem *reg, u8 bit_idx,
473
-		u8 clk_gate_flags, spinlock_t *lock);
511
+/**
512
+ * clk_hw_register_gate - register a gate clock with the clock framework
513
+ * @dev: device that is registering this clock
514
+ * @name: name of this clock
515
+ * @parent_name: name of this clock's parent
516
+ * @flags: framework-specific flags for this clock
517
+ * @reg: register address to control gating of this clock
518
+ * @bit_idx: which bit in the register controls gating of this clock
519
+ * @clk_gate_flags: gate-specific flags for this clock
520
+ * @lock: shared register lock for this clock
521
+ */
522
+#define clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx,     \
523
+			     clk_gate_flags, lock)			      \
524
+	__clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL,      \
525
+			       NULL, (flags), (reg), (bit_idx),		      \
526
+			       (clk_gate_flags), (lock))
527
+/**
528
+ * clk_hw_register_gate_parent_hw - register a gate clock with the clock
529
+ * framework
530
+ * @dev: device that is registering this clock
531
+ * @name: name of this clock
532
+ * @parent_hw: pointer to parent clk
533
+ * @flags: framework-specific flags for this clock
534
+ * @reg: register address to control gating of this clock
535
+ * @bit_idx: which bit in the register controls gating of this clock
536
+ * @clk_gate_flags: gate-specific flags for this clock
537
+ * @lock: shared register lock for this clock
538
+ */
539
+#define clk_hw_register_gate_parent_hw(dev, name, parent_hw, flags, reg,      \
540
+				       bit_idx, clk_gate_flags, lock)	      \
541
+	__clk_hw_register_gate((dev), NULL, (name), NULL, (parent_hw),        \
542
+			       NULL, (flags), (reg), (bit_idx),		      \
543
+			       (clk_gate_flags), (lock))
544
+/**
545
+ * clk_hw_register_gate_parent_data - register a gate clock with the clock
546
+ * framework
547
+ * @dev: device that is registering this clock
548
+ * @name: name of this clock
549
+ * @parent_data: parent clk data
550
+ * @flags: framework-specific flags for this clock
551
+ * @reg: register address to control gating of this clock
552
+ * @bit_idx: which bit in the register controls gating of this clock
553
+ * @clk_gate_flags: gate-specific flags for this clock
554
+ * @lock: shared register lock for this clock
555
+ */
556
+#define clk_hw_register_gate_parent_data(dev, name, parent_data, flags, reg,  \
557
+				       bit_idx, clk_gate_flags, lock)	      \
558
+	__clk_hw_register_gate((dev), NULL, (name), NULL, NULL, (parent_data), \
559
+			       (flags), (reg), (bit_idx),		      \
560
+			       (clk_gate_flags), (lock))
474561 void clk_unregister_gate(struct clk *clk);
475562 void clk_hw_unregister_gate(struct clk_hw *hw);
476563 int clk_gate_is_enabled(struct clk_hw *hw);
....@@ -487,7 +574,6 @@
487574  * @reg:	register containing the divider
488575  * @shift:	shift to the divider bit field
489576  * @width:	width of the divider bit field
490
- * @max_prate:	the maximum frequency of the parent clock
491577  * @table:	array of value/divider pairs, last entry should have div = 0
492578  * @lock:	register lock
493579  *
....@@ -517,6 +603,9 @@
517603  * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
518604  *	except when the value read from the register is zero, the divisor is
519605  *	2^width of the field.
606
+ * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used
607
+ *	for the divider register.  Setting this flag makes the register accesses
608
+ *	big endian.
520609  */
521610 struct clk_divider {
522611 	struct clk_hw	hw;
....@@ -524,7 +613,6 @@
524613 	u8		shift;
525614 	u8		width;
526615 	u8		flags;
527
-	unsigned long	max_prate;
528616 	const struct clk_div_table	*table;
529617 	spinlock_t	*lock;
530618 };
....@@ -539,6 +627,7 @@
539627 #define CLK_DIVIDER_ROUND_CLOSEST	BIT(4)
540628 #define CLK_DIVIDER_READ_ONLY		BIT(5)
541629 #define CLK_DIVIDER_MAX_AT_ZERO		BIT(6)
630
+#define CLK_DIVIDER_BIG_ENDIAN		BIT(7)
542631 
543632 extern const struct clk_ops clk_divider_ops;
544633 extern const struct clk_ops clk_divider_ro_ops;
....@@ -558,24 +647,153 @@
558647 		const struct clk_div_table *table, u8 width,
559648 		unsigned long flags);
560649 
561
-struct clk *clk_register_divider(struct device *dev, const char *name,
562
-		const char *parent_name, unsigned long flags,
563
-		void __iomem *reg, u8 shift, u8 width,
564
-		u8 clk_divider_flags, spinlock_t *lock);
565
-struct clk_hw *clk_hw_register_divider(struct device *dev, const char *name,
566
-		const char *parent_name, unsigned long flags,
567
-		void __iomem *reg, u8 shift, u8 width,
568
-		u8 clk_divider_flags, spinlock_t *lock);
650
+struct clk_hw *__clk_hw_register_divider(struct device *dev,
651
+		struct device_node *np, const char *name,
652
+		const char *parent_name, const struct clk_hw *parent_hw,
653
+		const struct clk_parent_data *parent_data, unsigned long flags,
654
+		void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,
655
+		const struct clk_div_table *table, spinlock_t *lock);
569656 struct clk *clk_register_divider_table(struct device *dev, const char *name,
570657 		const char *parent_name, unsigned long flags,
571658 		void __iomem *reg, u8 shift, u8 width,
572659 		u8 clk_divider_flags, const struct clk_div_table *table,
573660 		spinlock_t *lock);
574
-struct clk_hw *clk_hw_register_divider_table(struct device *dev,
575
-		const char *name, const char *parent_name, unsigned long flags,
576
-		void __iomem *reg, u8 shift, u8 width,
577
-		u8 clk_divider_flags, const struct clk_div_table *table,
578
-		spinlock_t *lock);
661
+/**
662
+ * clk_register_divider - register a divider clock with the clock framework
663
+ * @dev: device registering this clock
664
+ * @name: name of this clock
665
+ * @parent_name: name of clock's parent
666
+ * @flags: framework-specific flags
667
+ * @reg: register address to adjust divider
668
+ * @shift: number of bits to shift the bitfield
669
+ * @width: width of the bitfield
670
+ * @clk_divider_flags: divider-specific flags for this clock
671
+ * @lock: shared register lock for this clock
672
+ */
673
+#define clk_register_divider(dev, name, parent_name, flags, reg, shift, width, \
674
+			     clk_divider_flags, lock)			       \
675
+	clk_register_divider_table((dev), (name), (parent_name), (flags),      \
676
+				   (reg), (shift), (width),		       \
677
+				   (clk_divider_flags), NULL, (lock))
678
+/**
679
+ * clk_hw_register_divider - register a divider clock with the clock framework
680
+ * @dev: device registering this clock
681
+ * @name: name of this clock
682
+ * @parent_name: name of clock's parent
683
+ * @flags: framework-specific flags
684
+ * @reg: register address to adjust divider
685
+ * @shift: number of bits to shift the bitfield
686
+ * @width: width of the bitfield
687
+ * @clk_divider_flags: divider-specific flags for this clock
688
+ * @lock: shared register lock for this clock
689
+ */
690
+#define clk_hw_register_divider(dev, name, parent_name, flags, reg, shift,    \
691
+				width, clk_divider_flags, lock)		      \
692
+	__clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL,   \
693
+				  NULL, (flags), (reg), (shift), (width),     \
694
+				  (clk_divider_flags), NULL, (lock))
695
+/**
696
+ * clk_hw_register_divider_parent_hw - register a divider clock with the clock
697
+ * framework
698
+ * @dev: device registering this clock
699
+ * @name: name of this clock
700
+ * @parent_hw: pointer to parent clk
701
+ * @flags: framework-specific flags
702
+ * @reg: register address to adjust divider
703
+ * @shift: number of bits to shift the bitfield
704
+ * @width: width of the bitfield
705
+ * @clk_divider_flags: divider-specific flags for this clock
706
+ * @lock: shared register lock for this clock
707
+ */
708
+#define clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags, reg,   \
709
+					  shift, width, clk_divider_flags,    \
710
+					  lock)				      \
711
+	__clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw),     \
712
+				  NULL, (flags), (reg), (shift), (width),     \
713
+				  (clk_divider_flags), NULL, (lock))
714
+/**
715
+ * clk_hw_register_divider_parent_data - register a divider clock with the clock
716
+ * framework
717
+ * @dev: device registering this clock
718
+ * @name: name of this clock
719
+ * @parent_data: parent clk data
720
+ * @flags: framework-specific flags
721
+ * @reg: register address to adjust divider
722
+ * @shift: number of bits to shift the bitfield
723
+ * @width: width of the bitfield
724
+ * @clk_divider_flags: divider-specific flags for this clock
725
+ * @lock: shared register lock for this clock
726
+ */
727
+#define clk_hw_register_divider_parent_data(dev, name, parent_data, flags,    \
728
+					    reg, shift, width,		      \
729
+					    clk_divider_flags, lock)	      \
730
+	__clk_hw_register_divider((dev), NULL, (name), NULL, NULL,	      \
731
+				  (parent_data), (flags), (reg), (shift),     \
732
+				  (width), (clk_divider_flags), NULL, (lock))
733
+/**
734
+ * clk_hw_register_divider_table - register a table based divider clock with
735
+ * the clock framework
736
+ * @dev: device registering this clock
737
+ * @name: name of this clock
738
+ * @parent_name: name of clock's parent
739
+ * @flags: framework-specific flags
740
+ * @reg: register address to adjust divider
741
+ * @shift: number of bits to shift the bitfield
742
+ * @width: width of the bitfield
743
+ * @clk_divider_flags: divider-specific flags for this clock
744
+ * @table: array of divider/value pairs ending with a div set to 0
745
+ * @lock: shared register lock for this clock
746
+ */
747
+#define clk_hw_register_divider_table(dev, name, parent_name, flags, reg,     \
748
+				      shift, width, clk_divider_flags, table, \
749
+				      lock)				      \
750
+	__clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL,   \
751
+				  NULL, (flags), (reg), (shift), (width),     \
752
+				  (clk_divider_flags), (table), (lock))
753
+/**
754
+ * clk_hw_register_divider_table_parent_hw - register a table based divider
755
+ * clock with the clock framework
756
+ * @dev: device registering this clock
757
+ * @name: name of this clock
758
+ * @parent_hw: pointer to parent clk
759
+ * @flags: framework-specific flags
760
+ * @reg: register address to adjust divider
761
+ * @shift: number of bits to shift the bitfield
762
+ * @width: width of the bitfield
763
+ * @clk_divider_flags: divider-specific flags for this clock
764
+ * @table: array of divider/value pairs ending with a div set to 0
765
+ * @lock: shared register lock for this clock
766
+ */
767
+#define clk_hw_register_divider_table_parent_hw(dev, name, parent_hw, flags,  \
768
+						reg, shift, width,	      \
769
+						clk_divider_flags, table,     \
770
+						lock)			      \
771
+	__clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw),     \
772
+				  NULL, (flags), (reg), (shift), (width),     \
773
+				  (clk_divider_flags), (table), (lock))
774
+/**
775
+ * clk_hw_register_divider_table_parent_data - register a table based divider
776
+ * clock with the clock framework
777
+ * @dev: device registering this clock
778
+ * @name: name of this clock
779
+ * @parent_data: parent clk data
780
+ * @flags: framework-specific flags
781
+ * @reg: register address to adjust divider
782
+ * @shift: number of bits to shift the bitfield
783
+ * @width: width of the bitfield
784
+ * @clk_divider_flags: divider-specific flags for this clock
785
+ * @table: array of divider/value pairs ending with a div set to 0
786
+ * @lock: shared register lock for this clock
787
+ */
788
+#define clk_hw_register_divider_table_parent_data(dev, name, parent_data,     \
789
+						  flags, reg, shift, width,   \
790
+						  clk_divider_flags, table,   \
791
+						  lock)			      \
792
+	__clk_hw_register_divider((dev), NULL, (name), NULL, NULL,	      \
793
+				  (parent_data), (flags), (reg), (shift),     \
794
+				  (width), (clk_divider_flags), (table),      \
795
+				  (lock))
796
+
579797 void clk_unregister_divider(struct clk *clk);
580798 void clk_hw_unregister_divider(struct clk_hw *hw);
581799 
....@@ -600,8 +818,13 @@
600818  *	register, and mask of mux bits are in higher 16-bit of this register.
601819  *	While setting the mux bits, higher 16-bit should also be updated to
602820  *	indicate changing mux bits.
821
+ * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the
822
+ * 	.get_parent clk_op.
603823  * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
604824  *	frequency.
825
+ * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for
826
+ *	the mux register.  Setting this flag makes the register accesses big
827
+ *	endian.
605828  */
606829 struct clk_mux {
607830 	struct clk_hw	hw;
....@@ -620,31 +843,52 @@
620843 #define CLK_MUX_HIWORD_MASK		BIT(2)
621844 #define CLK_MUX_READ_ONLY		BIT(3) /* mux can't be changed */
622845 #define CLK_MUX_ROUND_CLOSEST		BIT(4)
846
+#define CLK_MUX_BIG_ENDIAN		BIT(5)
623847 
624848 extern const struct clk_ops clk_mux_ops;
625849 extern const struct clk_ops clk_mux_ro_ops;
626850 
627
-struct clk *clk_register_mux(struct device *dev, const char *name,
628
-		const char * const *parent_names, u8 num_parents,
629
-		unsigned long flags,
630
-		void __iomem *reg, u8 shift, u8 width,
631
-		u8 clk_mux_flags, spinlock_t *lock);
632
-struct clk_hw *clk_hw_register_mux(struct device *dev, const char *name,
633
-		const char * const *parent_names, u8 num_parents,
634
-		unsigned long flags,
635
-		void __iomem *reg, u8 shift, u8 width,
636
-		u8 clk_mux_flags, spinlock_t *lock);
637
-
851
+struct clk_hw *__clk_hw_register_mux(struct device *dev, struct device_node *np,
852
+		const char *name, u8 num_parents,
853
+		const char * const *parent_names,
854
+		const struct clk_hw **parent_hws,
855
+		const struct clk_parent_data *parent_data,
856
+		unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
857
+		u8 clk_mux_flags, u32 *table, spinlock_t *lock);
638858 struct clk *clk_register_mux_table(struct device *dev, const char *name,
639859 		const char * const *parent_names, u8 num_parents,
640
-		unsigned long flags,
641
-		void __iomem *reg, u8 shift, u32 mask,
860
+		unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
642861 		u8 clk_mux_flags, u32 *table, spinlock_t *lock);
643
-struct clk_hw *clk_hw_register_mux_table(struct device *dev, const char *name,
644
-		const char * const *parent_names, u8 num_parents,
645
-		unsigned long flags,
646
-		void __iomem *reg, u8 shift, u32 mask,
647
-		u8 clk_mux_flags, u32 *table, spinlock_t *lock);
862
+
863
+#define clk_register_mux(dev, name, parent_names, num_parents, flags, reg,    \
864
+			 shift, width, clk_mux_flags, lock)		      \
865
+	clk_register_mux_table((dev), (name), (parent_names), (num_parents),  \
866
+			       (flags), (reg), (shift), BIT((width)) - 1,     \
867
+			       (clk_mux_flags), NULL, (lock))
868
+#define clk_hw_register_mux_table(dev, name, parent_names, num_parents,	      \
869
+				  flags, reg, shift, mask, clk_mux_flags,     \
870
+				  table, lock)				      \
871
+	__clk_hw_register_mux((dev), NULL, (name), (num_parents),	      \
872
+			      (parent_names), NULL, NULL, (flags), (reg),     \
873
+			      (shift), (mask), (clk_mux_flags), (table),      \
874
+			      (lock))
875
+#define clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \
876
+			    shift, width, clk_mux_flags, lock)		      \
877
+	__clk_hw_register_mux((dev), NULL, (name), (num_parents),	      \
878
+			      (parent_names), NULL, NULL, (flags), (reg),     \
879
+			      (shift), BIT((width)) - 1, (clk_mux_flags),     \
880
+			      NULL, (lock))
881
+#define clk_hw_register_mux_hws(dev, name, parent_hws, num_parents, flags,    \
882
+				reg, shift, width, clk_mux_flags, lock)	      \
883
+	__clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL,	      \
884
+			      (parent_hws), NULL, (flags), (reg), (shift),    \
885
+			      BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
886
+#define clk_hw_register_mux_parent_data(dev, name, parent_data, num_parents,  \
887
+					flags, reg, shift, width,	      \
888
+					clk_mux_flags, lock)		      \
889
+	__clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \
890
+			      (parent_data), (flags), (reg), (shift),	      \
891
+			      BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
648892 
649893 int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags,
650894 			 unsigned int val);
....@@ -694,12 +938,18 @@
694938  * @mwidth:	width of the numerator bit field
695939  * @nshift:	shift to the denominator bit field
696940  * @nwidth:	width of the denominator bit field
697
- * @max_parent:	the maximum frequency of fractional divider parent clock
698941  * @lock:	register lock
699942  *
700943  * Clock with adjustable fractional divider affecting its output frequency.
701944  *
702945  * Flags:
946
+ * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator
947
+ *	is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED
948
+ *	is set then the numerator and denominator are both the value read
949
+ *	plus one.
950
+ * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are
951
+ *	used for the divider register.  Setting this flag makes the register
952
+ *	accesses big endian.
703953  * CLK_FRAC_DIVIDER_NO_LIMIT - not need to follow the 20 times limit on
704954  *	fractional divider
705955  */
....@@ -713,7 +963,6 @@
713963 	u8		nwidth;
714964 	u32		nmask;
715965 	u8		flags;
716
-	unsigned long	max_prate;
717966 	void		(*approximation)(struct clk_hw *hw,
718967 				unsigned long rate, unsigned long *parent_rate,
719968 				unsigned long *m, unsigned long *n);
....@@ -722,6 +971,8 @@
722971 
723972 #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)
724973 
974
+#define CLK_FRAC_DIVIDER_ZERO_BASED		BIT(0)
975
+#define CLK_FRAC_DIVIDER_BIG_ENDIAN		BIT(1)
725976 #define CLK_FRAC_DIVIDER_NO_LIMIT		BIT(2)
726977 
727978 extern const struct clk_ops clk_fractional_divider_ops;
....@@ -755,6 +1006,9 @@
7551006  *	leaving the parent rate unmodified.
7561007  * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be
7571008  *	rounded to the closest integer instead of the down one.
1009
+ * CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are
1010
+ *	used for the multiplier register.  Setting this flag makes the register
1011
+ *	accesses big endian.
7581012  */
7591013 struct clk_multiplier {
7601014 	struct clk_hw	hw;
....@@ -769,6 +1023,7 @@
7691023 
7701024 #define CLK_MULTIPLIER_ZERO_BYPASS		BIT(0)
7711025 #define CLK_MULTIPLIER_ROUND_CLOSEST	BIT(1)
1026
+#define CLK_MULTIPLIER_BIG_ENDIAN		BIT(2)
7721027 
7731028 extern const struct clk_ops clk_multiplier_ops;
7741029 
....@@ -779,9 +1034,6 @@
7791034  * @mux_hw:	handle between composite and hardware-specific mux clock
7801035  * @rate_hw:	handle between composite and hardware-specific rate clock
7811036  * @gate_hw:	handle between composite and hardware-specific gate clock
782
- * @brother_hw: a member of clk_composite who has the common parent clocks
783
- *              with another clk_composite, and it's also a handle between
784
- *              common and hardware-specific interfaces
7851037  * @mux_ops:	clock ops for mux
7861038  * @rate_ops:	clock ops for rate
7871039  * @gate_ops:	clock ops for gate
....@@ -793,7 +1045,6 @@
7931045 	struct clk_hw	*mux_hw;
7941046 	struct clk_hw	*rate_hw;
7951047 	struct clk_hw	*gate_hw;
796
-	struct clk_hw	*brother_hw;
7971048 
7981049 	const struct clk_ops	*mux_ops;
7991050 	const struct clk_ops	*rate_ops;
....@@ -808,6 +1059,12 @@
8081059 		struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
8091060 		struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
8101061 		unsigned long flags);
1062
+struct clk *clk_register_composite_pdata(struct device *dev, const char *name,
1063
+		const struct clk_parent_data *parent_data, int num_parents,
1064
+		struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1065
+		struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1066
+		struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1067
+		unsigned long flags);
8111068 void clk_unregister_composite(struct clk *clk);
8121069 struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
8131070 		const char * const *parent_names, int num_parents,
....@@ -815,69 +1072,21 @@
8151072 		struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
8161073 		struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
8171074 		unsigned long flags);
1075
+struct clk_hw *clk_hw_register_composite_pdata(struct device *dev,
1076
+		const char *name,
1077
+		const struct clk_parent_data *parent_data, int num_parents,
1078
+		struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1079
+		struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1080
+		struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1081
+		unsigned long flags);
8181082 void clk_hw_unregister_composite(struct clk_hw *hw);
8191083 
820
-/***
821
- * struct clk_gpio_gate - gpio gated clock
822
- *
823
- * @hw:		handle between common and hardware-specific interfaces
824
- * @gpiod:	gpio descriptor
825
- *
826
- * Clock with a gpio control for enabling and disabling the parent clock.
827
- * Implements .enable, .disable and .is_enabled
828
- */
829
-
830
-struct clk_gpio {
831
-	struct clk_hw	hw;
832
-	struct gpio_desc *gpiod;
833
-};
834
-
835
-#define to_clk_gpio(_hw) container_of(_hw, struct clk_gpio, hw)
836
-
837
-extern const struct clk_ops clk_gpio_gate_ops;
838
-struct clk *clk_register_gpio_gate(struct device *dev, const char *name,
839
-		const char *parent_name, struct gpio_desc *gpiod,
840
-		unsigned long flags);
841
-struct clk_hw *clk_hw_register_gpio_gate(struct device *dev, const char *name,
842
-		const char *parent_name, struct gpio_desc *gpiod,
843
-		unsigned long flags);
844
-void clk_hw_unregister_gpio_gate(struct clk_hw *hw);
845
-
846
-/**
847
- * struct clk_gpio_mux - gpio controlled clock multiplexer
848
- *
849
- * @hw:		see struct clk_gpio
850
- * @gpiod:	gpio descriptor to select the parent of this clock multiplexer
851
- *
852
- * Clock with a gpio control for selecting the parent clock.
853
- * Implements .get_parent, .set_parent and .determine_rate
854
- */
855
-
856
-extern const struct clk_ops clk_gpio_mux_ops;
857
-struct clk *clk_register_gpio_mux(struct device *dev, const char *name,
858
-		const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod,
859
-		unsigned long flags);
860
-struct clk_hw *clk_hw_register_gpio_mux(struct device *dev, const char *name,
861
-		const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod,
862
-		unsigned long flags);
863
-void clk_hw_unregister_gpio_mux(struct clk_hw *hw);
864
-
865
-/**
866
- * clk_register - allocate a new clock, register it and return an opaque cookie
867
- * @dev: device that is registering this clock
868
- * @hw: link to hardware-specific clock data
869
- *
870
- * clk_register is the primary interface for populating the clock tree with new
871
- * clock nodes.  It returns a pointer to the newly allocated struct clk which
872
- * cannot be dereferenced by driver code but may be used in conjuction with the
873
- * rest of the clock API.  In the event of an error clk_register will return an
874
- * error code; drivers must test for an error code after calling clk_register.
875
- */
8761084 struct clk *clk_register(struct device *dev, struct clk_hw *hw);
8771085 struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw);
8781086 
8791087 int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw);
8801088 int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw);
1089
+int __must_check of_clk_hw_register(struct device_node *node, struct clk_hw *hw);
8811090 
8821091 void clk_unregister(struct clk *clk);
8831092 void devm_clk_unregister(struct device *dev, struct clk *clk);
....@@ -889,14 +1098,27 @@
8891098 /* helper functions */
8901099 const char *__clk_get_name(const struct clk *clk);
8911100 const char *clk_hw_get_name(const struct clk_hw *hw);
1101
+#ifdef CONFIG_COMMON_CLK
8921102 struct clk_hw *__clk_get_hw(struct clk *clk);
1103
+#else
1104
+static inline struct clk_hw *__clk_get_hw(struct clk *clk)
1105
+{
1106
+	return (struct clk_hw *)clk;
1107
+}
1108
+#endif
1109
+
1110
+struct clk *clk_hw_get_clk(struct clk_hw *hw, const char *con_id);
1111
+struct clk *devm_clk_hw_get_clk(struct device *dev, struct clk_hw *hw,
1112
+				const char *con_id);
1113
+
8931114 unsigned int clk_hw_get_num_parents(const struct clk_hw *hw);
8941115 struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw);
8951116 struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw,
8961117 					  unsigned int index);
1118
+int clk_hw_get_parent_index(struct clk_hw *hw);
1119
+int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *new_parent);
8971120 unsigned int __clk_get_enable_count(struct clk *clk);
8981121 unsigned long clk_hw_get_rate(const struct clk_hw *hw);
899
-unsigned long __clk_get_flags(struct clk *clk);
9001122 unsigned long clk_hw_get_flags(const struct clk_hw *hw);
9011123 bool clk_hw_is_prepared(const struct clk_hw *hw);
9021124 bool clk_hw_rate_is_protected(const struct clk_hw *hw);
....@@ -914,11 +1136,6 @@
9141136 void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent);
9151137 void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate,
9161138 			   unsigned long max_rate);
917
-
918
-unsigned long clk_aggregate_rate(struct clk_hw *hw,
919
-					const struct clk_core *parent);
920
-int clk_vote_rate_vdd(struct clk_core *core, unsigned long rate);
921
-void clk_unvote_rate_vdd(struct clk_core *core, unsigned long rate);
9221139 
9231140 static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src)
9241141 {
....@@ -951,8 +1168,6 @@
9511168  */
9521169 unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate);
9531170 
954
-struct of_device_id;
955
-
9561171 struct clk_onecell_data {
9571172 	struct clk **clks;
9581173 	unsigned int clk_num;
....@@ -962,8 +1177,6 @@
9621177 	unsigned int num;
9631178 	struct clk_hw *hws[];
9641179 };
965
-
966
-extern struct of_device_id __clk_of_table;
9671180 
9681181 #define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn)
9691182 
....@@ -988,11 +1201,63 @@
9881201 		.ops		= _ops,				\
9891202 	})
9901203 
1204
+#define CLK_HW_INIT_HW(_name, _parent, _ops, _flags)			\
1205
+	(&(struct clk_init_data) {					\
1206
+		.flags		= _flags,				\
1207
+		.name		= _name,				\
1208
+		.parent_hws	= (const struct clk_hw*[]) { _parent },	\
1209
+		.num_parents	= 1,					\
1210
+		.ops		= _ops,					\
1211
+	})
1212
+
1213
+/*
1214
+ * This macro is intended for drivers to be able to share the otherwise
1215
+ * individual struct clk_hw[] compound literals created by the compiler
1216
+ * when using CLK_HW_INIT_HW. It does NOT support multiple parents.
1217
+ */
1218
+#define CLK_HW_INIT_HWS(_name, _parent, _ops, _flags)			\
1219
+	(&(struct clk_init_data) {					\
1220
+		.flags		= _flags,				\
1221
+		.name		= _name,				\
1222
+		.parent_hws	= _parent,				\
1223
+		.num_parents	= 1,					\
1224
+		.ops		= _ops,					\
1225
+	})
1226
+
1227
+#define CLK_HW_INIT_FW_NAME(_name, _parent, _ops, _flags)		\
1228
+	(&(struct clk_init_data) {					\
1229
+		.flags		= _flags,				\
1230
+		.name		= _name,				\
1231
+		.parent_data	= (const struct clk_parent_data[]) {	\
1232
+					{ .fw_name = _parent },		\
1233
+				  },					\
1234
+		.num_parents	= 1,					\
1235
+		.ops		= _ops,					\
1236
+	})
1237
+
9911238 #define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags)	\
9921239 	(&(struct clk_init_data) {				\
9931240 		.flags		= _flags,			\
9941241 		.name		= _name,			\
9951242 		.parent_names	= _parents,			\
1243
+		.num_parents	= ARRAY_SIZE(_parents),		\
1244
+		.ops		= _ops,				\
1245
+	})
1246
+
1247
+#define CLK_HW_INIT_PARENTS_HW(_name, _parents, _ops, _flags)	\
1248
+	(&(struct clk_init_data) {				\
1249
+		.flags		= _flags,			\
1250
+		.name		= _name,			\
1251
+		.parent_hws	= _parents,			\
1252
+		.num_parents	= ARRAY_SIZE(_parents),		\
1253
+		.ops		= _ops,				\
1254
+	})
1255
+
1256
+#define CLK_HW_INIT_PARENTS_DATA(_name, _parents, _ops, _flags)	\
1257
+	(&(struct clk_init_data) {				\
1258
+		.flags		= _flags,			\
1259
+		.name		= _name,			\
1260
+		.parent_data	= _parents,			\
9961261 		.num_parents	= ARRAY_SIZE(_parents),		\
9971262 		.ops		= _ops,				\
9981263 	})
....@@ -1015,6 +1280,43 @@
10151280 					      _parent,			\
10161281 					      &clk_fixed_factor_ops,	\
10171282 					      _flags),			\
1283
+	}
1284
+
1285
+#define CLK_FIXED_FACTOR_HW(_struct, _name, _parent,			\
1286
+			    _div, _mult, _flags)			\
1287
+	struct clk_fixed_factor _struct = {				\
1288
+		.div		= _div,					\
1289
+		.mult		= _mult,				\
1290
+		.hw.init	= CLK_HW_INIT_HW(_name,			\
1291
+						 _parent,		\
1292
+						 &clk_fixed_factor_ops,	\
1293
+						 _flags),		\
1294
+	}
1295
+
1296
+/*
1297
+ * This macro allows the driver to reuse the _parent array for multiple
1298
+ * fixed factor clk declarations.
1299
+ */
1300
+#define CLK_FIXED_FACTOR_HWS(_struct, _name, _parent,			\
1301
+			     _div, _mult, _flags)			\
1302
+	struct clk_fixed_factor _struct = {				\
1303
+		.div		= _div,					\
1304
+		.mult		= _mult,				\
1305
+		.hw.init	= CLK_HW_INIT_HWS(_name,		\
1306
+						  _parent,		\
1307
+						  &clk_fixed_factor_ops, \
1308
+						  _flags),	\
1309
+	}
1310
+
1311
+#define CLK_FIXED_FACTOR_FW_NAME(_struct, _name, _parent,		\
1312
+				 _div, _mult, _flags)			\
1313
+	struct clk_fixed_factor _struct = {				\
1314
+		.div		= _div,					\
1315
+		.mult		= _mult,				\
1316
+		.hw.init	= CLK_HW_INIT_FW_NAME(_name,		\
1317
+						      _parent,		\
1318
+						      &clk_fixed_factor_ops, \
1319
+						      _flags),		\
10181320 	}
10191321 
10201322 #ifdef CONFIG_OF
....@@ -1101,36 +1403,6 @@
11011403 }
11021404 #endif /* CONFIG_OF */
11031405 
1104
-/*
1105
- * wrap access to peripherals in accessor routines
1106
- * for improved portability across platforms
1107
- */
1406
+void clk_gate_restore_context(struct clk_hw *hw);
11081407 
1109
-#if IS_ENABLED(CONFIG_PPC)
1110
-
1111
-static inline u32 clk_readl(u32 __iomem *reg)
1112
-{
1113
-	return ioread32be(reg);
1114
-}
1115
-
1116
-static inline void clk_writel(u32 val, u32 __iomem *reg)
1117
-{
1118
-	iowrite32be(val, reg);
1119
-}
1120
-
1121
-#else	/* platform dependent I/O accessors */
1122
-
1123
-static inline u32 clk_readl(u32 __iomem *reg)
1124
-{
1125
-	return readl(reg);
1126
-}
1127
-
1128
-static inline void clk_writel(u32 val, u32 __iomem *reg)
1129
-{
1130
-	writel(val, reg);
1131
-}
1132
-
1133
-#endif	/* platform dependent I/O accessors */
1134
-
1135
-#endif /* CONFIG_COMMON_CLK */
11361408 #endif /* CLK_PROVIDER_H */