hc
2024-05-10 23fa18eaa71266feff7ba8d83022d9e1cc83c65a
kernel/include/linux/clk/tegra.h
....@@ -1,17 +1,6 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
12 /*
23 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3
- *
4
- * This program is free software; you can redistribute it and/or modify it
5
- * under the terms and conditions of the GNU General Public License,
6
- * version 2, as published by the Free Software Foundation.
7
- *
8
- * This program is distributed in the hope it will be useful, but WITHOUT
9
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11
- * more details.
12
- *
13
- * You should have received a copy of the GNU General Public License
14
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
154 */
165
176 #ifndef __LINUX_CLK_TEGRA_H_
....@@ -119,6 +108,19 @@
119108
120109 tegra_cpu_car_ops->resume();
121110 }
111
+#else
112
+static inline bool tegra_cpu_rail_off_ready(void)
113
+{
114
+ return false;
115
+}
116
+
117
+static inline void tegra_cpu_clock_suspend(void)
118
+{
119
+}
120
+
121
+static inline void tegra_cpu_clock_resume(void)
122
+{
123
+}
122124 #endif
123125
124126 extern void tegra210_xusb_pll_hw_control_enable(void);
....@@ -129,5 +131,43 @@
129131 extern void tegra210_put_utmipll_in_iddq(void);
130132 extern void tegra210_put_utmipll_out_iddq(void);
131133 extern int tegra210_clk_handle_mbist_war(unsigned int id);
134
+extern void tegra210_clk_emc_dll_enable(bool flag);
135
+extern void tegra210_clk_emc_dll_update_setting(u32 emc_dll_src_value);
136
+extern void tegra210_clk_emc_update_setting(u32 emc_src_value);
137
+
138
+struct clk;
139
+
140
+typedef long (tegra20_clk_emc_round_cb)(unsigned long rate,
141
+ unsigned long min_rate,
142
+ unsigned long max_rate,
143
+ void *arg);
144
+
145
+void tegra20_clk_set_emc_round_callback(tegra20_clk_emc_round_cb *round_cb,
146
+ void *cb_arg);
147
+int tegra20_clk_prepare_emc_mc_same_freq(struct clk *emc_clk, bool same);
148
+
149
+struct tegra210_clk_emc_config {
150
+ unsigned long rate;
151
+ bool same_freq;
152
+ u32 value;
153
+
154
+ unsigned long parent_rate;
155
+ u8 parent;
156
+};
157
+
158
+struct tegra210_clk_emc_provider {
159
+ struct module *owner;
160
+ struct device *dev;
161
+
162
+ struct tegra210_clk_emc_config *configs;
163
+ unsigned int num_configs;
164
+
165
+ int (*set_rate)(struct device *dev,
166
+ const struct tegra210_clk_emc_config *config);
167
+};
168
+
169
+int tegra210_clk_emc_attach(struct clk *clk,
170
+ struct tegra210_clk_emc_provider *provider);
171
+void tegra210_clk_emc_detach(struct clk *clk);
132172
133173 #endif /* __LINUX_CLK_TEGRA_H_ */