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| 1 | +/* SPDX-License-Identifier: GPL-2.0-only */ |
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1 | 2 | /* |
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2 | 3 | * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. |
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3 | | - * |
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4 | | - * This program is free software; you can redistribute it and/or modify it |
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5 | | - * under the terms and conditions of the GNU General Public License, |
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6 | | - * version 2, as published by the Free Software Foundation. |
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7 | | - * |
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8 | | - * This program is distributed in the hope it will be useful, but WITHOUT |
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9 | | - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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10 | | - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
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11 | | - * more details. |
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12 | | - * |
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13 | | - * You should have received a copy of the GNU General Public License |
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14 | | - * along with this program. If not, see <http://www.gnu.org/licenses/>. |
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15 | 4 | */ |
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16 | 5 | |
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17 | 6 | #ifndef __LINUX_CLK_TEGRA_H_ |
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.. | .. |
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119 | 108 | |
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120 | 109 | tegra_cpu_car_ops->resume(); |
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121 | 110 | } |
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| 111 | +#else |
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| 112 | +static inline bool tegra_cpu_rail_off_ready(void) |
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| 113 | +{ |
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| 114 | + return false; |
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| 115 | +} |
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| 116 | + |
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| 117 | +static inline void tegra_cpu_clock_suspend(void) |
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| 118 | +{ |
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| 119 | +} |
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| 120 | + |
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| 121 | +static inline void tegra_cpu_clock_resume(void) |
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| 122 | +{ |
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| 123 | +} |
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122 | 124 | #endif |
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123 | 125 | |
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124 | 126 | extern void tegra210_xusb_pll_hw_control_enable(void); |
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.. | .. |
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129 | 131 | extern void tegra210_put_utmipll_in_iddq(void); |
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130 | 132 | extern void tegra210_put_utmipll_out_iddq(void); |
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131 | 133 | extern int tegra210_clk_handle_mbist_war(unsigned int id); |
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| 134 | +extern void tegra210_clk_emc_dll_enable(bool flag); |
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| 135 | +extern void tegra210_clk_emc_dll_update_setting(u32 emc_dll_src_value); |
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| 136 | +extern void tegra210_clk_emc_update_setting(u32 emc_src_value); |
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| 137 | + |
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| 138 | +struct clk; |
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| 139 | + |
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| 140 | +typedef long (tegra20_clk_emc_round_cb)(unsigned long rate, |
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| 141 | + unsigned long min_rate, |
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| 142 | + unsigned long max_rate, |
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| 143 | + void *arg); |
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| 144 | + |
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| 145 | +void tegra20_clk_set_emc_round_callback(tegra20_clk_emc_round_cb *round_cb, |
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| 146 | + void *cb_arg); |
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| 147 | +int tegra20_clk_prepare_emc_mc_same_freq(struct clk *emc_clk, bool same); |
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| 148 | + |
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| 149 | +struct tegra210_clk_emc_config { |
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| 150 | + unsigned long rate; |
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| 151 | + bool same_freq; |
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| 152 | + u32 value; |
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| 153 | + |
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| 154 | + unsigned long parent_rate; |
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| 155 | + u8 parent; |
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| 156 | +}; |
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| 157 | + |
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| 158 | +struct tegra210_clk_emc_provider { |
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| 159 | + struct module *owner; |
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| 160 | + struct device *dev; |
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| 161 | + |
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| 162 | + struct tegra210_clk_emc_config *configs; |
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| 163 | + unsigned int num_configs; |
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| 164 | + |
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| 165 | + int (*set_rate)(struct device *dev, |
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| 166 | + const struct tegra210_clk_emc_config *config); |
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| 167 | +}; |
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| 168 | + |
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| 169 | +int tegra210_clk_emc_attach(struct clk *clk, |
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| 170 | + struct tegra210_clk_emc_provider *provider); |
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| 171 | +void tegra210_clk_emc_detach(struct clk *clk); |
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132 | 172 | |
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133 | 173 | #endif /* __LINUX_CLK_TEGRA_H_ */ |
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