.. | .. |
---|
| 1 | +/* SPDX-License-Identifier: GPL-2.0-only */ |
---|
1 | 2 | /* |
---|
2 | 3 | * Copyright (c) 2016, The Linux Foundation. All rights reserved. |
---|
3 | | - * |
---|
4 | | - * This software is licensed under the terms of the GNU General Public |
---|
5 | | - * License version 2, as published by the Free Software Foundation, and |
---|
6 | | - * may be copied, distributed, and modified under those terms. |
---|
7 | | - * |
---|
8 | | - * This program is distributed in the hope that it will be useful, |
---|
9 | | - * but WITHOUT ANY WARRANTY; without even the implied warranty of |
---|
10 | | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
---|
11 | | - * GNU General Public License for more details. |
---|
12 | 4 | */ |
---|
13 | 5 | |
---|
14 | 6 | |
---|
.. | .. |
---|
134 | 126 | #define GCC_USB3_PHY_AUX_CLK 116 |
---|
135 | 127 | #define GCC_USB_HS_SYSTEM_CLK 117 |
---|
136 | 128 | #define GCC_SDCC1_AHB_CLK 118 |
---|
| 129 | +#define GCC_LPASS_Q6_AXI_CLK 119 |
---|
| 130 | +#define GCC_MSS_Q6_BIMC_AXI_CLK 120 |
---|
| 131 | +#define GCC_PCIE_0_CFG_AHB_CLK 121 |
---|
| 132 | +#define GCC_PCIE_0_MSTR_AXI_CLK 122 |
---|
| 133 | +#define GCC_PCIE_0_SLV_AXI_CLK 123 |
---|
| 134 | +#define GCC_PCIE_1_CFG_AHB_CLK 124 |
---|
| 135 | +#define GCC_PCIE_1_MSTR_AXI_CLK 125 |
---|
| 136 | +#define GCC_PCIE_1_SLV_AXI_CLK 126 |
---|
| 137 | +#define GCC_PDM_AHB_CLK 127 |
---|
| 138 | +#define GCC_SDCC2_AHB_CLK 128 |
---|
| 139 | +#define GCC_SDCC3_AHB_CLK 129 |
---|
| 140 | +#define GCC_SDCC4_AHB_CLK 130 |
---|
| 141 | +#define GCC_TSIF_AHB_CLK 131 |
---|
| 142 | +#define GCC_UFS_AHB_CLK 132 |
---|
| 143 | +#define GCC_UFS_RX_SYMBOL_0_CLK 133 |
---|
| 144 | +#define GCC_UFS_RX_SYMBOL_1_CLK 134 |
---|
| 145 | +#define GCC_UFS_TX_SYMBOL_0_CLK 135 |
---|
| 146 | +#define GCC_UFS_TX_SYMBOL_1_CLK 136 |
---|
| 147 | +#define GCC_USB2_HS_PHY_SLEEP_CLK 137 |
---|
| 148 | +#define GCC_USB30_SLEEP_CLK 138 |
---|
| 149 | +#define GCC_USB_HS_AHB_CLK 139 |
---|
| 150 | +#define GCC_USB_PHY_CFG_AHB2PHY_CLK 140 |
---|
| 151 | + |
---|
| 152 | +/* GDSCs */ |
---|
| 153 | +#define PCIE_GDSC 0 |
---|
| 154 | +#define PCIE_0_GDSC 1 |
---|
| 155 | +#define PCIE_1_GDSC 2 |
---|
| 156 | +#define USB30_GDSC 3 |
---|
| 157 | +#define UFS_GDSC 4 |
---|
| 158 | + |
---|
| 159 | +/* Resets */ |
---|
| 160 | +#define USB3_PHY_RESET 0 |
---|
| 161 | +#define USB3PHY_PHY_RESET 1 |
---|
| 162 | +#define PCIE_PHY_0_RESET 2 |
---|
| 163 | +#define PCIE_PHY_1_RESET 3 |
---|
| 164 | +#define QUSB2_PHY_RESET 4 |
---|
137 | 165 | |
---|
138 | 166 | #endif |
---|