disable pwm7

hc

2024-05-10 23fa18eaa71266feff7ba8d83022d9e1cc83c65a

 kernel/drivers/usb/host/ehci-fsl.c
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@@ -23,12 +23,13 @@
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 #include <linux/platform_device.h>
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 #include <linux/fsl_devices.h>
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 #include <linux/of_platform.h>
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+#include <linux/io.h>
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 #include "ehci.h"
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 #include "ehci-fsl.h"
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 #define DRIVER_DESC "Freescale EHCI Host controller driver"
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-#define DRV_NAME "ehci-fsl"
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+#define DRV_NAME "fsl-ehci"
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 static struct hc_driver __read_mostly fsl_ehci_hc_driver;
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..
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@@ -50,6 +51,7 @@
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 	struct resource *res;
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 	int irq;
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 	int retval;
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+	u32 tmp;
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 	pr_debug("initializing FSL-SOC USB Controller\n");
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..
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@@ -114,17 +116,28 @@
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 	}
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 	/* Enable USB controller, 83xx or 8536 */
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-	if (pdata->have_sysif_regs && pdata->controller_ver < FSL_USB_VER_1_6)
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-		clrsetbits_be32(hcd->regs + FSL_SOC_USB_CTRL,
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-				CONTROL_REGISTER_W1C_MASK, 0x4);
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+	if (pdata->have_sysif_regs && pdata->controller_ver < FSL_USB_VER_1_6) {
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+		tmp = ioread32be(hcd->regs + FSL_SOC_USB_CTRL);
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+		tmp &= ~CONTROL_REGISTER_W1C_MASK;
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+		tmp |= 0x4;
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+		iowrite32be(tmp, hcd->regs + FSL_SOC_USB_CTRL);
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+	}
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+
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+	/* Set USB_EN bit to select ULPI phy for USB controller version 2.5 */
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+	if (pdata->controller_ver == FSL_USB_VER_2_5 &&
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+	    pdata->phy_mode == FSL_USB2_PHY_ULPI)
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+		iowrite32be(USB_CTRL_USB_EN, hcd->regs + FSL_SOC_USB_CTRL);
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 	/*
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 	 * Enable UTMI phy and program PTS field in UTMI mode before asserting
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 	 * controller reset for USB Controller version 2.5
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 	 */
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 	if (pdata->has_fsl_erratum_a007792) {
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-		clrsetbits_be32(hcd->regs + FSL_SOC_USB_CTRL,
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-				CONTROL_REGISTER_W1C_MASK, CTRL_UTMI_PHY_EN);
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+		tmp = ioread32be(hcd->regs + FSL_SOC_USB_CTRL);
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+		tmp &= ~CONTROL_REGISTER_W1C_MASK;
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+		tmp |= CTRL_UTMI_PHY_EN;
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+		iowrite32be(tmp, hcd->regs + FSL_SOC_USB_CTRL);
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+
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 		writel(PORT_PTS_UTMI, hcd->regs + FSL_SOC_USB_PORTSC1);
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 	}
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@@ -170,11 +183,22 @@
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 	return retval;
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 }
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185
 
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+static bool usb_phy_clk_valid(struct usb_hcd *hcd)
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+{
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+	void __iomem *non_ehci = hcd->regs;
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+	bool ret = true;
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+
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+	if (!(ioread32be(non_ehci + FSL_SOC_USB_CTRL) & PHY_CLK_VALID))
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+		ret = false;
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+
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+	return ret;
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+}
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+
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 static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
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 			       enum fsl_usb2_phy_modes phy_mode,
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 			       unsigned int port_offset)
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 {
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-	u32 portsc;
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+	u32 portsc, tmp;
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 	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
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 	void __iomem *non_ehci = hcd->regs;
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 	struct device *dev = hcd->self.controller;
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@@ -192,11 +216,16 @@
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 	case FSL_USB2_PHY_ULPI:
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 		if (pdata->have_sysif_regs && pdata->controller_ver) {
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 			/* controller version 1.6 or above */
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-			clrbits32(non_ehci + FSL_SOC_USB_CTRL,
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-				  CONTROL_REGISTER_W1C_MASK | UTMI_PHY_EN);
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-			clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
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-					CONTROL_REGISTER_W1C_MASK,
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-					ULPI_PHY_CLK_SEL | USB_CTRL_USB_EN);
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+			/* turn off UTMI PHY first */
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+			tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
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+			tmp &= ~(CONTROL_REGISTER_W1C_MASK | UTMI_PHY_EN);
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+			iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL);
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+
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+			/* then turn on ULPI and enable USB controller */
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+			tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
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+			tmp &= ~CONTROL_REGISTER_W1C_MASK;
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+			tmp |= ULPI_PHY_CLK_SEL | USB_CTRL_USB_EN;
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+			iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL);
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 		}
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 		portsc |= PORT_PTS_ULPI;
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 		break;
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@@ -205,45 +234,66 @@
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 		break;
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 	case FSL_USB2_PHY_UTMI_WIDE:
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 		portsc |= PORT_PTS_PTW;
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-		/* fall through */
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+		fallthrough;
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 	case FSL_USB2_PHY_UTMI:
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+		/* Presence of this node "has_fsl_erratum_a006918"
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+		 * in device-tree is used to stop USB controller
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+		 * initialization in Linux
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+		 */
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+		if (pdata->has_fsl_erratum_a006918) {
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+			dev_warn(dev, "USB PHY clock invalid\n");
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+			return -EINVAL;
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+		}
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+		fallthrough;
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 	case FSL_USB2_PHY_UTMI_DUAL:
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+		/* PHY_CLK_VALID bit is de-featured from all controller
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+		 * versions below 2.4 and is to be checked only for
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+		 * internal UTMI phy
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+		 */
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+		if (pdata->controller_ver > FSL_USB_VER_2_4 &&
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+		    pdata->have_sysif_regs && !usb_phy_clk_valid(hcd)) {
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+			dev_err(dev, "USB PHY clock invalid\n");
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+			return -EINVAL;
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+		}
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+
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 		if (pdata->have_sysif_regs && pdata->controller_ver) {
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 			/* controller version 1.6 or above */
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-			clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
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-					CONTROL_REGISTER_W1C_MASK, UTMI_PHY_EN);
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+			tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
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+			tmp &= ~CONTROL_REGISTER_W1C_MASK;
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+			tmp |= UTMI_PHY_EN;
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+			iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL);
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+
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 			mdelay(FSL_UTMI_PHY_DLY);  /* Delay for UTMI PHY CLK to
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 						become stable - 10ms*/
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 		}
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 		/* enable UTMI PHY */
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-		if (pdata->have_sysif_regs)
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-			clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
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-					CONTROL_REGISTER_W1C_MASK,
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-					CTRL_UTMI_PHY_EN);
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+		if (pdata->have_sysif_regs) {
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+			tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
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+			tmp &= ~CONTROL_REGISTER_W1C_MASK;
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+			tmp |= CTRL_UTMI_PHY_EN;
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+			iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL);
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+		}
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 		portsc |= PORT_PTS_UTMI;
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 		break;
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 	case FSL_USB2_PHY_NONE:
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 		break;
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 	}
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-	/*
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-	 * check PHY_CLK_VALID to determine phy clock presence before writing
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-	 * to portsc
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-	 */
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-	if (pdata->check_phy_clk_valid) {
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-		if (!(ioread32be(non_ehci + FSL_SOC_USB_CTRL) &
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-		    PHY_CLK_VALID)) {
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-			dev_warn(hcd->self.controller,
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-				 "USB PHY clock invalid\n");
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-			return -EINVAL;
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-		}
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+	if (pdata->have_sysif_regs &&
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+	    pdata->controller_ver > FSL_USB_VER_1_6 &&
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+	    !usb_phy_clk_valid(hcd)) {
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+		dev_warn(hcd->self.controller, "USB PHY clock invalid\n");
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+		return -EINVAL;
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 	}
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 	ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]);
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-	if (phy_mode != FSL_USB2_PHY_ULPI && pdata->have_sysif_regs)
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-		clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
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-				CONTROL_REGISTER_W1C_MASK, USB_CTRL_USB_EN);
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+	if (phy_mode != FSL_USB2_PHY_ULPI && pdata->have_sysif_regs) {
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+		tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
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+		tmp &= ~CONTROL_REGISTER_W1C_MASK;
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+		tmp |= USB_CTRL_USB_EN;
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+		iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL);
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+	}
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 	return 0;
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 }
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@@ -284,14 +334,9 @@
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 			return -EINVAL;
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 	if (pdata->operating_mode == FSL_USB2_MPH_HOST) {
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-		unsigned int chip, rev, svr;
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-
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-		svr = mfspr(SPRN_SVR);
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-		chip = svr >> 16;
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-		rev = (svr >> 4) & 0xf;
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 		/* Deal with USB Erratum #14 on MPC834x Rev 1.0 & 1.1 chips */
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-		if ((rev == 1) && (chip >= 0x8050) && (chip <= 0x8055))
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+		if (pdata->has_fsl_erratum_14 == 1)
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 			ehci->has_fsl_port_bug = 1;
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 		if (pdata->port_enables & FSL_USB2_PORT0_ENABLED)
..
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@@ -638,7 +683,7 @@
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 /**
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  * fsl_ehci_drv_remove - shutdown processing for FSL-based HCDs
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- * @dev: USB Host Controller being removed
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+ * @pdev: USB Host Controller being removed
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  * Context: !in_interrupt()
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  *
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  * Reverses the effect of usb_hcd_fsl_probe().