forked from ~ljy/RK356X_SDK_RELEASE

hc
2024-05-10 23fa18eaa71266feff7ba8d83022d9e1cc83c65a
kernel/drivers/staging/vt6655/rf.c
....@@ -163,7 +163,7 @@
163163 0x841FF200 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Need modify for 11a: 451FE2 */
164164 0x3FDFA300 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Need modify for 11a: 5FDFA3 */
165165 0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* 11b/g // Need modify for 11a */
166
- /* RoberYu:20050113, Rev0.47 Regsiter Setting Guide */
166
+ /* RoberYu:20050113, Rev0.47 Register Setting Guide */
167167 0x802B5500 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Need modify for 11a: 8D1B55 */
168168 0x56AF3600 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW,
169169 0xCE020700 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Need modify for 11a: 860207 */
....@@ -171,7 +171,7 @@
171171 0x221BB900 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW,
172172 0xE0000A00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Need modify for 11a: E0600A */
173173 0x08031B00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* init 0x080B1B00 => 0x080F1B00 for 3 wire control TxGain(D10) */
174
- /* RoberYu:20050113, Rev0.47 Regsiter Setting Guide */
174
+ /* RoberYu:20050113, Rev0.47 Register Setting Guide */
175175 0x000A3C00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Need modify for 11a: 00143C */
176176 0xFFFFFD00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW,
177177 0x00000E00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW,
....@@ -419,7 +419,7 @@
419419
420420 MACvWordRegBitsOn(iobase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPECTI |
421421 SOFTPWRCTL_TXPEINV));
422
- BBvPowerSaveModeOFF(priv); /* RobertYu:20050106, have DC value for Calibration */
422
+ bb_power_save_mode_off(priv); /* RobertYu:20050106, have DC value for Calibration */
423423
424424 for (ii = 0; ii < CB_AL7230_INIT_SEQ; ii++)
425425 ret &= IFRFbWriteEmbedded(priv, dwAL7230InitTable[ii]);
....@@ -436,14 +436,14 @@
436436 ret &= IFRFbWriteEmbedded(priv, (0x3ABA8F00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW));
437437 MACvTimer0MicroSDelay(priv, 30);/* 30us */
438438 /* TXDCOC:disable, RCK:disable */
439
- ret &= IFRFbWriteEmbedded(priv, dwAL7230InitTable[CB_AL7230_INIT_SEQ-1]);
439
+ ret &= IFRFbWriteEmbedded(priv, dwAL7230InitTable[CB_AL7230_INIT_SEQ - 1]);
440440
441441 MACvWordRegBitsOn(iobase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPE3 |
442442 SOFTPWRCTL_SWPE2 |
443443 SOFTPWRCTL_SWPECTI |
444444 SOFTPWRCTL_TXPEINV));
445445
446
- BBvPowerSaveModeON(priv); /* RobertYu:20050106 */
446
+ bb_power_save_mode_on(priv); /* RobertYu:20050106 */
447447
448448 /* PE1: TX_ON, PE2: RX_ON, PE3: PLLON */
449449 /* 3-wire control for power saving mode */
....@@ -558,7 +558,8 @@
558558 MACvTimer0MicroSDelay(priv, 30);/* 30us */
559559 ret &= IFRFbWriteEmbedded(priv, (0x00780f00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW));
560560 MACvTimer0MicroSDelay(priv, 30);/* 30us */
561
- ret &= IFRFbWriteEmbedded(priv, dwAL2230InitTable[CB_AL2230_INIT_SEQ-1]);
561
+ ret &= IFRFbWriteEmbedded(priv,
562
+ dwAL2230InitTable[CB_AL2230_INIT_SEQ - 1]);
562563
563564 MACvWordRegBitsOn(iobase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPE3 |
564565 SOFTPWRCTL_SWPE2 |
....@@ -702,9 +703,9 @@
702703 for (ii = 0; ii < CB_AL2230_INIT_SEQ; ii++)
703704 MACvSetMISCFifo(priv, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL2230InitTable[ii]);
704705
705
- MACvSetMISCFifo(priv, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL2230ChannelTable0[uChannel-1]);
706
+ MACvSetMISCFifo(priv, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL2230ChannelTable0[uChannel - 1]);
706707 ii++;
707
- MACvSetMISCFifo(priv, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL2230ChannelTable1[uChannel-1]);
708
+ MACvSetMISCFifo(priv, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL2230ChannelTable1[uChannel - 1]);
708709 break;
709710
710711 /* Need to check, PLLON need to be low for channel setting */
....@@ -723,11 +724,11 @@
723724 MACvSetMISCFifo(priv, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230InitTableAMode[ii]);
724725 }
725726
726
- MACvSetMISCFifo(priv, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230ChannelTable0[uChannel-1]);
727
+ MACvSetMISCFifo(priv, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230ChannelTable0[uChannel - 1]);
727728 ii++;
728
- MACvSetMISCFifo(priv, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230ChannelTable1[uChannel-1]);
729
+ MACvSetMISCFifo(priv, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230ChannelTable1[uChannel - 1]);
729730 ii++;
730
- MACvSetMISCFifo(priv, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230ChannelTable2[uChannel-1]);
731
+ MACvSetMISCFifo(priv, (unsigned short)(MISCFIFO_SYNDATA_IDX + ii), dwAL7230ChannelTable2[uChannel - 1]);
731732 break;
732733
733734 case RF_NOTHING:
....@@ -755,13 +756,9 @@
755756 * Return Value: true if succeeded; false if failed.
756757 *
757758 */
758
-bool RFbSetPower(
759
- struct vnt_private *priv,
760
- unsigned int rate,
761
- u16 uCH
762
-)
759
+bool RFbSetPower(struct vnt_private *priv, unsigned int rate, u16 uCH)
763760 {
764
- bool ret = true;
761
+ bool ret;
765762 unsigned char byPwr = 0;
766763 unsigned char byDec = 0;
767764
....@@ -792,7 +789,7 @@
792789 byDec = byPwr + 10;
793790
794791 if (byDec >= priv->byMaxPwrLevel)
795
- byDec = priv->byMaxPwrLevel-1;
792
+ byDec = priv->byMaxPwrLevel - 1;
796793
797794 byPwr = byDec;
798795 break;
....@@ -828,11 +825,8 @@
828825 *
829826 */
830827
831
-bool RFbRawSetPower(
832
- struct vnt_private *priv,
833
- unsigned char byPwr,
834
- unsigned int rate
835
-)
828
+bool RFbRawSetPower(struct vnt_private *priv, unsigned char byPwr,
829
+ unsigned int rate)
836830 {
837831 bool ret = true;
838832 unsigned long dwMax7230Pwr = 0;
....@@ -894,11 +888,7 @@
894888 *
895889 */
896890 void
897
-RFvRSSITodBm(
898
- struct vnt_private *priv,
899
- unsigned char byCurrRSSI,
900
- long *pldBm
901
- )
891
+RFvRSSITodBm(struct vnt_private *priv, unsigned char byCurrRSSI, long *pldBm)
902892 {
903893 unsigned char byIdx = (((byCurrRSSI & 0xC0) >> 6) & 0x03);
904894 long b = (byCurrRSSI & 0x3F);