forked from ~ljy/RK356X_SDK_RELEASE

hc
2024-05-10 23fa18eaa71266feff7ba8d83022d9e1cc83c65a
kernel/drivers/staging/rtl8188eu/hal/phy.c
....@@ -51,8 +51,7 @@
5151 usb_write32(adapt, regaddr, data);
5252 }
5353
54
-static u32 rf_serial_read(struct adapter *adapt,
55
- enum rf_radio_path rfpath, u32 offset)
54
+static u32 rf_serial_read(struct adapter *adapt, enum rf_radio_path rfpath, u32 offset)
5655 {
5756 u32 ret = 0;
5857 struct bb_reg_def *phyreg = &adapt->HalData->PHYRegDef[rfpath];
....@@ -69,10 +68,10 @@
6968 bMaskDWord);
7069
7170 tmplong2 = (tmplong2 & (~bLSSIReadAddress)) |
72
- (offset<<23) | bLSSIReadEdge;
71
+ (offset << 23) | bLSSIReadEdge;
7372
7473 phy_set_bb_reg(adapt, rFPGA0_XA_HSSIParameter2, bMaskDWord,
75
- tmplong&(~bLSSIReadEdge));
74
+ tmplong & (~bLSSIReadEdge));
7675 udelay(10);
7776
7877 phy_set_bb_reg(adapt, phyreg->rfHSSIPara2, bMaskDWord, tmplong2);
....@@ -102,12 +101,12 @@
102101 struct bb_reg_def *phyreg = &adapt->HalData->PHYRegDef[rfpath];
103102
104103 offset &= 0xff;
105
- data_and_addr = ((offset<<20) | (data&0x000fffff)) & 0x0fffffff;
104
+ data_and_addr = ((offset << 20) | (data & 0x000fffff)) & 0x0fffffff;
106105 phy_set_bb_reg(adapt, phyreg->rf3wireOffset, bMaskDWord, data_and_addr);
107106 }
108107
109108 u32 rtw_hal_read_rfreg(struct adapter *adapt, enum rf_radio_path rf_path,
110
- u32 reg_addr, u32 bit_mask)
109
+ u32 reg_addr, u32 bit_mask)
111110 {
112111 u32 original_value, bit_shift;
113112
....@@ -117,7 +116,7 @@
117116 }
118117
119118 void phy_set_rf_reg(struct adapter *adapt, enum rf_radio_path rf_path,
120
- u32 reg_addr, u32 bit_mask, u32 data)
119
+ u32 reg_addr, u32 bit_mask, u32 data)
121120 {
122121 u32 original_value, bit_shift;
123122
....@@ -143,20 +142,20 @@
143142 for (TxCount = 0; TxCount < path_nums; TxCount++) {
144143 if (TxCount == RF_PATH_A) {
145144 cck_pwr[TxCount] = hal_data->Index24G_CCK_Base[TxCount][index];
146
- ofdm_pwr[TxCount] = hal_data->Index24G_BW40_Base[RF_PATH_A][index]+
145
+ ofdm_pwr[TxCount] = hal_data->Index24G_BW40_Base[RF_PATH_A][index] +
147146 hal_data->OFDM_24G_Diff[TxCount][RF_PATH_A];
148147
149
- bw20_pwr[TxCount] = hal_data->Index24G_BW40_Base[RF_PATH_A][index]+
148
+ bw20_pwr[TxCount] = hal_data->Index24G_BW40_Base[RF_PATH_A][index] +
150149 hal_data->BW20_24G_Diff[TxCount][RF_PATH_A];
151150 bw40_pwr[TxCount] = hal_data->Index24G_BW40_Base[TxCount][index];
152151 } else if (TxCount == RF_PATH_B) {
153152 cck_pwr[TxCount] = hal_data->Index24G_CCK_Base[TxCount][index];
154
- ofdm_pwr[TxCount] = hal_data->Index24G_BW40_Base[RF_PATH_A][index]+
155
- hal_data->BW20_24G_Diff[RF_PATH_A][index]+
153
+ ofdm_pwr[TxCount] = hal_data->Index24G_BW40_Base[RF_PATH_A][index] +
154
+ hal_data->BW20_24G_Diff[RF_PATH_A][index] +
156155 hal_data->BW20_24G_Diff[TxCount][index];
157156
158
- bw20_pwr[TxCount] = hal_data->Index24G_BW40_Base[RF_PATH_A][index]+
159
- hal_data->BW20_24G_Diff[TxCount][RF_PATH_A]+
157
+ bw20_pwr[TxCount] = hal_data->Index24G_BW40_Base[RF_PATH_A][index] +
158
+ hal_data->BW20_24G_Diff[TxCount][RF_PATH_A] +
160159 hal_data->BW20_24G_Diff[TxCount][index];
161160 bw40_pwr[TxCount] = hal_data->Index24G_BW40_Base[TxCount][index];
162161 }
....@@ -190,7 +189,7 @@
190189
191190 rtl88eu_phy_rf6052_set_cck_txpower(adapt, &cck_pwr[0]);
192191 rtl88eu_phy_rf6052_set_ofdm_txpower(adapt, &ofdm_pwr[0], &bw20_pwr[0],
193
- &bw40_pwr[0], channel);
192
+ &bw40_pwr[0], channel);
194193 }
195194
196195 static void phy_set_bw_mode_callback(struct adapter *adapt)
....@@ -205,7 +204,7 @@
205204 /* Set MAC register */
206205
207206 reg_bw_opmode = usb_read8(adapt, REG_BWOPMODE);
208
- reg_prsr_rsc = usb_read8(adapt, REG_RRSR+2);
207
+ reg_prsr_rsc = usb_read8(adapt, REG_RRSR + 2);
209208
210209 switch (hal_data->CurrentChannelBW) {
211210 case HT_CHANNEL_WIDTH_20:
....@@ -215,9 +214,9 @@
215214 case HT_CHANNEL_WIDTH_40:
216215 reg_bw_opmode &= ~BW_OPMODE_20MHZ;
217216 usb_write8(adapt, REG_BWOPMODE, reg_bw_opmode);
218
- reg_prsr_rsc = (reg_prsr_rsc&0x90) |
219
- (hal_data->nCur40MhzPrimeSC<<5);
220
- usb_write8(adapt, REG_RRSR+2, reg_prsr_rsc);
217
+ reg_prsr_rsc = (reg_prsr_rsc & 0x90) |
218
+ (hal_data->nCur40MhzPrimeSC << 5);
219
+ usb_write8(adapt, REG_RRSR + 2, reg_prsr_rsc);
221220 break;
222221 default:
223222 break;
....@@ -236,11 +235,11 @@
236235 * These settings are required only for 40MHz
237236 */
238237 phy_set_bb_reg(adapt, rCCK0_System, bCCKSideBand,
239
- (hal_data->nCur40MhzPrimeSC>>1));
238
+ (hal_data->nCur40MhzPrimeSC >> 1));
240239 phy_set_bb_reg(adapt, rOFDM1_LSTF, 0xC00,
241240 hal_data->nCur40MhzPrimeSC);
242241 phy_set_bb_reg(adapt, 0x818, (BIT(26) | BIT(27)),
243
- (hal_data->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
242
+ (hal_data->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
244243 break;
245244 default:
246245 break;
....@@ -251,7 +250,7 @@
251250 }
252251
253252 void rtw_hal_set_bwmode(struct adapter *adapt, enum ht_channel_width bandwidth,
254
- unsigned char offset)
253
+ unsigned char offset)
255254 {
256255 struct hal_data_8188e *hal_data = adapt->HalData;
257256 enum ht_channel_width tmp_bw = hal_data->CurrentChannelBW;
....@@ -298,25 +297,6 @@
298297
299298 #define ODM_TXPWRTRACK_MAX_IDX_88E 6
300299
301
-static u8 get_right_chnl_for_iqk(u8 chnl)
302
-{
303
- u8 place;
304
- u8 channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = {
305
- 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64,
306
- 100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122,
307
- 124, 126, 128, 130, 132, 134, 136, 138, 140, 149, 151, 153,
308
- 155, 157, 159, 161, 163, 165
309
- };
310
-
311
- if (chnl > 14) {
312
- for (place = 0; place < sizeof(channel_all); place++) {
313
- if (channel_all[place] == chnl)
314
- return ++place;
315
- }
316
- }
317
- return 0;
318
-}
319
-
320300 void rtl88eu_dm_txpower_track_adjust(struct odm_dm_struct *dm_odm, u8 type,
321301 u8 *direction, u32 *out_write_val)
322302 {
....@@ -356,16 +336,16 @@
356336 if (pwr_value >= ODM_TXPWRTRACK_MAX_IDX_88E && *direction == 1)
357337 pwr_value = ODM_TXPWRTRACK_MAX_IDX_88E;
358338
359
- *out_write_val = pwr_value | (pwr_value<<8) | (pwr_value<<16) |
360
- (pwr_value<<24);
339
+ *out_write_val = pwr_value | (pwr_value << 8) | (pwr_value << 16) |
340
+ (pwr_value << 24);
361341 }
362342
363343 static void dm_txpwr_track_setpwr(struct odm_dm_struct *dm_odm)
364344 {
365345 if (dm_odm->BbSwingFlagOfdm || dm_odm->BbSwingFlagCck) {
366346 ODM_RT_TRACE(dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
367
- ("dm_txpwr_track_setpwr CH=%d\n", *(dm_odm->pChannel)));
368
- phy_set_tx_power_level(dm_odm->Adapter, *(dm_odm->pChannel));
347
+ ("%s CH=%d\n", __func__, *dm_odm->pChannel));
348
+ phy_set_tx_power_level(dm_odm->Adapter, *dm_odm->pChannel);
369349 dm_odm->BbSwingFlagOfdm = false;
370350 dm_odm->BbSwingFlagCck = false;
371351 }
....@@ -408,9 +388,9 @@
408388
409389 if (thermal_val) {
410390 /* Query OFDM path A default setting */
411
- ele_d = phy_query_bb_reg(adapt, rOFDM0_XATxIQImbalance, bMaskDWord)&bMaskOFDM_D;
391
+ ele_d = phy_query_bb_reg(adapt, rOFDM0_XATxIQImbalance, bMaskDWord) & bMaskOFDM_D;
412392 for (i = 0; i < OFDM_TABLE_SIZE_92D; i++) {
413
- if (ele_d == (OFDMSwingTable[i]&bMaskOFDM_D)) {
393
+ if (ele_d == (OFDMSwingTable[i] & bMaskOFDM_D)) {
414394 ofdm_index_old[0] = (u8)i;
415395 dm_odm->BbSwingIdxOfdmBase = (u8)i;
416396 break;
....@@ -422,11 +402,11 @@
422402
423403 for (i = 0; i < CCK_TABLE_SIZE; i++) {
424404 if ((dm_odm->RFCalibrateInfo.bCCKinCH14 &&
425
- memcmp(&temp_cck, &CCKSwingTable_Ch14[i][2], 4)) ||
426
- memcmp(&temp_cck, &CCKSwingTable_Ch1_Ch13[i][2], 4)) {
427
- cck_index_old = (u8)i;
428
- dm_odm->BbSwingIdxCckBase = (u8)i;
429
- break;
405
+ memcmp(&temp_cck, &CCKSwingTable_Ch14[i][2], 4)) ||
406
+ memcmp(&temp_cck, &CCKSwingTable_Ch1_Ch13[i][2], 4)) {
407
+ cck_index_old = (u8)i;
408
+ dm_odm->BbSwingIdxCckBase = (u8)i;
409
+ break;
430410 }
431411 }
432412
....@@ -456,9 +436,9 @@
456436 thermal_val = (u8)(thermal_avg / thermal_avg_count);
457437
458438 if (dm_odm->RFCalibrateInfo.bDoneTxpower &&
459
- !dm_odm->RFCalibrateInfo.bReloadtxpowerindex)
439
+ !dm_odm->RFCalibrateInfo.bReloadtxpowerindex) {
460440 delta = abs(thermal_val - dm_odm->RFCalibrateInfo.ThermalValue);
461
- else {
441
+ } else {
462442 delta = abs(thermal_val - hal_data->EEPROMThermalMeter);
463443 if (dm_odm->RFCalibrateInfo.bReloadtxpowerindex) {
464444 dm_odm->RFCalibrateInfo.bReloadtxpowerindex = false;
....@@ -491,18 +471,18 @@
491471 }
492472 }
493473 if (offset >= index_mapping_NUM_88E)
494
- offset = index_mapping_NUM_88E-1;
474
+ offset = index_mapping_NUM_88E - 1;
495475
496476 /* Updating ofdm_index values with new OFDM / CCK offset */
497477 ofdm_index[0] = dm_odm->RFCalibrateInfo.OFDM_index[0] + ofdm_index_mapping[j][offset];
498
- if (ofdm_index[0] > OFDM_TABLE_SIZE_92D-1)
499
- ofdm_index[0] = OFDM_TABLE_SIZE_92D-1;
478
+ if (ofdm_index[0] > OFDM_TABLE_SIZE_92D - 1)
479
+ ofdm_index[0] = OFDM_TABLE_SIZE_92D - 1;
500480 else if (ofdm_index[0] < ofdm_min_index)
501481 ofdm_index[0] = ofdm_min_index;
502482
503483 cck_index = dm_odm->RFCalibrateInfo.CCK_index + ofdm_index_mapping[j][offset];
504
- if (cck_index > CCK_TABLE_SIZE-1)
505
- cck_index = CCK_TABLE_SIZE-1;
484
+ if (cck_index > CCK_TABLE_SIZE - 1)
485
+ cck_index = CCK_TABLE_SIZE - 1;
506486 else if (cck_index < 0)
507487 cck_index = 0;
508488
....@@ -567,8 +547,8 @@
567547 reg_e9c = phy_query_bb_reg(adapt, rTx_Power_After_IQK_A, bMaskDWord);
568548
569549 if (!(reg_eac & BIT(28)) &&
570
- (((reg_e94 & 0x03FF0000)>>16) != 0x142) &&
571
- (((reg_e9c & 0x03FF0000)>>16) != 0x42))
550
+ (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
551
+ (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
572552 result |= 0x01;
573553 return result;
574554 }
....@@ -619,13 +599,13 @@
619599 reg_e9c = phy_query_bb_reg(adapt, rTx_Power_After_IQK_A, bMaskDWord);
620600
621601 if (!(reg_eac & BIT(28)) &&
622
- (((reg_e94 & 0x03FF0000)>>16) != 0x142) &&
623
- (((reg_e9c & 0x03FF0000)>>16) != 0x42))
602
+ (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
603
+ (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
624604 result |= 0x01;
625605 else /* if Tx not OK, ignore Rx */
626606 return result;
627607
628
- u4tmp = 0x80007C00 | (reg_e94&0x3FF0000) | ((reg_e9c&0x3FF0000) >> 16);
608
+ u4tmp = 0x80007C00 | (reg_e94 & 0x3FF0000) | ((reg_e9c & 0x3FF0000) >> 16);
629609 phy_set_bb_reg(adapt, rTx_IQK, bMaskDWord, u4tmp);
630610
631611 /* 1 RX IQK */
....@@ -667,8 +647,8 @@
667647 phy_set_rf_reg(adapt, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180);
668648
669649 if (!(reg_eac & BIT(27)) && /* if Tx is OK, check whether Rx is OK */
670
- (((reg_ea4 & 0x03FF0000)>>16) != 0x132) &&
671
- (((reg_eac & 0x03FF0000)>>16) != 0x36))
650
+ (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) &&
651
+ (((reg_eac & 0x03FF0000) >> 16) != 0x36))
672652 result |= 0x02;
673653 else
674654 ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
....@@ -696,15 +676,15 @@
696676 regecc = phy_query_bb_reg(adapt, rRx_Power_After_IQK_B_2, bMaskDWord);
697677
698678 if (!(regeac & BIT(31)) &&
699
- (((regeb4 & 0x03FF0000)>>16) != 0x142) &&
700
- (((regebc & 0x03FF0000)>>16) != 0x42))
679
+ (((regeb4 & 0x03FF0000) >> 16) != 0x142) &&
680
+ (((regebc & 0x03FF0000) >> 16) != 0x42))
701681 result |= 0x01;
702682 else
703683 return result;
704684
705685 if (!(regeac & BIT(30)) &&
706
- (((regec4 & 0x03FF0000)>>16) != 0x132) &&
707
- (((regecc & 0x03FF0000)>>16) != 0x36))
686
+ (((regec4 & 0x03FF0000) >> 16) != 0x132) &&
687
+ (((regecc & 0x03FF0000) >> 16) != 0x36))
708688 result |= 0x02;
709689 else
710690 ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION,
....@@ -730,7 +710,7 @@
730710 tx0_a = (x * oldval_0) >> 8;
731711 phy_set_bb_reg(adapt, rOFDM0_XATxIQImbalance, 0x3FF, tx0_a);
732712 phy_set_bb_reg(adapt, rOFDM0_ECCAThreshold, BIT(31),
733
- ((x * oldval_0>>7) & 0x1));
713
+ ((x * oldval_0 >> 7) & 0x1));
734714
735715 y = result[final_candidate][1];
736716 if ((y & 0x00000200) != 0)
....@@ -738,11 +718,11 @@
738718
739719 tx0_c = (y * oldval_0) >> 8;
740720 phy_set_bb_reg(adapt, rOFDM0_XCTxAFE, 0xF0000000,
741
- ((tx0_c&0x3C0)>>6));
721
+ ((tx0_c & 0x3C0) >> 6));
742722 phy_set_bb_reg(adapt, rOFDM0_XATxIQImbalance, 0x003F0000,
743
- (tx0_c&0x3F));
723
+ (tx0_c & 0x3F));
744724 phy_set_bb_reg(adapt, rOFDM0_ECCAThreshold, BIT(29),
745
- ((y * oldval_0>>7) & 0x1));
725
+ ((y * oldval_0 >> 7) & 0x1));
746726
747727 if (txonly)
748728 return;
....@@ -776,7 +756,7 @@
776756 phy_set_bb_reg(adapt, rOFDM0_XBTxIQImbalance, 0x3FF, tx1_a);
777757
778758 phy_set_bb_reg(adapt, rOFDM0_ECCAThreshold, BIT(27),
779
- ((x * oldval_1>>7) & 0x1));
759
+ ((x * oldval_1 >> 7) & 0x1));
780760
781761 y = result[final_candidate][5];
782762 if ((y & 0x00000200) != 0)
....@@ -785,11 +765,11 @@
785765 tx1_c = (y * oldval_1) >> 8;
786766
787767 phy_set_bb_reg(adapt, rOFDM0_XDTxAFE, 0xF0000000,
788
- ((tx1_c&0x3C0)>>6));
768
+ ((tx1_c & 0x3C0) >> 6));
789769 phy_set_bb_reg(adapt, rOFDM0_XBTxIQImbalance, 0x003F0000,
790
- (tx1_c&0x3F));
770
+ (tx1_c & 0x3F));
791771 phy_set_bb_reg(adapt, rOFDM0_ECCAThreshold, BIT(25),
792
- ((y * oldval_1>>7) & 0x1));
772
+ ((y * oldval_1 >> 7) & 0x1));
793773
794774 if (txonly)
795775 return;
....@@ -805,7 +785,7 @@
805785 }
806786 }
807787
808
-static void save_adda_registers(struct adapter *adapt, u32 *addareg,
788
+static void save_adda_registers(struct adapter *adapt, const u32 *addareg,
809789 u32 *backup, u32 register_num)
810790 {
811791 u32 i;
....@@ -814,7 +794,7 @@
814794 backup[i] = phy_query_bb_reg(adapt, addareg[i], bMaskDWord);
815795 }
816796
817
-static void save_mac_registers(struct adapter *adapt, u32 *mac_reg,
797
+static void save_mac_registers(struct adapter *adapt, const u32 *mac_reg,
818798 u32 *backup)
819799 {
820800 u32 i;
....@@ -825,7 +805,7 @@
825805 backup[i] = usb_read32(adapt, mac_reg[i]);
826806 }
827807
828
-static void reload_adda_reg(struct adapter *adapt, u32 *adda_reg,
808
+static void reload_adda_reg(struct adapter *adapt, const u32 *adda_reg,
829809 u32 *backup, u32 regiester_num)
830810 {
831811 u32 i;
....@@ -834,8 +814,8 @@
834814 phy_set_bb_reg(adapt, adda_reg[i], bMaskDWord, backup[i]);
835815 }
836816
837
-static void reload_mac_registers(struct adapter *adapt,
838
- u32 *mac_reg, u32 *backup)
817
+static void reload_mac_registers(struct adapter *adapt, const u32 *mac_reg,
818
+ u32 *backup)
839819 {
840820 u32 i;
841821
....@@ -845,7 +825,7 @@
845825 usb_write32(adapt, mac_reg[i], backup[i]);
846826 }
847827
848
-static void path_adda_on(struct adapter *adapt, u32 *adda_reg,
828
+static void path_adda_on(struct adapter *adapt, const u32 *adda_reg,
849829 bool is_path_a_on, bool is2t)
850830 {
851831 u32 path_on;
....@@ -863,16 +843,17 @@
863843 phy_set_bb_reg(adapt, adda_reg[i], bMaskDWord, path_on);
864844 }
865845
866
-static void mac_setting_calibration(struct adapter *adapt, u32 *mac_reg, u32 *backup)
846
+static void mac_setting_calibration(struct adapter *adapt, const u32 *mac_reg,
847
+ u32 *backup)
867848 {
868849 u32 i = 0;
869850
870851 usb_write8(adapt, mac_reg[i], 0x3F);
871852
872853 for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++)
873
- usb_write8(adapt, mac_reg[i], (u8)(backup[i]&(~BIT(3))));
854
+ usb_write8(adapt, mac_reg[i], (u8)(backup[i] & (~BIT(3))));
874855
875
- usb_write8(adapt, mac_reg[i], (u8)(backup[i]&(~BIT(5))));
856
+ usb_write8(adapt, mac_reg[i], (u8)(backup[i] & (~BIT(5))));
876857 }
877858
878859 static void path_a_standby(struct adapter *adapt)
....@@ -921,48 +902,48 @@
921902
922903 if (diff > MAX_TOLERANCE) {
923904 if ((i == 2 || i == 6) && !sim_bitmap) {
924
- if (resulta[c1][i] + resulta[c1][i+1] == 0)
925
- final_candidate[(i/4)] = c2;
926
- else if (resulta[c2][i] + resulta[c2][i+1] == 0)
927
- final_candidate[(i/4)] = c1;
905
+ if (resulta[c1][i] + resulta[c1][i + 1] == 0)
906
+ final_candidate[(i / 4)] = c2;
907
+ else if (resulta[c2][i] + resulta[c2][i + 1] == 0)
908
+ final_candidate[(i / 4)] = c1;
928909 else
929
- sim_bitmap = sim_bitmap | (1<<i);
910
+ sim_bitmap = sim_bitmap | (1 << i);
930911 } else {
931
- sim_bitmap = sim_bitmap | (1<<i);
912
+ sim_bitmap = sim_bitmap | (1 << i);
932913 }
933914 }
934915 }
935916
936917 if (sim_bitmap == 0) {
937
- for (i = 0; i < (bound/4); i++) {
918
+ for (i = 0; i < (bound / 4); i++) {
938919 if (final_candidate[i] != 0xFF) {
939
- for (j = i*4; j < (i+1)*4-2; j++)
920
+ for (j = i * 4; j < (i + 1) * 4 - 2; j++)
940921 resulta[3][j] = resulta[final_candidate[i]][j];
941922 result = false;
942923 }
943924 }
944925 return result;
945
- } else {
946
- if (!(sim_bitmap & 0x03)) { /* path A TX OK */
947
- for (i = 0; i < 2; i++)
948
- resulta[3][i] = resulta[c1][i];
949
- }
950
- if (!(sim_bitmap & 0x0c)) { /* path A RX OK */
951
- for (i = 2; i < 4; i++)
952
- resulta[3][i] = resulta[c1][i];
953
- }
954
-
955
- if (!(sim_bitmap & 0x30)) { /* path B TX OK */
956
- for (i = 4; i < 6; i++)
957
- resulta[3][i] = resulta[c1][i];
958
- }
959
-
960
- if (!(sim_bitmap & 0xc0)) { /* path B RX OK */
961
- for (i = 6; i < 8; i++)
962
- resulta[3][i] = resulta[c1][i];
963
- }
964
- return false;
965926 }
927
+
928
+ if (!(sim_bitmap & 0x03)) { /* path A TX OK */
929
+ for (i = 0; i < 2; i++)
930
+ resulta[3][i] = resulta[c1][i];
931
+ }
932
+ if (!(sim_bitmap & 0x0c)) { /* path A RX OK */
933
+ for (i = 2; i < 4; i++)
934
+ resulta[3][i] = resulta[c1][i];
935
+ }
936
+
937
+ if (!(sim_bitmap & 0x30)) { /* path B TX OK */
938
+ for (i = 4; i < 6; i++)
939
+ resulta[3][i] = resulta[c1][i];
940
+ }
941
+
942
+ if (!(sim_bitmap & 0xc0)) { /* path B RX OK */
943
+ for (i = 6; i < 8; i++)
944
+ resulta[3][i] = resulta[c1][i];
945
+ }
946
+ return false;
966947 }
967948
968949 static void phy_iq_calibrate(struct adapter *adapt, s32 result[][8],
....@@ -971,30 +952,31 @@
971952 struct odm_dm_struct *dm_odm = &adapt->HalData->odmpriv;
972953 u32 i;
973954 u8 path_a_ok, path_b_ok;
974
- u32 adda_reg[IQK_ADDA_REG_NUM] = {
975
- rFPGA0_XCD_SwitchControl, rBlue_Tooth,
976
- rRx_Wait_CCA, rTx_CCK_RFON,
977
- rTx_CCK_BBON, rTx_OFDM_RFON,
978
- rTx_OFDM_BBON, rTx_To_Rx,
979
- rTx_To_Tx, rRx_CCK,
980
- rRx_OFDM, rRx_Wait_RIFS,
981
- rRx_TO_Rx, rStandby,
982
- rSleep, rPMPD_ANAEN};
983
-
984
- u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
985
- REG_TXPAUSE, REG_BCN_CTRL,
986
- REG_BCN_CTRL_1, REG_GPIO_MUXCFG};
987
-
955
+ static const u32 adda_reg[IQK_ADDA_REG_NUM] = {
956
+ rFPGA0_XCD_SwitchControl, rBlue_Tooth,
957
+ rRx_Wait_CCA, rTx_CCK_RFON,
958
+ rTx_CCK_BBON, rTx_OFDM_RFON,
959
+ rTx_OFDM_BBON, rTx_To_Rx,
960
+ rTx_To_Tx, rRx_CCK,
961
+ rRx_OFDM, rRx_Wait_RIFS,
962
+ rRx_TO_Rx, rStandby,
963
+ rSleep, rPMPD_ANAEN
964
+ };
965
+ static const u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
966
+ REG_TXPAUSE, REG_BCN_CTRL,
967
+ REG_BCN_CTRL_1, REG_GPIO_MUXCFG
968
+ };
988969 /* since 92C & 92D have the different define in IQK_BB_REG */
989
- u32 iqk_bb_reg_92c[IQK_BB_REG_NUM] = {
990
- rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar,
991
- rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB,
992
- rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE,
993
- rFPGA0_XB_RFInterfaceOE, rFPGA0_RFMOD};
970
+ static const u32 iqk_bb_reg_92c[IQK_BB_REG_NUM] = {
971
+ rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar,
972
+ rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB,
973
+ rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE,
974
+ rFPGA0_XB_RFInterfaceOE, rFPGA0_RFMOD
975
+ };
994976
995977 u32 retry_count = 9;
996978
997
- if (*(dm_odm->mp_mode) == 1)
979
+ if (*dm_odm->mp_mode == 1)
998980 retry_count = 9;
999981 else
1000982 retry_count = 2;
....@@ -1056,10 +1038,10 @@
10561038 for (i = 0; i < retry_count; i++) {
10571039 path_a_ok = phy_path_a_iqk(adapt, is2t);
10581040 if (path_a_ok == 0x01) {
1059
- result[t][0] = (phy_query_bb_reg(adapt, rTx_Power_Before_IQK_A,
1060
- bMaskDWord)&0x3FF0000)>>16;
1061
- result[t][1] = (phy_query_bb_reg(adapt, rTx_Power_After_IQK_A,
1062
- bMaskDWord)&0x3FF0000)>>16;
1041
+ result[t][0] = (phy_query_bb_reg(adapt, rTx_Power_Before_IQK_A,
1042
+ bMaskDWord) & 0x3FF0000) >> 16;
1043
+ result[t][1] = (phy_query_bb_reg(adapt, rTx_Power_After_IQK_A,
1044
+ bMaskDWord) & 0x3FF0000) >> 16;
10631045 break;
10641046 }
10651047 }
....@@ -1067,15 +1049,14 @@
10671049 for (i = 0; i < retry_count; i++) {
10681050 path_a_ok = phy_path_a_rx_iqk(adapt, is2t);
10691051 if (path_a_ok == 0x03) {
1070
- result[t][2] = (phy_query_bb_reg(adapt, rRx_Power_Before_IQK_A_2,
1071
- bMaskDWord)&0x3FF0000)>>16;
1072
- result[t][3] = (phy_query_bb_reg(adapt, rRx_Power_After_IQK_A_2,
1073
- bMaskDWord)&0x3FF0000)>>16;
1052
+ result[t][2] = (phy_query_bb_reg(adapt, rRx_Power_Before_IQK_A_2,
1053
+ bMaskDWord) & 0x3FF0000) >> 16;
1054
+ result[t][3] = (phy_query_bb_reg(adapt, rRx_Power_After_IQK_A_2,
1055
+ bMaskDWord) & 0x3FF0000) >> 16;
10741056 break;
1075
- } else {
1076
- ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
1077
- ("Path A Rx IQK Fail!!\n"));
10781057 }
1058
+ ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
1059
+ ("Path A Rx IQK Fail!!\n"));
10791060 }
10801061
10811062 if (path_a_ok == 0x00) {
....@@ -1093,19 +1074,19 @@
10931074 path_b_ok = phy_path_b_iqk(adapt);
10941075 if (path_b_ok == 0x03) {
10951076 result[t][4] = (phy_query_bb_reg(adapt, rTx_Power_Before_IQK_B,
1096
- bMaskDWord)&0x3FF0000)>>16;
1077
+ bMaskDWord) & 0x3FF0000) >> 16;
10971078 result[t][5] = (phy_query_bb_reg(adapt, rTx_Power_After_IQK_B,
1098
- bMaskDWord)&0x3FF0000)>>16;
1079
+ bMaskDWord) & 0x3FF0000) >> 16;
10991080 result[t][6] = (phy_query_bb_reg(adapt, rRx_Power_Before_IQK_B_2,
1100
- bMaskDWord)&0x3FF0000)>>16;
1081
+ bMaskDWord) & 0x3FF0000) >> 16;
11011082 result[t][7] = (phy_query_bb_reg(adapt, rRx_Power_After_IQK_B_2,
1102
- bMaskDWord)&0x3FF0000)>>16;
1083
+ bMaskDWord) & 0x3FF0000) >> 16;
11031084 break;
11041085 } else if (i == (retry_count - 1) && path_b_ok == 0x01) { /* Tx IQK OK */
11051086 result[t][4] = (phy_query_bb_reg(adapt, rTx_Power_Before_IQK_B,
1106
- bMaskDWord)&0x3FF0000)>>16;
1087
+ bMaskDWord) & 0x3FF0000) >> 16;
11071088 result[t][5] = (phy_query_bb_reg(adapt, rTx_Power_After_IQK_B,
1108
- bMaskDWord)&0x3FF0000)>>16;
1089
+ bMaskDWord) & 0x3FF0000) >> 16;
11091090 }
11101091 }
11111092
....@@ -1158,31 +1139,31 @@
11581139 /* Check continuous TX and Packet TX */
11591140 tmpreg = usb_read8(adapt, 0xd03);
11601141
1161
- if ((tmpreg&0x70) != 0)
1162
- usb_write8(adapt, 0xd03, tmpreg&0x8F);
1142
+ if ((tmpreg & 0x70) != 0)
1143
+ usb_write8(adapt, 0xd03, tmpreg & 0x8F);
11631144 else
11641145 usb_write8(adapt, REG_TXPAUSE, 0xFF);
11651146
1166
- if ((tmpreg&0x70) != 0) {
1147
+ if ((tmpreg & 0x70) != 0) {
11671148 /* 1. Read original RF mode */
11681149 /* Path-A */
11691150 rf_a_mode = rtw_hal_read_rfreg(adapt, RF_PATH_A, RF_AC,
1170
- bMask12Bits);
1151
+ bMask12Bits);
11711152
11721153 /* Path-B */
11731154 if (is2t)
11741155 rf_b_mode = rtw_hal_read_rfreg(adapt, RF_PATH_B, RF_AC,
1175
- bMask12Bits);
1156
+ bMask12Bits);
11761157
11771158 /* 2. Set RF mode = standby mode */
11781159 /* Path-A */
11791160 phy_set_rf_reg(adapt, RF_PATH_A, RF_AC, bMask12Bits,
1180
- (rf_a_mode&0x8FFFF)|0x10000);
1161
+ (rf_a_mode & 0x8FFFF) | 0x10000);
11811162
11821163 /* Path-B */
11831164 if (is2t)
11841165 phy_set_rf_reg(adapt, RF_PATH_B, RF_AC, bMask12Bits,
1185
- (rf_b_mode&0x8FFFF)|0x10000);
1166
+ (rf_b_mode & 0x8FFFF) | 0x10000);
11861167 }
11871168
11881169 /* 3. Read RF reg18 */
....@@ -1190,12 +1171,12 @@
11901171
11911172 /* 4. Set LC calibration begin bit15 */
11921173 phy_set_rf_reg(adapt, RF_PATH_A, RF_CHNLBW, bMask12Bits,
1193
- lc_cal|0x08000);
1174
+ lc_cal | 0x08000);
11941175
11951176 msleep(100);
11961177
11971178 /* Restore original situation */
1198
- if ((tmpreg&0x70) != 0) {
1179
+ if ((tmpreg & 0x70) != 0) {
11991180 /* Deal with continuous TX case */
12001181 /* Path-A */
12011182 usb_write8(adapt, 0xd03, tmpreg);
....@@ -1215,7 +1196,7 @@
12151196 {
12161197 struct odm_dm_struct *dm_odm = &adapt->HalData->odmpriv;
12171198 s32 result[4][8];
1218
- u8 i, final, chn_index;
1199
+ u8 i, final;
12191200 bool pathaok, pathbok;
12201201 s32 reg_e94, reg_e9c, reg_ea4, reg_eb4, reg_ebc, reg_ec4;
12211202 bool is12simular, is13simular, is23simular;
....@@ -1244,15 +1225,10 @@
12441225 return;
12451226 }
12461227
1247
- for (i = 0; i < 8; i++) {
1248
- result[0][i] = 0;
1249
- result[1][i] = 0;
1250
- result[2][i] = 0;
1251
- if ((i == 0) || (i == 2) || (i == 4) || (i == 6))
1252
- result[3][i] = 0x100;
1253
- else
1254
- result[3][i] = 0;
1255
- }
1228
+ memset(result, 0, sizeof(result));
1229
+ for (i = 0; i < 8; i += 2)
1230
+ result[3][i] = 0x100;
1231
+
12561232 final = 0xff;
12571233 pathaok = false;
12581234 pathbok = false;
....@@ -1324,12 +1300,10 @@
13241300 (reg_ec4 == 0));
13251301 }
13261302
1327
- chn_index = get_right_chnl_for_iqk(adapt->HalData->CurrentChannel);
1328
-
13291303 if (final < 4) {
13301304 for (i = 0; i < IQK_Matrix_REG_NUM; i++)
1331
- dm_odm->RFCalibrateInfo.IQKMatrixRegSetting[chn_index].Value[0][i] = result[final][i];
1332
- dm_odm->RFCalibrateInfo.IQKMatrixRegSetting[chn_index].bIQKDone = true;
1305
+ dm_odm->RFCalibrateInfo.IQKMatrixRegSetting[0].Value[0][i] = result[final][i];
1306
+ dm_odm->RFCalibrateInfo.IQKMatrixRegSetting[0].bIQKDone = true;
13331307 }
13341308
13351309 save_adda_registers(adapt, iqk_bb_reg_92c,
....@@ -1347,7 +1321,7 @@
13471321 if (singletone || carrier_sup)
13481322 return;
13491323
1350
- while (*(dm_odm->pbScanInProcess) && timecount < timeout) {
1324
+ while (*dm_odm->pbScanInProcess && timecount < timeout) {
13511325 mdelay(50);
13521326 timecount += 50;
13531327 }