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2024-05-10 23fa18eaa71266feff7ba8d83022d9e1cc83c65a 
 kernel/drivers/net/wireless/rockchip_wlan/cywdhd/bcmdhd/include/siutils.h
....@@ -1,16 +1,17 @@
1
-/* SPDX-License-Identifier: GPL-2.0 */
21 /*
32  * Misc utility routines for accessing the SOC Interconnects
43  * of Broadcom HNBU chips.
54  *
6
- * Copyright (C) 1999-2019, Broadcom Corporation
7
- * 
5
+ * Portions of this code are copyright (c) 2022 Cypress Semiconductor Corporation
6
+ *
7
+ * Copyright (C) 1999-2017, Broadcom Corporation
8
+ *
89  *      Unless you and Broadcom execute a separate written software license
910  * agreement governing use of this software, this software is licensed to you
1011  * under the terms of the GNU General Public License version 2 (the "GPL"),
1112  * available at http://www.broadcom.com/licenses/GPLv2.php, with the
1213  * following added to such license:
13
- * 
14
+ *
1415  *      As a special exception, the copyright holders of this software give you
1516  * permission to link this software with independent modules, and to copy and
1617  * distribute the resulting executable under terms of your choice, provided that
....@@ -18,7 +19,7 @@
1819  * the license of that module.  An independent module is a module which is not
1920  * derived from this software.  The special exception does not apply to any
2021  * modifications of the software.
21
- * 
22
+ *
2223  *      Notwithstanding the above, under no circumstances may you combine this
2324  * software in any way with any other Broadcom software provided under a license
2425  * other than the GPL, without Broadcom's express prior written consent.
....@@ -26,7 +27,7 @@
2627  *
2728  * <<Broadcom-WL-IPTag/Open:>>
2829  *
29
- * $Id: siutils.h 603826 2015-12-03 08:57:00Z $
30
+ * $Id: siutils.h 699906 2017-05-16 22:39:33Z $
3031  */
3132 
3233 #ifndef	_siutils_h_
....@@ -36,6 +37,28 @@
3637 #include "wlioctl.h"
3738 #endif /* SR_DEBUG */
3839 
40
+#define WARM_BOOT	0xA0B0C0D0
41
+
42
+#ifdef BCM_BACKPLANE_TIMEOUT
43
+
44
+#define SI_MAX_ERRLOG_SIZE	4
45
+typedef struct si_axi_error
46
+{
47
+	uint32 error;
48
+	uint32 coreid;
49
+	uint32 errlog_lo;
50
+	uint32 errlog_hi;
51
+	uint32 errlog_id;
52
+	uint32 errlog_flags;
53
+	uint32 errlog_status;
54
+} si_axi_error_t;
55
+
56
+typedef struct si_axi_error_info
57
+{
58
+	uint32 count;
59
+	si_axi_error_t axi_error[SI_MAX_ERRLOG_SIZE];
60
+} si_axi_error_info_t;
61
+#endif /* BCM_BACKPLANE_TIMEOUT */
3962 
4063 /**
4164  * Data structure to export all chip specific common variables
....@@ -58,6 +81,7 @@
5881 	uint	boardvendor;		/**< board vendor */
5982 	uint	boardflags;		/**< board flags */
6083 	uint	boardflags2;		/**< board flags2 */
84
+	uint	boardflags4;		/**< board flags4 */
6185 	uint	chip;			/**< chip number */
6286 	uint	chiprev;		/**< chip revision */
6387 	uint	chippkg;		/**< chip package option */
....@@ -65,13 +89,23 @@
6589 	bool	issim;			/**< chip is in simulation or emulation */
6690 	uint    socirev;		/**< SOC interconnect rev */
6791 	bool	pci_pr32414;
92
+	int	gcirev;			/**< gci core rev */
93
+	int	lpflags;		/**< low power flags */
94
+	uint32	enum_base;	/**< backplane address where the chipcommon core resides */
6895 
96
+#ifdef BCM_BACKPLANE_TIMEOUT
97
+	si_axi_error_info_t * err_info;
98
+#endif /* BCM_BACKPLANE_TIMEOUT */
99
+
100
+	bool	_multibp_enable;
101
+	bool	secureboot;
102
+	bool    chipidpresent;
69103 };
70104 
71105 /* for HIGH_ONLY driver, the si_t must be writable to allow states sync from BMAC to HIGH driver
72106  * for monolithic driver, it is readonly to prevent accident change
73107  */
74
-typedef const struct si_pub si_t;
108
+typedef struct si_pub si_t;
75109 
76110 /*
77111  * Many of the routines below take an 'sih' handle as their first arg.
....@@ -118,7 +152,22 @@
118152 #define PMU_RES		31
119153 #endif /* SR_DEBUG */
120154 
155
+/* "access" param defines for si_seci_access() below */
156
+#define SECI_ACCESS_STATUSMASK_SET	0
157
+#define SECI_ACCESS_INTRS			1
158
+#define SECI_ACCESS_UART_CTS		2
159
+#define SECI_ACCESS_UART_RTS		3
160
+#define SECI_ACCESS_UART_RXEMPTY	4
161
+#define SECI_ACCESS_UART_GETC		5
162
+#define SECI_ACCESS_UART_TXFULL		6
163
+#define SECI_ACCESS_UART_PUTC		7
164
+#define SECI_ACCESS_STATUSMASK_GET	8
165
+
166
+#if defined(BCMQT)
167
+#define	ISSIM_ENAB(sih)	TRUE
168
+#else
121169 #define	ISSIM_ENAB(sih)	FALSE
170
+#endif // endif
122171 
123172 #define INVALID_ADDR (~0)
124173 
....@@ -127,10 +176,14 @@
127176 #define PMUCTL_ENAB(sih)	(BCMPMUCTL)
128177 #else
129178 #define PMUCTL_ENAB(sih)	((sih)->cccaps & CC_CAP_PMU)
130
-#endif
179
+#endif // endif
131180 
181
+#if defined(BCMAOBENAB)
182
+#define AOB_ENAB(sih)  (BCMAOBENAB)
183
+#else
132184 #define AOB_ENAB(sih)	((sih)->ccrev >= 35 ? \
133185 			((sih)->cccaps_ext & CC_CAP_EXT_AOB_PRESENT) : 0)
186
+#endif /* BCMAOBENAB */
134187 
135188 /* chipcommon clock/power control (exclusive with PMU's) */
136189 #if defined(BCMPMUCTL) && BCMPMUCTL
....@@ -139,7 +192,7 @@
139192 #else
140193 #define CCCTL_ENAB(sih)		((sih)->cccaps & CC_CAP_PWR_CTL)
141194 #define CCPLL_ENAB(sih)		((sih)->cccaps & CC_CAP_PLL_MASK)
142
-#endif
195
+#endif // endif
143196 
144197 typedef void (*gci_gpio_handler_t)(uint32 stat, void *arg);
145198 
....@@ -151,8 +204,6 @@
151204 #define GPIO_CTRL_5_6_EN_MASK 0x60
152205 #define GPIO_CTRL_7_6_EN_MASK 0xC0
153206 #define GPIO_OUT_7_EN_MASK 0x80
154
-
155
-
156207 
157208 /* CR4 specific defines used by the host driver */
158209 #define SI_CR4_CAP			(0x04)
....@@ -166,19 +217,27 @@
166217 #define	ARMCR4_TCBANB_SHIFT	0
167218 
168219 #define	SICF_CPUHALT		(0x0020)
169
-#define	ARMCR4_BSZ_MASK		0x3f
170
-#define	ARMCR4_BSZ_MULT		8192
220
+#define	ARMCR4_BSZ_MASK		0x7f
221
+#define	ARMCR4_BUNITSZ_MASK	0x200
222
+#define	ARMCR4_BSZ_8K		8192
223
+#define	ARMCR4_BSZ_1K		1024
171224 #define	SI_BPIND_1BYTE		0x1
172225 #define	SI_BPIND_2BYTE		0x3
173226 #define	SI_BPIND_4BYTE		0xF
227
+
228
+#define GET_GCI_OFFSET(sih, gci_reg)	\
229
+	(AOB_ENAB(sih)? OFFSETOF(gciregs_t, gci_reg) : OFFSETOF(chipcregs_t, gci_reg))
230
+
231
+#define GET_GCI_CORE(sih)	\
232
+	(AOB_ENAB(sih)? si_findcoreidx(sih, GCI_CORE_ID, 0) : SI_CC_IDX)
233
+
174234 #include <osl_decl.h>
175235 /* === exported functions === */
176
-extern si_t *si_attach(uint pcidev, osl_t *osh, void *regs, uint bustype,
236
+extern si_t *si_attach(uint pcidev, osl_t *osh, volatile void *regs, uint bustype,
177237                        void *sdh, char **vars, uint *varsz);
178238 extern si_t *si_kattach(osl_t *osh);
179239 extern void si_detach(si_t *sih);
180
-extern bool si_pci_war16165(si_t *sih);
181
-extern void *
240
+extern volatile void *
182241 si_d11_switch_addrbase(si_t *sih, uint coreunit);
183242 extern uint si_corelist(si_t *sih, uint coreid[]);
184243 extern uint si_coreid(si_t *sih);
....@@ -189,40 +248,41 @@
189248 extern uint si_coreunit(si_t *sih);
190249 extern uint si_corevendor(si_t *sih);
191250 extern uint si_corerev(si_t *sih);
251
+extern uint si_corerev_minor(si_t *sih);
192252 extern void *si_osh(si_t *sih);
193253 extern void si_setosh(si_t *sih, osl_t *osh);
194
-extern uint si_backplane_access(si_t *sih, uint addr, uint size,
254
+extern int si_backplane_access(si_t *sih, uint addr, uint size,
195255 	uint *val, bool read);
196256 extern uint si_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val);
257
+extern uint si_corereg_writeonly(si_t *sih, uint coreidx, uint regoff, uint mask, uint val);
197258 extern uint si_pmu_corereg(si_t *sih, uint32 idx, uint regoff, uint mask, uint val);
198
-extern uint32 *si_corereg_addr(si_t *sih, uint coreidx, uint regoff);
199
-extern void *si_coreregs(si_t *sih);
259
+extern volatile uint32 *si_corereg_addr(si_t *sih, uint coreidx, uint regoff);
260
+extern volatile void *si_coreregs(si_t *sih);
200261 extern uint si_wrapperreg(si_t *sih, uint32 offset, uint32 mask, uint32 val);
201262 extern uint si_core_wrapperreg(si_t *sih, uint32 coreidx, uint32 offset, uint32 mask, uint32 val);
202263 extern void *si_wrapperregs(si_t *sih);
203264 extern uint32 si_core_cflags(si_t *sih, uint32 mask, uint32 val);
204265 extern void si_core_cflags_wo(si_t *sih, uint32 mask, uint32 val);
205266 extern uint32 si_core_sflags(si_t *sih, uint32 mask, uint32 val);
206
-extern void si_d11rsdb_core1_alt_reg_clk_dis(si_t *sih);
207
-extern void si_d11rsdb_core1_alt_reg_clk_en(si_t *sih);
267
+extern void si_commit(si_t *sih);
208268 extern bool si_iscoreup(si_t *sih);
209269 extern uint si_numcoreunits(si_t *sih, uint coreid);
210270 extern uint si_numd11coreunits(si_t *sih);
211271 extern uint si_findcoreidx(si_t *sih, uint coreid, uint coreunit);
212
-extern void *si_setcoreidx(si_t *sih, uint coreidx);
213
-extern void *si_setcore(si_t *sih, uint coreid, uint coreunit);
214
-extern void *si_switch_core(si_t *sih, uint coreid, uint *origidx, uint *intr_val);
272
+extern volatile void *si_setcoreidx(si_t *sih, uint coreidx);
273
+extern volatile void *si_setcore(si_t *sih, uint coreid, uint coreunit);
274
+extern uint32 si_oobr_baseaddr(si_t *sih, bool second);
275
+extern volatile void *si_switch_core(si_t *sih, uint coreid, uint *origidx, uint *intr_val);
215276 extern void si_restore_core(si_t *sih, uint coreid, uint intr_val);
216277 extern int si_numaddrspaces(si_t *sih);
217
-extern uint32 si_addrspace(si_t *sih, uint asidx);
218
-extern uint32 si_addrspacesize(si_t *sih, uint asidx);
278
+extern uint32 si_addrspace(si_t *sih, uint spidx, uint baidx);
279
+extern uint32 si_addrspacesize(si_t *sih, uint spidx, uint baidx);
219280 extern void si_coreaddrspaceX(si_t *sih, uint asidx, uint32 *addr, uint32 *size);
220281 extern int si_corebist(si_t *sih);
221282 extern void si_core_reset(si_t *sih, uint32 bits, uint32 resetbits);
222283 extern void si_core_disable(si_t *sih, uint32 bits);
223284 extern uint32 si_clock_rate(uint32 pll_type, uint32 n, uint32 m);
224285 extern uint si_chip_hostif(si_t *sih);
225
-extern bool si_read_pmu_autopll(si_t *sih);
226286 extern uint32 si_clock(si_t *sih);
227287 extern uint32 si_alp_clock(si_t *sih); /* returns [Hz] units */
228288 extern uint32 si_ilp_clock(si_t *sih); /* returns [Hz] units */
....@@ -240,6 +300,7 @@
240300 extern uint32 si_gpiotimerval(si_t *sih, uint32 mask, uint32 val);
241301 extern void si_btcgpiowar(si_t *sih);
242302 extern bool si_deviceremoved(si_t *sih);
303
+extern void si_set_device_removed(si_t *sih, bool status);
243304 extern uint32 si_sysmem_size(si_t *sih);
244305 extern uint32 si_socram_size(si_t *sih);
245306 extern uint32 si_socdevram_size(si_t *sih);
....@@ -253,13 +314,14 @@
253314 extern void si_watchdog(si_t *sih, uint ticks);
254315 extern void si_watchdog_ms(si_t *sih, uint32 ms);
255316 extern uint32 si_watchdog_msticks(void);
256
-extern void *si_gpiosetcore(si_t *sih);
317
+extern volatile void *si_gpiosetcore(si_t *sih);
257318 extern uint32 si_gpiocontrol(si_t *sih, uint32 mask, uint32 val, uint8 priority);
258319 extern uint32 si_gpioouten(si_t *sih, uint32 mask, uint32 val, uint8 priority);
259320 extern uint32 si_gpioout(si_t *sih, uint32 mask, uint32 val, uint8 priority);
260321 extern uint32 si_gpioin(si_t *sih);
261322 extern uint32 si_gpiointpolarity(si_t *sih, uint32 mask, uint32 val, uint8 priority);
262323 extern uint32 si_gpiointmask(si_t *sih, uint32 mask, uint32 val, uint8 priority);
324
+extern uint32 si_gpioeventintmask(si_t *sih, uint32 mask, uint32 val, uint8 priority);
263325 extern uint32 si_gpioled(si_t *sih, uint32 mask, uint32 val);
264326 extern uint32 si_gpioreserve(si_t *sih, uint32 gpio_num, uint8 priority);
265327 extern uint32 si_gpiorelease(si_t *sih, uint32 gpio_num, uint8 priority);
....@@ -269,16 +331,31 @@
269331 extern void si_gci_uart_init(si_t *sih, osl_t *osh, uint8 seci_mode);
270332 extern void si_gci_enable_gpio(si_t *sih, uint8 gpio, uint32 mask, uint32 value);
271333 extern uint8 si_gci_host_wake_gpio_init(si_t *sih);
334
+extern uint8 si_gci_time_sync_gpio_init(si_t *sih);
272335 extern void si_gci_host_wake_gpio_enable(si_t *sih, uint8 gpio, bool state);
336
+extern void si_gci_time_sync_gpio_enable(si_t *sih, uint8 gpio, bool state);
337
+
338
+extern void si_invalidate_second_bar0win(si_t *sih);
339
+
340
+extern void si_gci_shif_config_wake_pin(si_t *sih, uint8 gpio_n,
341
+		uint8 wake_events, bool gci_gpio);
342
+extern void si_shif_int_enable(si_t *sih, uint8 gpio_n, uint8 wake_events, bool enable);
273343 
274344 /* GCI interrupt handlers */
275345 extern void si_gci_handler_process(si_t *sih);
346
+
347
+extern void si_enable_gpio_wake(si_t *sih, uint8 *wake_mask, uint8 *cur_status, uint8 gci_gpio,
348
+	uint32 pmu_cc2_mask, uint32 pmu_cc2_value);
276349 
277350 /* GCI GPIO event handlers */
278351 extern void *si_gci_gpioint_handler_register(si_t *sih, uint8 gpio, uint8 sts,
279352 	gci_gpio_handler_t cb, void *arg);
280353 extern void si_gci_gpioint_handler_unregister(si_t *sih, void* gci_i);
354
+
281355 extern uint8 si_gci_gpio_status(si_t *sih, uint8 gci_gpio, uint8 mask, uint8 value);
356
+extern void si_gci_config_wake_pin(si_t *sih, uint8 gpio_n, uint8 wake_events,
357
+	bool gci_gpio);
358
+extern void si_gci_free_wake_pin(si_t *sih, uint8 gpio_n);
282359 
283360 /* Wake-on-wireless-LAN (WOWL) */
284361 extern bool si_pci_pmecap(si_t *sih);
....@@ -291,21 +368,25 @@
291368 extern uint si_pcie_writereg(void *sih, uint addrtype, uint offset, uint val);
292369 extern void si_deepsleep_count(si_t *sih, bool arm_wakeup);
293370 
294
-
295371 #ifdef BCMSDIO
296372 extern void si_sdio_init(si_t *sih);
297
-#endif
373
+extern void *si_get_sdio_addrbase(void *sdh);
374
+#endif // endif
298375 
299376 extern uint16 si_d11_devid(si_t *sih);
300377 extern int si_corepciid(si_t *sih, uint func, uint16 *pcivendor, uint16 *pcidevice,
301378 	uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif, uint8 *pciheader);
379
+
380
+extern uint32 si_seci_access(si_t *sih, uint32 val, int access);
381
+extern volatile void* si_seci_init(si_t *sih, uint8 seci_mode);
382
+extern void si_seci_clk_force(si_t *sih, bool val);
383
+extern bool si_seci_clk_force_status(si_t *sih);
302384 
303385 #define si_eci(sih) 0
304386 static INLINE void * si_eci_init(si_t *sih) {return NULL;}
305387 #define si_eci_notify_bt(sih, type, val)  (0)
306388 #define si_seci(sih) 0
307389 #define si_seci_upd(sih, a)	do {} while (0)
308
-static INLINE void * si_seci_init(si_t *sih, uint8 use_seci) {return NULL;}
309390 static INLINE void * si_gci_init(si_t *sih) {return NULL;}
310391 #define si_seci_down(sih) do {} while (0)
311392 #define si_gci(sih) 0
....@@ -317,8 +398,6 @@
317398 
318399 /* SPROM availability */
319400 extern bool si_is_sprom_available(si_t *sih);
320
-extern bool si_is_sprom_enabled(si_t *sih);
321
-extern void si_sprom_enable(si_t *sih, bool enable);
322401 
323402 /* OTP/SROM CIS stuff */
324403 extern int si_cis_source(si_t *sih);
....@@ -332,7 +411,6 @@
332411 #define	TSMC_FAB12	0x2	/**< TSMC Fab12/Fab14 chip */
333412 #define	SMIC_FAB4	0x3	/**< SMIC Fab4 chip */
334413 
335
-extern int si_otp_fabid(si_t *sih, uint16 *fabid, bool rw);
336414 extern uint16 si_fabid(si_t *sih);
337415 extern uint16 si_chipid(si_t *sih);
338416 
....@@ -347,7 +425,6 @@
347425 extern char *si_getdevpathvar(si_t *sih, const char *name);
348426 extern int si_getdevpathintvar(si_t *sih, const char *name);
349427 extern char *si_coded_devpathvar(si_t *sih, char *varname, int var_len, const char *name);
350
-
351428 
352429 extern uint8 si_pcieclkreq(si_t *sih, uint32 mask, uint32 val);
353430 extern uint32 si_pcielcreg(si_t *sih, uint32 mask, uint32 val);
....@@ -368,24 +445,14 @@
368445 extern void si_pcie_extendL1timer(si_t *sih, bool extend);
369446 extern int si_pci_fixcfg(si_t *sih);
370447 extern void si_chippkg_set(si_t *sih, uint);
448
+extern bool si_is_warmboot(void);
371449 
372
-extern void si_chipcontrl_btshd0_4331(si_t *sih, bool on);
373450 extern void si_chipcontrl_restore(si_t *sih, uint32 val);
374451 extern uint32 si_chipcontrl_read(si_t *sih);
375
-extern void si_chipcontrl_epa4331(si_t *sih, bool on);
376
-extern void si_chipcontrl_epa4331_wowl(si_t *sih, bool enter_wowl);
377452 extern void si_chipcontrl_srom4360(si_t *sih, bool on);
378
-extern void si_clk_srom4365(si_t *sih);
379
-/* Enable BT-COEX & Ex-PA for 4313 */
380
-extern void si_epa_4313war(si_t *sih);
453
+extern void si_srom_clk_set(si_t *sih); /**< for chips with fast BP clock */
381454 extern void si_btc_enable_chipcontrol(si_t *sih);
382
-/* BT/WL selection for 4313 bt combo >= P250 boards */
383
-extern void si_btcombo_p250_4313_war(si_t *sih);
384
-extern void si_btcombo_43228_war(si_t *sih);
385
-extern void si_clk_pmu_htavail_set(si_t *sih, bool set_clear);
386455 extern void si_pmu_avb_clk_set(si_t *sih, osl_t *osh, bool set_flag);
387
-extern void si_pmu_synth_pwrsw_4313_war(si_t *sih);
388
-extern uint si_pll_reset(si_t *sih);
389456 /* === debug routines === */
390457 
391458 extern bool si_taclear(si_t *sih, bool details);
....@@ -393,11 +460,13 @@
393460 #if defined(BCMDBG_PHYDUMP)
394461 struct bcmstrbuf;
395462 extern int si_dump_pcieinfo(si_t *sih, struct bcmstrbuf *b);
396
-#endif 
463
+extern void si_dump_pmuregs(si_t *sih, struct bcmstrbuf *b);
464
+extern int si_dump_pcieregs(si_t *sih, struct bcmstrbuf *b);
465
+#endif // endif
397466 
398467 #if defined(BCMDBG_PHYDUMP)
399468 extern void si_dumpregs(si_t *sih, struct bcmstrbuf *b);
400
-#endif 
469
+#endif // endif
401470 
402471 extern uint32 si_ccreg(si_t *sih, uint32 offset, uint32 mask, uint32 val);
403472 extern uint32 si_pciereg(si_t *sih, uint32 offset, uint32 mask, uint32 val, uint type);
....@@ -421,8 +490,12 @@
421490 extern int si_pcie_configspace_restore(si_t *sih);
422491 extern int si_pcie_configspace_get(si_t *sih, uint8 *buf, uint size);
423492 
424
-char *si_getnvramflvar(si_t *sih, const char *name);
493
+#ifdef BCM_BACKPLANE_TIMEOUT
494
+extern const si_axi_error_info_t * si_get_axi_errlog_info(si_t *sih);
495
+extern void si_reset_axi_errlog_info(si_t * sih);
496
+#endif /* BCM_BACKPLANE_TIMEOUT */
425497 
498
+extern void si_update_backplane_timeouts(si_t *sih, bool enable, uint32 timeout, uint32 cid);
426499 
427500 extern uint32 si_tcm_size(si_t *sih);
428501 extern bool si_has_flops(si_t *sih);
....@@ -437,27 +510,27 @@
437510 extern uint32 si_gci_int_enable(si_t *sih, bool enable);
438511 extern void si_gci_reset(si_t *sih);
439512 #ifdef BCMLTECOEX
440
-extern void si_gci_seci_init(si_t *sih);
441513 extern void si_ercx_init(si_t *sih, uint32 ltecx_mux, uint32 ltecx_padnum,
442514 	uint32 ltecx_fnsel, uint32 ltecx_gcigpio);
443
-extern void si_wci2_init(si_t *sih, uint8 baudrate, uint32 ltecx_mux, uint32 ltecx_padnum,
444
-	uint32 ltecx_fnsel, uint32 ltecx_gcigpio);
445515 #endif /* BCMLTECOEX */
516
+extern void si_gci_seci_init(si_t *sih);
517
+extern void si_wci2_init(si_t *sih, uint8 baudrate, uint32 ltecx_mux, uint32 ltecx_padnum,
518
+	uint32 ltecx_fnsel, uint32 ltecx_gcigpio, uint32 xtalfreq);
519
+
520
+extern bool si_btcx_wci2_init(si_t *sih);
521
+
446522 extern void si_gci_set_functionsel(si_t *sih, uint32 pin, uint8 fnsel);
447523 extern uint32 si_gci_get_functionsel(si_t *sih, uint32 pin);
448524 extern void si_gci_clear_functionsel(si_t *sih, uint8 fnsel);
449525 extern uint8 si_gci_get_chipctrlreg_idx(uint32 pin, uint32 *regidx, uint32 *pos);
450526 extern uint32 si_gci_chipcontrol(si_t *sih, uint reg, uint32 mask, uint32 val);
451527 extern uint32 si_gci_chipstatus(si_t *sih, uint reg);
452
-extern uint16 si_cc_get_reg16(uint32 reg_offs);
453
-extern uint32 si_cc_get_reg32(uint32 reg_offs);
454
-extern uint32 si_cc_set_reg32(uint32 reg_offs, uint32 val);
455
-extern uint32 si_gci_preinit_upd_indirect(uint32 regidx, uint32 setval, uint32 mask);
456528 extern uint8 si_enable_device_wake(si_t *sih, uint8 *wake_status, uint8 *cur_status);
529
+extern uint8 si_get_device_wake_opt(si_t *sih);
457530 extern void si_swdenable(si_t *sih, uint32 swdflag);
531
+extern uint8 si_enable_perst_wake(si_t *sih, uint8 *perst_wake_mask, uint8 *perst_cur_status);
458532 
459533 extern uint32 si_get_pmu_reg_addr(si_t *sih, uint32 offset);
460
-
461534 #define CHIPCTRLREG1 0x1
462535 #define CHIPCTRLREG2 0x2
463536 #define CHIPCTRLREG3 0x3
....@@ -475,7 +548,6 @@
475548 void si_force_islanding(si_t *sih, bool enable);
476549 extern uint32 si_pmu_res_req_timer_clr(si_t *sih);
477550 extern void si_pmu_rfldo(si_t *sih, bool on);
478
-extern void si_survive_perst_war(si_t *sih, bool reset, uint32 sperst_mask, uint32 spert_val);
479551 extern uint32 si_pcie_set_ctrlreg(si_t *sih, uint32 sperst_mask, uint32 spert_val);
480552 extern void si_pcie_ltr_war(si_t *sih);
481553 extern void si_pcie_hw_LTR_war(si_t *sih);
....@@ -483,21 +555,25 @@
483555 extern void si_pciedev_crwlpciegen2(si_t *sih);
484556 extern void si_pcie_prep_D3(si_t *sih, bool enter_D3);
485557 extern void si_pciedev_reg_pm_clk_period(si_t *sih);
558
+extern void si_d11rsdb_core1_alt_reg_clk_dis(si_t *sih);
559
+extern void si_d11rsdb_core1_alt_reg_clk_en(si_t *sih);
560
+extern void si_pcie_disable_oobselltr(si_t *sih);
561
+extern uint32 si_raw_reg(si_t *sih, uint32 reg, uint32 val, uint32 wrire_req);
486562 
487563 #ifdef WLRSDB
488564 extern void si_d11rsdb_core_disable(si_t *sih, uint32 bits);
489565 extern void si_d11rsdb_core_reset(si_t *sih, uint32 bits, uint32 resetbits);
490
-#endif
491
-
566
+extern void set_secondary_d11_core(si_t *sih, volatile void **secmap, volatile void **secwrap);
567
+#endif // endif
492568 
493569 /* Macro to enable clock gating changes in different cores */
494
-#define MEM_CLK_GATE_BIT 	5
495
-#define GCI_CLK_GATE_BIT 	18
570
+#define MEM_CLK_GATE_BIT	5
571
+#define GCI_CLK_GATE_BIT	18
496572 
497573 #define USBAPP_CLK_BIT		0
498574 #define PCIE_CLK_BIT		3
499575 #define ARMCR4_DBG_CLK_BIT	4
500
-#define SAMPLE_SYNC_CLK_BIT 	17
576
+#define SAMPLE_SYNC_CLK_BIT	17
501577 #define PCIE_TL_CLK_BIT		18
502578 #define HQ_REQ_BIT		24
503579 #define PLL_DIV2_BIT_START	9
....@@ -521,11 +597,21 @@
521597 			OFFSETOF(pmuregs_t, member), mask, val): \
522598 		si_corereg(si, SI_CC_IDX, OFFSETOF(chipcregs_t, member), mask, val))
523599 
600
+/* Used only for the regs present in the pmu core and not present in the old cc core */
601
+#define PMU_REG_NEW(si, member, mask, val) \
602
+		si_corereg(si, si_findcoreidx(si, PMU_CORE_ID, 0), \
603
+			OFFSETOF(pmuregs_t, member), mask, val)
604
+
524605 #define GCI_REG(si, offset, mask, val) \
525
-	(AOB_ENAB(si) ? \
606
+		(AOB_ENAB(si) ? \
607
+			si_corereg(si, si_findcoreidx(si, GCI_CORE_ID, 0), \
608
+				offset, mask, val): \
609
+			si_corereg(si, SI_CC_IDX, offset, mask, val))
610
+
611
+/* Used only for the regs present in the gci core and not present in the old cc core */
612
+#define GCI_REG_NEW(si, member, mask, val) \
526613 		si_corereg(si, si_findcoreidx(si, GCI_CORE_ID, 0), \
527
-			offset, mask, val): \
528
-		si_corereg(si, SI_CC_IDX, offset, mask, val))
614
+			OFFSETOF(gciregs_t, member), mask, val)
529615 
530616 #define LHL_REG(si, member, mask, val) \
531617 		si_corereg(si, si_findcoreidx(si, GCI_CORE_ID, 0), \
....@@ -553,6 +639,7 @@
553639 #define GCI_CCTL_FGCA_OFFSET			20 /**< ForceGciClkAvail */
554640 #define GCI_CCTL_FGCAV_OFFSET			21 /**< ForceGciClkAvailValue */
555641 #define GCI_CCTL_SCS_OFFSET			24 /**< SeciClkStretch, 31:24 */
642
+#define GCI_CCTL_SCS				25 /* SeciClkStretch */
556643 
557644 #define GCI_MODE_UART				0x0
558645 #define GCI_MODE_SECI				0x1
....@@ -573,9 +660,19 @@
573660 #define GCI_SECIIN_GCIGPIO_OFFSET		4
574661 #define GCI_SECIIN_RXID2IP_OFFSET		8
575662 
663
+#define GCI_SECIIN_MODE_MASK                    0x7
664
+#define GCI_SECIIN_GCIGPIO_MASK                 0xF
665
+
576666 #define GCI_SECIOUT_MODE_OFFSET			0
577667 #define GCI_SECIOUT_GCIGPIO_OFFSET		4
668
+#define	GCI_SECIOUT_LOOPBACK_OFFSET		8
578669 #define GCI_SECIOUT_SECIINRELATED_OFFSET	16
670
+
671
+#define GCI_SECIOUT_MODE_MASK                   0x7
672
+#define GCI_SECIOUT_GCIGPIO_MASK                0xF
673
+#define GCI_SECIOUT_SECIINRELATED_MASK          0x1
674
+
675
+#define GCI_SECIOUT_SECIINRELATED               0x1
579676 
580677 #define GCI_SECIAUX_RXENABLE_OFFSET		0
581678 #define GCI_SECIFIFO_RXENABLE_OFFSET		16
....@@ -589,15 +686,41 @@
589686 #define GCI_GPIOIDX_OFFSET			16
590687 
591688 #define GCI_LTECX_SECI_ID			0 /**< SECI port for LTECX */
689
+#define GCI_LTECX_TXCONF_EN_OFFSET		2
690
+#define GCI_LTECX_PRISEL_EN_OFFSET		3
592691 
593692 /* To access per GCI bit registers */
594693 #define GCI_REG_WIDTH				32
694
+
695
+/* number of event summary bits */
696
+#define GCI_EVENT_NUM_BITS			32
697
+
698
+/* gci event bits per core */
699
+#define GCI_EVENT_BITS_PER_CORE	4
700
+#define GCI_EVENT_HWBIT_1			1
701
+#define GCI_EVENT_HWBIT_2			2
702
+#define GCI_EVENT_SWBIT_1			3
703
+#define GCI_EVENT_SWBIT_2			4
704
+
705
+#define GCI_MBDATA_TOWLAN_POS	96
706
+#define GCI_MBACK_TOWLAN_POS	104
707
+#define GCI_WAKE_TOWLAN_PO		112
708
+#define GCI_SWREADY_POS			120
595709 
596710 /* GCI bit positions */
597711 /* GCI [127:000] = WLAN [127:0] */
598712 #define GCI_WLAN_IP_ID				0
599713 #define GCI_WLAN_BEGIN				0
600714 #define GCI_WLAN_PRIO_POS			(GCI_WLAN_BEGIN + 4)
715
+#define GCI_WLAN_PERST_POS			(GCI_WLAN_BEGIN + 15)
716
+
717
+/* GCI [255:128] = BT [127:0] */
718
+#define GCI_BT_IP_ID					1
719
+#define GCI_BT_BEGIN					128
720
+#define GCI_BT_MBDATA_TOWLAN_POS	(GCI_BT_BEGIN + GCI_MBDATA_TOWLAN_POS)
721
+#define GCI_BT_MBACK_TOWLAN_POS	(GCI_BT_BEGIN + GCI_MBACK_TOWLAN_POS)
722
+#define GCI_BT_WAKE_TOWLAN_POS	(GCI_BT_BEGIN + GCI_WAKE_TOWLAN_PO)
723
+#define GCI_BT_SWREADY_POS			(GCI_BT_BEGIN + GCI_SWREADY_POS)
601724 
602725 /* GCI [639:512] = LTE [127:0] */
603726 #define GCI_LTE_IP_ID				4
....@@ -605,6 +728,8 @@
605728 #define GCI_LTE_FRAMESYNC_POS			(GCI_LTE_BEGIN + 0)
606729 #define GCI_LTE_RX_POS				(GCI_LTE_BEGIN + 1)
607730 #define GCI_LTE_TX_POS				(GCI_LTE_BEGIN + 2)
731
+#define GCI_LTE_WCI2TYPE_POS			(GCI_LTE_BEGIN + 48)
732
+#define GCI_LTE_WCI2TYPE_MASK			7
608733 #define GCI_LTE_AUXRXDVALID_POS			(GCI_LTE_BEGIN + 56)
609734 
610735 /* Reg Index corresponding to ECI bit no x of ECI space */
....@@ -612,19 +737,88 @@
612737 /* Bit offset of ECI bit no x in 32-bit words */
613738 #define GCI_BITOFFSET(x)			((x)%GCI_REG_WIDTH)
614739 
740
+/* BT SMEM Control Register 0 */
741
+#define GCI_BT_SMEM_CTRL0_SUBCORE_ENABLE_PKILL	(1 << 28)
742
+
615743 /* End - GCI Macros */
616744 
617
-#ifdef REROUTE_OOBINT
618
-#define CC_OOB          0x0
619
-#define M2MDMA_OOB      0x1
620
-#define PMU_OOB         0x2
621
-#define D11_OOB         0x3
622
-#define SDIOD_OOB       0x4
623
-#define WLAN_OOB	0x5
624
-#define PMU_OOB_BIT     0x12
625
-#endif /* REROUTE_OOBINT */
745
+#define AXI_OOB		0x7
626746 
627747 extern void si_pll_sr_reinit(si_t *sih);
628748 extern void si_pll_closeloop(si_t *sih);
749
+void si_config_4364_d11_oob(si_t *sih, uint coreid);
750
+extern void si_gci_set_femctrl(si_t *sih, osl_t *osh, bool set);
751
+extern void si_gci_set_femctrl_mask_ant01(si_t *sih, osl_t *osh, bool set);
752
+extern uint si_num_slaveports(si_t *sih, uint coreid);
753
+extern uint32 si_get_slaveport_addr(si_t *sih, uint spidx, uint baidx,
754
+	uint core_id, uint coreunit);
755
+extern uint32 si_get_d11_slaveport_addr(si_t *sih, uint spidx,
756
+	uint baidx, uint coreunit);
757
+uint si_introff(si_t *sih);
758
+void si_intrrestore(si_t *sih, uint intr_val);
759
+void si_nvram_res_masks(si_t *sih, uint32 *min_mask, uint32 *max_mask);
760
+extern uint32 si_xtalfreq(si_t *sih);
761
+extern uint8 si_getspurmode(si_t *sih);
762
+extern uint32 si_get_openloop_dco_code(si_t *sih);
763
+extern void si_set_openloop_dco_code(si_t *sih, uint32 openloop_dco_code);
764
+extern uint32 si_wrapper_dump_buf_size(si_t *sih);
765
+extern uint32 si_wrapper_dump_binary(si_t *sih, uchar *p);
766
+extern uint32 si_wrapper_dump_last_timeout(si_t *sih, uint32 *error, uint32 *core, uint32 *ba,
767
+	uchar *p);
768
+
769
+/* SR Power Control */
770
+extern uint32 si_srpwr_request(si_t *sih, uint32 mask, uint32 val);
771
+extern uint32 si_srpwr_stat_spinwait(si_t *sih, uint32 mask, uint32 val);
772
+extern uint32 si_srpwr_stat(si_t *sih);
773
+extern uint32 si_srpwr_domain(si_t *sih);
774
+extern uint32 si_srpwr_domain_all_mask(si_t *sih);
775
+
776
+/* SR Power Control */
777
+	/* No capabilities bit so using chipid for now */
778
+#define SRPWR_CAP(sih)  (BCM4347_CHIP(sih->chip) || BCM4369_CHIP(sih->chip))
779
+
780
+#ifdef BCMSRPWR
781
+	extern bool _bcmsrpwr;
782
+	#if defined(ROM_ENAB_RUNTIME_CHECK) || !defined(DONGLEBUILD)
783
+		#define SRPWR_ENAB()    (_bcmsrpwr)
784
+	#elif defined(BCMSRPWR_DISABLED)
785
+		#define SRPWR_ENAB()    (0)
786
+	#else
787
+		#define SRPWR_ENAB()    (1)
788
+	#endif
789
+#else
790
+	#define SRPWR_ENAB()            (0)
791
+#endif /* BCMSRPWR */
792
+
793
+/*
794
+ * Multi-BackPlane architecture.  Each can power up/down independently.
795
+ *   Common backplane: shared between BT and WL
796
+ *      ChipC, PCIe, GCI, PMU, SRs
797
+ *      HW powers up as needed
798
+ *   WL BackPlane (WLBP):
799
+ *      ARM, TCM, Main, Aux
800
+ *      Host needs to power up
801
+ */
802
+#ifdef CHIPS_CUSTOMER_HW6
803
+#define MULTIBP_CAP(sih)	(BCM4368_CHIP(sih->chip) || BCM4378_CHIP(sih->chip) || \
804
+				BCM4387_CHIP(sih->chip))
805
+#else /* !CHIPS_CUSTOMER_HW6 */
806
+#define MULTIBP_CAP(sih)	(FALSE)
807
+#endif /* CHIPS_CUSTOMER_HW6 */
808
+#define MULTIBP_ENAB(sih)      ((sih) && (sih)->_multibp_enable)
809
+
810
+uint32 si_enum_base(uint devid);
811
+uint32 si_pcie_enum_base(uint devid);
812
+
813
+extern uint8 si_lhl_ps_mode(si_t *sih);
814
+
815
+#ifdef UART_TRAP_DBG
816
+void ai_dump_APB_Bridge_registers(si_t *sih);
817
+#endif /* UART_TRAP_DBG */
818
+
819
+void si_clrirq_idx(si_t *sih, uint core_idx);
820
+
821
+/* return if scan core is present */
822
+bool si_scan_core_present(si_t *sih);
629823 
630824 #endif	/* _siutils_h_ */