disable pwm7

hc

2024-05-10 23fa18eaa71266feff7ba8d83022d9e1cc83c65a

 kernel/drivers/net/wireless/rockchip_wlan/cywdhd/bcmdhd/include/sbsdpcmdev.h
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@@ -1,16 +1,17 @@
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-/* SPDX-License-Identifier: GPL-2.0 */
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 /*
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  * Broadcom SiliconBackplane SDIO/PCMCIA hardware-specific
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  * device core support
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  *
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- * Copyright (C) 1999-2019, Broadcom Corporation
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- * 
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+ * Portions of this code are copyright (c) 2022 Cypress Semiconductor Corporation
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+ *
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+ * Copyright (C) 1999-2017, Broadcom Corporation
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+ *
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  *      Unless you and Broadcom execute a separate written software license
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  * agreement governing use of this software, this software is licensed to you
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  * under the terms of the GNU General Public License version 2 (the "GPL"),
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  * available at http://www.broadcom.com/licenses/GPLv2.php, with the
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  * following added to such license:
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- * 
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+ *
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  *      As a special exception, the copyright holders of this software give you
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  * permission to link this software with independent modules, and to copy and
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  * distribute the resulting executable under terms of your choice, provided that
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@@ -18,7 +19,7 @@
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  * the license of that module.  An independent module is a module which is not
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  * derived from this software.  The special exception does not apply to any
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  * modifications of the software.
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- * 
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+ *
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  *      Notwithstanding the above, under no circumstances may you combine this
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  * software in any way with any other Broadcom software provided under a license
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  * other than the GPL, without Broadcom's express prior written consent.
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@@ -26,7 +27,7 @@
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  *
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  * <<Broadcom-WL-IPTag/Open:>>
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  *
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- * $Id: sbsdpcmdev.h 514727 2014-11-12 03:02:48Z $
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+ * $Id: sbsdpcmdev.h 616398 2016-02-01 09:37:52Z $
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  */
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 #ifndef	_sbsdpcmdev_h_
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@@ -39,7 +40,6 @@
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 #define	PAD		_XSTR(__LINE__)
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 #endif	/* PAD */
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-
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 typedef volatile struct {
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 	dma64regs_t	xmt;		/* dma tx */
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 	uint32 PAD[2];
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@@ -51,21 +51,21 @@
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 typedef volatile struct {
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 	dma64p_t dma64regs[2];
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 	dma64diag_t dmafifo;		/* DMA Diagnostic Regs, 0x280-0x28c */
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-	uint32 PAD[92];
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+	uint32 PAD[28];
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 } sdiodma64_t;
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 /* dma32 sdiod corerev == 0 */
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 typedef volatile struct {
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 	dma32regp_t dma32regs[2];	/* dma tx & rx, 0x200-0x23c */
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 	dma32diag_t dmafifo;		/* DMA Diagnostic Regs, 0x240-0x24c */
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-	uint32 PAD[108];
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+	uint32 PAD[44];
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 } sdiodma32_t;
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 /* dma32 regs for pcmcia core */
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 typedef volatile struct {
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 	dma32regp_t dmaregs;		/* DMA Regs, 0x200-0x21c, rev8 */
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 	dma32diag_t dmafifo;		/* DMA Diagnostic Regs, 0x220-0x22c */
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-	uint32 PAD[116];
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+	uint32 PAD[52];
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 } pcmdma32_t;
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 /* core registers */
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@@ -100,7 +100,9 @@
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 	/* synchronized access to registers in SDIO clock domain */
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 	uint32 sdioaccess;		/* SdioAccess, 0x050, rev8   */
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-	uint32 PAD[3];
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+	uint32 PAD[1];
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+	uint32 MiscHostAccessIntEn;
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+	uint32 PAD[1];
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 	/* PCMCIA frame control */
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 	uint8 pcmciaframectrl;		/* pcmciaFrameCtrl, 0x060, rev8   */
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@@ -127,7 +129,9 @@
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 	uint32 writeterm;		/* WriteTermCount, 0x13c, rev8, SDIO: wr frm terminates */
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 	uint32 PAD[40];
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 	uint32 clockctlstatus;		/* ClockCtlStatus, 0x1e0, rev8 */
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-	uint32 PAD[7];
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+	uint32 PAD[1];
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+	uint32 powerctl;		/* 0x1e8 */
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+	uint32 PAD[5];
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 	/* DMA engines */
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 	volatile union {
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@@ -135,6 +139,11 @@
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 		sdiodma32_t sdiod32;
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 		sdiodma64_t sdiod64;
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 	} dma;
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+
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+	uint32 PAD[12];			/* 0x300-0x32c */
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+	uint32 chipid;			/* SDIO ChipID Register, 0x330, rev31 */
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+	uint32 eromptr;			/* SDIO EromPtrOffset Register, 0x334, rev31 */
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+	uint32 PAD[50];
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 	/* SDIO/PCMCIA CIS region */
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 	char cis[512];			/* 512 byte CIS, 0x400-0x5ff, rev6 */
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@@ -234,6 +243,7 @@
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 #define SDA_F1_FBR_SPACE	0x100	/* sdioAccess F1 FBR register space */
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 #define SDA_F2_FBR_SPACE	0x200	/* sdioAccess F2 FBR register space */
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 #define SDA_F1_REG_SPACE	0x300	/* sdioAccess F1 core-specific register space */
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+#define SDA_F3_FBR_SPACE	0x400	/* sdioAccess F3 FBR register space */
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 /* SDA_F1_REG_SPACE sdioaccess-accessible F1 reg space register offsets */
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 #define SDA_CHIPCONTROLDATA	0x006	/* ChipControlData */
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@@ -250,6 +260,13 @@
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 #define SDA_SDIOWRFRAMEBCHIGH	0x01a	/* SdioWrFrameBCHigh */
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 #define SDA_SDIORDFRAMEBCLOW	0x01b	/* SdioRdFrameBCLow */
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 #define SDA_SDIORDFRAMEBCHIGH	0x01c	/* SdioRdFrameBCHigh */
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+#define SDA_MESBUSYCNTRL	0x01d	/* mesBusyCntrl */
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+#define SDA_WAKEUPCTRL		0x01e	/* WakeupCtrl */
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+#define SDA_SLEEPCSR		0x01f	/* sleepCSR */
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+
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+/* SDA_F1_REG_SPACE register bits */
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+/* sleepCSR register */
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+#define SDA_SLEEPCSR_KEEP_SDIO_ON	0x1
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 /* SDA_F2WATERMARK */
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 #define SDA_F2WATERMARK_MASK	0x7f	/* F2Watermark Mask */