disable pwm7

hc

2024-05-10 23fa18eaa71266feff7ba8d83022d9e1cc83c65a

 kernel/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/phy.c
..
..
@@ -1,27 +1,5 @@
1
-/******************************************************************************
2
- *
3
- * Copyright(c) 2009-2012  Realtek Corporation.
4
- *
5
- * This program is free software; you can redistribute it and/or modify it
6
- * under the terms of version 2 of the GNU General Public License as
7
- * published by the Free Software Foundation.
8
- *
9
- * This program is distributed in the hope that it will be useful, but WITHOUT
10
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12
- * more details.
13
- *
14
- * The full GNU General Public License is included in this distribution in the
15
- * file called LICENSE.
16
- *
17
- * Contact Information:
18
- * wlanfae <wlanfae@realtek.com>
19
- * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20
- * Hsinchu 300, Taiwan.
21
- *
22
- * Larry Finger <Larry.Finger@lwfinger.net>
23
- *
24
- *****************************************************************************/
1
+// SPDX-License-Identifier: GPL-2.0
2
+/* Copyright(c) 2009-2012  Realtek Corporation.*/
25
3
 
26
4
 #include "../wifi.h"
27
5
 #include "../pci.h"
..
..
@@ -47,9 +25,9 @@
47
25
 	u32 original_value, readback_value, bitshift;
48
26
 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
49
27
 
50
-	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
51
-		 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
52
-		 regaddr, rfpath, bitmask);
28
+	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
29
+		"regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
30
+		regaddr, rfpath, bitmask);
53
31
 
54
32
 	spin_lock(&rtlpriv->locks.rf_lock);
55
33
 
..
..
@@ -66,9 +44,9 @@
66
44
 
67
45
 	spin_unlock(&rtlpriv->locks.rf_lock);
68
46
 
69
-	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
70
-		 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
71
-		 regaddr, rfpath, bitmask, original_value);
47
+	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
48
+		"regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
49
+		regaddr, rfpath, bitmask, original_value);
72
50
 
73
51
 	return readback_value;
74
52
 }
..
..
@@ -104,7 +82,7 @@
104
82
 	rtl_write_byte(rtlpriv, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
105
83
 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN,
106
84
 		       FEN_PPLL | FEN_PCIEA | FEN_DIO_PCIE |
107
-		       FEN_BB_GLB_RSTn | FEN_BBRSTB);
85
+		       FEN_BB_GLB_RSTN | FEN_BBRSTB);
108
86
 	rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80);
109
87
 	regvaldw = rtl_read_dword(rtlpriv, REG_LEDCFG0);
110
88
 	rtl_write_dword(rtlpriv, REG_LEDCFG0, regvaldw | BIT(23));
..
..
@@ -121,9 +99,9 @@
121
99
 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
122
100
 	u32 original_value, bitshift;
123
101
 
124
-	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
125
-		 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
126
-		 regaddr, bitmask, data, rfpath);
102
+	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
103
+		"regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
104
+		regaddr, bitmask, data, rfpath);
127
105
 
128
106
 	spin_lock(&rtlpriv->locks.rf_lock);
129
107
 
..
..
@@ -154,9 +132,9 @@
154
132
 
155
133
 	spin_unlock(&rtlpriv->locks.rf_lock);
156
134
 
157
-	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
158
-		 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
159
-		 regaddr, bitmask, data, rfpath);
135
+	rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
136
+		"regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
137
+		regaddr, bitmask, data, rfpath);
160
138
 }
161
139
 
162
140
 static bool _rtl92c_phy_config_mac_with_headerfile(struct ieee80211_hw *hw)
..
..
@@ -166,10 +144,10 @@
166
144
 	u32 arraylength;
167
145
 	u32 *ptrarray;
168
146
 
169
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl819XMACPHY_Array\n");
147
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl819XMACPHY_Array\n");
170
148
 	arraylength = MAC_2T_ARRAYLENGTH;
171
149
 	ptrarray = RTL8192CEMAC_2T_ARRAY;
172
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Img:RTL8192CEMAC_2T_ARRAY\n");
150
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Img:RTL8192CEMAC_2T_ARRAY\n");
173
151
 	for (i = 0; i < arraylength; i = i + 2)
174
152
 		rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]);
175
153
 	return true;
..
..
@@ -202,20 +180,20 @@
202
180
 			rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
203
181
 				      phy_regarray_table[i + 1]);
204
182
 			udelay(1);
205
-			RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
206
-				 "The phy_regarray_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
207
-				 phy_regarray_table[i],
208
-				 phy_regarray_table[i + 1]);
183
+			rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
184
+				"The phy_regarray_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
185
+				phy_regarray_table[i],
186
+				phy_regarray_table[i + 1]);
209
187
 		}
210
188
 	} else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
211
189
 		for (i = 0; i < agctab_arraylen; i = i + 2) {
212
190
 			rtl_set_bbreg(hw, agctab_array_table[i], MASKDWORD,
213
191
 				      agctab_array_table[i + 1]);
214
192
 			udelay(1);
215
-			RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
216
-				 "The agctab_array_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
217
-				 agctab_array_table[i],
218
-				 agctab_array_table[i + 1]);
193
+			rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
194
+				"The agctab_array_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
195
+				agctab_array_table[i],
196
+				agctab_array_table[i + 1]);
219
197
 		}
220
198
 	}
221
199
 	return true;
..
..
@@ -236,15 +214,15 @@
236
214
 		for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
237
215
 			rtl_addr_delay(phy_regarray_table_pg[i]);
238
216
 
239
-			_rtl92c_store_pwrIndex_diffrate_offset(hw,
217
+			_rtl92c_store_pwrindex_diffrate_offset(hw,
240
218
 					       phy_regarray_table_pg[i],
241
219
 					       phy_regarray_table_pg[i + 1],
242
220
 					       phy_regarray_table_pg[i + 2]);
243
221
 		}
244
222
 	} else {
245
223
 
246
-		RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
247
-			 "configtype != BaseBand_Config_PHY_REG\n");
224
+		rtl_dbg(rtlpriv, COMP_SEND, DBG_TRACE,
225
+			"configtype != BaseBand_Config_PHY_REG\n");
248
226
 	}
249
227
 	return true;
250
228
 }
..
..
@@ -265,21 +243,21 @@
265
243
 		radioa_array_table = RTL8192CERADIOA_2TARRAY;
266
244
 		radiob_arraylen = RADIOB_2TARRAYLENGTH;
267
245
 		radiob_array_table = RTL8192CE_RADIOB_2TARRAY;
268
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
269
-			 "Radio_A:RTL8192CERADIOA_2TARRAY\n");
270
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
271
-			 "Radio_B:RTL8192CE_RADIOB_2TARRAY\n");
246
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
247
+			"Radio_A:RTL8192CERADIOA_2TARRAY\n");
248
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
249
+			"Radio_B:RTL8192CE_RADIOB_2TARRAY\n");
272
250
 	} else {
273
251
 		radioa_arraylen = RADIOA_1TARRAYLENGTH;
274
252
 		radioa_array_table = RTL8192CE_RADIOA_1TARRAY;
275
253
 		radiob_arraylen = RADIOB_1TARRAYLENGTH;
276
254
 		radiob_array_table = RTL8192CE_RADIOB_1TARRAY;
277
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
278
-			 "Radio_A:RTL8192CE_RADIOA_1TARRAY\n");
279
-		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
280
-			 "Radio_B:RTL8192CE_RADIOB_1TARRAY\n");
255
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
256
+			"Radio_A:RTL8192CE_RADIOA_1TARRAY\n");
257
+		rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
258
+			"Radio_B:RTL8192CE_RADIOB_1TARRAY\n");
281
259
 	}
282
-	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Radio No %x\n", rfpath);
260
+	rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Radio No %x\n", rfpath);
283
261
 	switch (rfpath) {
284
262
 	case RF90_PATH_A:
285
263
 		for (i = 0; i < radioa_arraylen; i = i + 2) {
..
..
@@ -315,9 +293,9 @@
315
293
 	u8 reg_bw_opmode;
316
294
 	u8 reg_prsr_rsc;
317
295
 
318
-	RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n",
319
-		 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
320
-		 "20MHz" : "40MHz");
296
+	rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n",
297
+		rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
298
+		"20MHz" : "40MHz");
321
299
 
322
300
 	if (is_hal_stop(rtlhal)) {
323
301
 		rtlphy->set_bwmode_inprogress = false;
..
..
@@ -370,7 +348,7 @@
370
348
 	}
371
349
 	rtl92ce_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
372
350
 	rtlphy->set_bwmode_inprogress = false;
373
-	RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
351
+	rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
374
352
 }
375
353
 
376
354
 void _rtl92ce_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
..
..
@@ -440,8 +418,8 @@
440
418
 		rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
441
419
 		rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
442
420
 		rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
443
-		RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
444
-			 "Switch RF timeout !!!\n");
421
+		rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE,
422
+			"Switch RF timeout !!!\n");
445
423
 		return;
446
424
 	}
447
425
 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
..
..
@@ -464,21 +442,21 @@
464
442
 			if ((ppsc->rfpwr_state == ERFOFF) &&
465
443
 			    RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
466
444
 				bool rtstatus;
467
-				u32 InitializeCount = 0;
445
+				u32 initializecount = 0;
446
+
468
447
 				do {
469
-					InitializeCount++;
470
-					RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
471
-						 "IPS Set eRf nic enable\n");
448
+					initializecount++;
449
+					rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
450
+						"IPS Set eRf nic enable\n");
472
451
 					rtstatus = rtl_ps_enable_nic(hw);
473
-				} while (!rtstatus && (InitializeCount < 10));
452
+				} while (!rtstatus && (initializecount < 10));
474
453
 				RT_CLEAR_PS_LEVEL(ppsc,
475
454
 						  RT_RF_OFF_LEVL_HALT_NIC);
476
455
 			} else {
477
-				RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
478
-					 "Set ERFON sleeped:%d ms\n",
479
-					 jiffies_to_msecs(jiffies -
480
-							  ppsc->
481
-							  last_sleep_jiffies));
456
+				rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
457
+					"Set ERFON slept:%d ms\n",
458
+					jiffies_to_msecs(jiffies -
459
+						 ppsc->last_sleep_jiffies));
482
460
 				ppsc->last_awake_jiffies = jiffies;
483
461
 				rtl92ce_phy_set_rf_on(hw);
484
462
 			}
..
..
@@ -493,8 +471,8 @@
493
471
 		}
494
472
 	case ERFOFF:{
495
473
 			if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
496
-				RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
497
-					 "IPS Set eRf nic disable\n");
474
+				rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
475
+					"IPS Set eRf nic disable\n");
498
476
 				rtl_ps_disable_nic(hw);
499
477
 				RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
500
478
 			} else {
..
..
@@ -519,27 +497,27 @@
519
497
 					queue_id++;
520
498
 					continue;
521
499
 				} else {
522
-					RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
523
-						 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
524
-						 i + 1, queue_id,
525
-						 skb_queue_len(&ring->queue));
500
+					rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
501
+						"eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
502
+						i + 1, queue_id,
503
+						skb_queue_len(&ring->queue));
526
504
 
527
505
 					udelay(10);
528
506
 					i++;
529
507
 				}
530
508
 				if (i >= MAX_DOZE_WAITING_TIMES_9x) {
531
-					RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
532
-						 "ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
533
-						 MAX_DOZE_WAITING_TIMES_9x,
534
-						 queue_id,
535
-						 skb_queue_len(&ring->queue));
509
+					rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
510
+						"ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
511
+						MAX_DOZE_WAITING_TIMES_9x,
512
+						queue_id,
513
+						skb_queue_len(&ring->queue));
536
514
 					break;
537
515
 				}
538
516
 			}
539
-			RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
540
-				 "Set ERFSLEEP awaked:%d ms\n",
541
-				 jiffies_to_msecs(jiffies -
542
-						  ppsc->last_awake_jiffies));
517
+			rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
518
+				"Set ERFSLEEP awaked:%d ms\n",
519
+				jiffies_to_msecs(jiffies -
520
+						 ppsc->last_awake_jiffies));
543
521
 			ppsc->last_sleep_jiffies = jiffies;
544
522
 			_rtl92ce_phy_set_rf_sleep(hw);
545
523
 			break;