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2024-05-10 23fa18eaa71266feff7ba8d83022d9e1cc83c65a 
 kernel/drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c
....@@ -1,29 +1,426 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  *  Copyright (C) 2017 Chelsio Communications.  All rights reserved.
3
- *
4
- *  This program is free software; you can redistribute it and/or modify it
5
- *  under the terms and conditions of the GNU General Public License,
6
- *  version 2, as published by the Free Software Foundation.
7
- *
8
- *  This program is distributed in the hope it will be useful, but WITHOUT
9
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11
- *  more details.
12
- *
13
- *  The full GNU General Public License is included in this distribution in
14
- *  the file called "COPYING".
15
- *
164  */
175 
186 #include <linux/sort.h>
7
+#include <linux/string.h>
198 
209 #include "t4_regs.h"
2110 #include "cxgb4.h"
11
+#include "cxgb4_cudbg.h"
2212 #include "cudbg_if.h"
2313 #include "cudbg_lib_common.h"
2414 #include "cudbg_entity.h"
2515 #include "cudbg_lib.h"
2616 #include "cudbg_zlib.h"
17
+#include "cxgb4_tc_mqprio.h"
18
+
19
+static const u32 t6_tp_pio_array[][IREG_NUM_ELEM] = {
20
+	{0x7e40, 0x7e44, 0x020, 28}, /* t6_tp_pio_regs_20_to_3b */
21
+	{0x7e40, 0x7e44, 0x040, 10}, /* t6_tp_pio_regs_40_to_49 */
22
+	{0x7e40, 0x7e44, 0x050, 10}, /* t6_tp_pio_regs_50_to_59 */
23
+	{0x7e40, 0x7e44, 0x060, 14}, /* t6_tp_pio_regs_60_to_6d */
24
+	{0x7e40, 0x7e44, 0x06F, 1}, /* t6_tp_pio_regs_6f */
25
+	{0x7e40, 0x7e44, 0x070, 6}, /* t6_tp_pio_regs_70_to_75 */
26
+	{0x7e40, 0x7e44, 0x130, 18}, /* t6_tp_pio_regs_130_to_141 */
27
+	{0x7e40, 0x7e44, 0x145, 19}, /* t6_tp_pio_regs_145_to_157 */
28
+	{0x7e40, 0x7e44, 0x160, 1}, /* t6_tp_pio_regs_160 */
29
+	{0x7e40, 0x7e44, 0x230, 25}, /* t6_tp_pio_regs_230_to_248 */
30
+	{0x7e40, 0x7e44, 0x24a, 3}, /* t6_tp_pio_regs_24c */
31
+	{0x7e40, 0x7e44, 0x8C0, 1} /* t6_tp_pio_regs_8c0 */
32
+};
33
+
34
+static const u32 t5_tp_pio_array[][IREG_NUM_ELEM] = {
35
+	{0x7e40, 0x7e44, 0x020, 28}, /* t5_tp_pio_regs_20_to_3b */
36
+	{0x7e40, 0x7e44, 0x040, 19}, /* t5_tp_pio_regs_40_to_52 */
37
+	{0x7e40, 0x7e44, 0x054, 2}, /* t5_tp_pio_regs_54_to_55 */
38
+	{0x7e40, 0x7e44, 0x060, 13}, /* t5_tp_pio_regs_60_to_6c */
39
+	{0x7e40, 0x7e44, 0x06F, 1}, /* t5_tp_pio_regs_6f */
40
+	{0x7e40, 0x7e44, 0x120, 4}, /* t5_tp_pio_regs_120_to_123 */
41
+	{0x7e40, 0x7e44, 0x12b, 2}, /* t5_tp_pio_regs_12b_to_12c */
42
+	{0x7e40, 0x7e44, 0x12f, 21}, /* t5_tp_pio_regs_12f_to_143 */
43
+	{0x7e40, 0x7e44, 0x145, 19}, /* t5_tp_pio_regs_145_to_157 */
44
+	{0x7e40, 0x7e44, 0x230, 25}, /* t5_tp_pio_regs_230_to_248 */
45
+	{0x7e40, 0x7e44, 0x8C0, 1} /* t5_tp_pio_regs_8c0 */
46
+};
47
+
48
+static const u32 t6_tp_tm_pio_array[][IREG_NUM_ELEM] = {
49
+	{0x7e18, 0x7e1c, 0x0, 12}
50
+};
51
+
52
+static const u32 t5_tp_tm_pio_array[][IREG_NUM_ELEM] = {
53
+	{0x7e18, 0x7e1c, 0x0, 12}
54
+};
55
+
56
+static const u32 t6_tp_mib_index_array[6][IREG_NUM_ELEM] = {
57
+	{0x7e50, 0x7e54, 0x0, 13},
58
+	{0x7e50, 0x7e54, 0x10, 6},
59
+	{0x7e50, 0x7e54, 0x18, 21},
60
+	{0x7e50, 0x7e54, 0x30, 32},
61
+	{0x7e50, 0x7e54, 0x50, 22},
62
+	{0x7e50, 0x7e54, 0x68, 12}
63
+};
64
+
65
+static const u32 t5_tp_mib_index_array[9][IREG_NUM_ELEM] = {
66
+	{0x7e50, 0x7e54, 0x0, 13},
67
+	{0x7e50, 0x7e54, 0x10, 6},
68
+	{0x7e50, 0x7e54, 0x18, 8},
69
+	{0x7e50, 0x7e54, 0x20, 13},
70
+	{0x7e50, 0x7e54, 0x30, 16},
71
+	{0x7e50, 0x7e54, 0x40, 16},
72
+	{0x7e50, 0x7e54, 0x50, 16},
73
+	{0x7e50, 0x7e54, 0x60, 6},
74
+	{0x7e50, 0x7e54, 0x68, 4}
75
+};
76
+
77
+static const u32 t5_sge_dbg_index_array[2][IREG_NUM_ELEM] = {
78
+	{0x10cc, 0x10d0, 0x0, 16},
79
+	{0x10cc, 0x10d4, 0x0, 16},
80
+};
81
+
82
+static const u32 t6_sge_qbase_index_array[] = {
83
+	/* 1 addr reg SGE_QBASE_INDEX and 4 data reg SGE_QBASE_MAP[0-3] */
84
+	0x1250, 0x1240, 0x1244, 0x1248, 0x124c,
85
+};
86
+
87
+static const u32 t5_pcie_pdbg_array[][IREG_NUM_ELEM] = {
88
+	{0x5a04, 0x5a0c, 0x00, 0x20}, /* t5_pcie_pdbg_regs_00_to_20 */
89
+	{0x5a04, 0x5a0c, 0x21, 0x20}, /* t5_pcie_pdbg_regs_21_to_40 */
90
+	{0x5a04, 0x5a0c, 0x41, 0x10}, /* t5_pcie_pdbg_regs_41_to_50 */
91
+};
92
+
93
+static const u32 t5_pcie_cdbg_array[][IREG_NUM_ELEM] = {
94
+	{0x5a10, 0x5a18, 0x00, 0x20}, /* t5_pcie_cdbg_regs_00_to_20 */
95
+	{0x5a10, 0x5a18, 0x21, 0x18}, /* t5_pcie_cdbg_regs_21_to_37 */
96
+};
97
+
98
+static const u32 t5_pm_rx_array[][IREG_NUM_ELEM] = {
99
+	{0x8FD0, 0x8FD4, 0x10000, 0x20}, /* t5_pm_rx_regs_10000_to_10020 */
100
+	{0x8FD0, 0x8FD4, 0x10021, 0x0D}, /* t5_pm_rx_regs_10021_to_1002c */
101
+};
102
+
103
+static const u32 t5_pm_tx_array[][IREG_NUM_ELEM] = {
104
+	{0x8FF0, 0x8FF4, 0x10000, 0x20}, /* t5_pm_tx_regs_10000_to_10020 */
105
+	{0x8FF0, 0x8FF4, 0x10021, 0x1D}, /* t5_pm_tx_regs_10021_to_1003c */
106
+};
107
+
108
+static const u32 t5_pcie_config_array[][2] = {
109
+	{0x0, 0x34},
110
+	{0x3c, 0x40},
111
+	{0x50, 0x64},
112
+	{0x70, 0x80},
113
+	{0x94, 0xa0},
114
+	{0xb0, 0xb8},
115
+	{0xd0, 0xd4},
116
+	{0x100, 0x128},
117
+	{0x140, 0x148},
118
+	{0x150, 0x164},
119
+	{0x170, 0x178},
120
+	{0x180, 0x194},
121
+	{0x1a0, 0x1b8},
122
+	{0x1c0, 0x208},
123
+};
124
+
125
+static const u32 t6_ma_ireg_array[][IREG_NUM_ELEM] = {
126
+	{0x78f8, 0x78fc, 0xa000, 23}, /* t6_ma_regs_a000_to_a016 */
127
+	{0x78f8, 0x78fc, 0xa400, 30}, /* t6_ma_regs_a400_to_a41e */
128
+	{0x78f8, 0x78fc, 0xa800, 20} /* t6_ma_regs_a800_to_a813 */
129
+};
130
+
131
+static const u32 t6_ma_ireg_array2[][IREG_NUM_ELEM] = {
132
+	{0x78f8, 0x78fc, 0xe400, 17}, /* t6_ma_regs_e400_to_e600 */
133
+	{0x78f8, 0x78fc, 0xe640, 13} /* t6_ma_regs_e640_to_e7c0 */
134
+};
135
+
136
+static const u32 t6_up_cim_reg_array[][IREG_NUM_ELEM + 1] = {
137
+	{0x7b50, 0x7b54, 0x2000, 0x20, 0}, /* up_cim_2000_to_207c */
138
+	{0x7b50, 0x7b54, 0x2080, 0x1d, 0}, /* up_cim_2080_to_20fc */
139
+	{0x7b50, 0x7b54, 0x00, 0x20, 0}, /* up_cim_00_to_7c */
140
+	{0x7b50, 0x7b54, 0x80, 0x20, 0}, /* up_cim_80_to_fc */
141
+	{0x7b50, 0x7b54, 0x100, 0x11, 0}, /* up_cim_100_to_14c */
142
+	{0x7b50, 0x7b54, 0x200, 0x10, 0}, /* up_cim_200_to_23c */
143
+	{0x7b50, 0x7b54, 0x240, 0x2, 0}, /* up_cim_240_to_244 */
144
+	{0x7b50, 0x7b54, 0x250, 0x2, 0}, /* up_cim_250_to_254 */
145
+	{0x7b50, 0x7b54, 0x260, 0x2, 0}, /* up_cim_260_to_264 */
146
+	{0x7b50, 0x7b54, 0x270, 0x2, 0}, /* up_cim_270_to_274 */
147
+	{0x7b50, 0x7b54, 0x280, 0x20, 0}, /* up_cim_280_to_2fc */
148
+	{0x7b50, 0x7b54, 0x300, 0x20, 0}, /* up_cim_300_to_37c */
149
+	{0x7b50, 0x7b54, 0x380, 0x14, 0}, /* up_cim_380_to_3cc */
150
+	{0x7b50, 0x7b54, 0x4900, 0x4, 0x4}, /* up_cim_4900_to_4c60 */
151
+	{0x7b50, 0x7b54, 0x4904, 0x4, 0x4}, /* up_cim_4904_to_4c64 */
152
+	{0x7b50, 0x7b54, 0x4908, 0x4, 0x4}, /* up_cim_4908_to_4c68 */
153
+	{0x7b50, 0x7b54, 0x4910, 0x4, 0x4}, /* up_cim_4910_to_4c70 */
154
+	{0x7b50, 0x7b54, 0x4914, 0x4, 0x4}, /* up_cim_4914_to_4c74 */
155
+	{0x7b50, 0x7b54, 0x4920, 0x10, 0x10}, /* up_cim_4920_to_4a10 */
156
+	{0x7b50, 0x7b54, 0x4924, 0x10, 0x10}, /* up_cim_4924_to_4a14 */
157
+	{0x7b50, 0x7b54, 0x4928, 0x10, 0x10}, /* up_cim_4928_to_4a18 */
158
+	{0x7b50, 0x7b54, 0x492c, 0x10, 0x10}, /* up_cim_492c_to_4a1c */
159
+};
160
+
161
+static const u32 t5_up_cim_reg_array[][IREG_NUM_ELEM + 1] = {
162
+	{0x7b50, 0x7b54, 0x2000, 0x20, 0}, /* up_cim_2000_to_207c */
163
+	{0x7b50, 0x7b54, 0x2080, 0x19, 0}, /* up_cim_2080_to_20ec */
164
+	{0x7b50, 0x7b54, 0x00, 0x20, 0}, /* up_cim_00_to_7c */
165
+	{0x7b50, 0x7b54, 0x80, 0x20, 0}, /* up_cim_80_to_fc */
166
+	{0x7b50, 0x7b54, 0x100, 0x11, 0}, /* up_cim_100_to_14c */
167
+	{0x7b50, 0x7b54, 0x200, 0x10, 0}, /* up_cim_200_to_23c */
168
+	{0x7b50, 0x7b54, 0x240, 0x2, 0}, /* up_cim_240_to_244 */
169
+	{0x7b50, 0x7b54, 0x250, 0x2, 0}, /* up_cim_250_to_254 */
170
+	{0x7b50, 0x7b54, 0x260, 0x2, 0}, /* up_cim_260_to_264 */
171
+	{0x7b50, 0x7b54, 0x270, 0x2, 0}, /* up_cim_270_to_274 */
172
+	{0x7b50, 0x7b54, 0x280, 0x20, 0}, /* up_cim_280_to_2fc */
173
+	{0x7b50, 0x7b54, 0x300, 0x20, 0}, /* up_cim_300_to_37c */
174
+	{0x7b50, 0x7b54, 0x380, 0x14, 0}, /* up_cim_380_to_3cc */
175
+};
176
+
177
+static const u32 t6_hma_ireg_array[][IREG_NUM_ELEM] = {
178
+	{0x51320, 0x51324, 0xa000, 32} /* t6_hma_regs_a000_to_a01f */
179
+};
180
+
181
+u32 cudbg_get_entity_length(struct adapter *adap, u32 entity)
182
+{
183
+	struct cudbg_tcam tcam_region = { 0 };
184
+	u32 value, n = 0, len = 0;
185
+
186
+	switch (entity) {
187
+	case CUDBG_REG_DUMP:
188
+		switch (CHELSIO_CHIP_VERSION(adap->params.chip)) {
189
+		case CHELSIO_T4:
190
+			len = T4_REGMAP_SIZE;
191
+			break;
192
+		case CHELSIO_T5:
193
+		case CHELSIO_T6:
194
+			len = T5_REGMAP_SIZE;
195
+			break;
196
+		default:
197
+			break;
198
+		}
199
+		break;
200
+	case CUDBG_DEV_LOG:
201
+		len = adap->params.devlog.size;
202
+		break;
203
+	case CUDBG_CIM_LA:
204
+		if (is_t6(adap->params.chip)) {
205
+			len = adap->params.cim_la_size / 10 + 1;
206
+			len *= 10 * sizeof(u32);
207
+		} else {
208
+			len = adap->params.cim_la_size / 8;
209
+			len *= 8 * sizeof(u32);
210
+		}
211
+		len += sizeof(u32); /* for reading CIM LA configuration */
212
+		break;
213
+	case CUDBG_CIM_MA_LA:
214
+		len = 2 * CIM_MALA_SIZE * 5 * sizeof(u32);
215
+		break;
216
+	case CUDBG_CIM_QCFG:
217
+		len = sizeof(struct cudbg_cim_qcfg);
218
+		break;
219
+	case CUDBG_CIM_IBQ_TP0:
220
+	case CUDBG_CIM_IBQ_TP1:
221
+	case CUDBG_CIM_IBQ_ULP:
222
+	case CUDBG_CIM_IBQ_SGE0:
223
+	case CUDBG_CIM_IBQ_SGE1:
224
+	case CUDBG_CIM_IBQ_NCSI:
225
+		len = CIM_IBQ_SIZE * 4 * sizeof(u32);
226
+		break;
227
+	case CUDBG_CIM_OBQ_ULP0:
228
+		len = cudbg_cim_obq_size(adap, 0);
229
+		break;
230
+	case CUDBG_CIM_OBQ_ULP1:
231
+		len = cudbg_cim_obq_size(adap, 1);
232
+		break;
233
+	case CUDBG_CIM_OBQ_ULP2:
234
+		len = cudbg_cim_obq_size(adap, 2);
235
+		break;
236
+	case CUDBG_CIM_OBQ_ULP3:
237
+		len = cudbg_cim_obq_size(adap, 3);
238
+		break;
239
+	case CUDBG_CIM_OBQ_SGE:
240
+		len = cudbg_cim_obq_size(adap, 4);
241
+		break;
242
+	case CUDBG_CIM_OBQ_NCSI:
243
+		len = cudbg_cim_obq_size(adap, 5);
244
+		break;
245
+	case CUDBG_CIM_OBQ_RXQ0:
246
+		len = cudbg_cim_obq_size(adap, 6);
247
+		break;
248
+	case CUDBG_CIM_OBQ_RXQ1:
249
+		len = cudbg_cim_obq_size(adap, 7);
250
+		break;
251
+	case CUDBG_EDC0:
252
+		value = t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A);
253
+		if (value & EDRAM0_ENABLE_F) {
254
+			value = t4_read_reg(adap, MA_EDRAM0_BAR_A);
255
+			len = EDRAM0_SIZE_G(value);
256
+		}
257
+		len = cudbg_mbytes_to_bytes(len);
258
+		break;
259
+	case CUDBG_EDC1:
260
+		value = t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A);
261
+		if (value & EDRAM1_ENABLE_F) {
262
+			value = t4_read_reg(adap, MA_EDRAM1_BAR_A);
263
+			len = EDRAM1_SIZE_G(value);
264
+		}
265
+		len = cudbg_mbytes_to_bytes(len);
266
+		break;
267
+	case CUDBG_MC0:
268
+		value = t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A);
269
+		if (value & EXT_MEM0_ENABLE_F) {
270
+			value = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A);
271
+			len = EXT_MEM0_SIZE_G(value);
272
+		}
273
+		len = cudbg_mbytes_to_bytes(len);
274
+		break;
275
+	case CUDBG_MC1:
276
+		value = t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A);
277
+		if (value & EXT_MEM1_ENABLE_F) {
278
+			value = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
279
+			len = EXT_MEM1_SIZE_G(value);
280
+		}
281
+		len = cudbg_mbytes_to_bytes(len);
282
+		break;
283
+	case CUDBG_RSS:
284
+		len = t4_chip_rss_size(adap) * sizeof(u16);
285
+		break;
286
+	case CUDBG_RSS_VF_CONF:
287
+		len = adap->params.arch.vfcount *
288
+		      sizeof(struct cudbg_rss_vf_conf);
289
+		break;
290
+	case CUDBG_PATH_MTU:
291
+		len = NMTUS * sizeof(u16);
292
+		break;
293
+	case CUDBG_PM_STATS:
294
+		len = sizeof(struct cudbg_pm_stats);
295
+		break;
296
+	case CUDBG_HW_SCHED:
297
+		len = sizeof(struct cudbg_hw_sched);
298
+		break;
299
+	case CUDBG_TP_INDIRECT:
300
+		switch (CHELSIO_CHIP_VERSION(adap->params.chip)) {
301
+		case CHELSIO_T5:
302
+			n = sizeof(t5_tp_pio_array) +
303
+			    sizeof(t5_tp_tm_pio_array) +
304
+			    sizeof(t5_tp_mib_index_array);
305
+			break;
306
+		case CHELSIO_T6:
307
+			n = sizeof(t6_tp_pio_array) +
308
+			    sizeof(t6_tp_tm_pio_array) +
309
+			    sizeof(t6_tp_mib_index_array);
310
+			break;
311
+		default:
312
+			break;
313
+		}
314
+		n = n / (IREG_NUM_ELEM * sizeof(u32));
315
+		len = sizeof(struct ireg_buf) * n;
316
+		break;
317
+	case CUDBG_SGE_INDIRECT:
318
+		len = sizeof(struct ireg_buf) * 2 +
319
+		      sizeof(struct sge_qbase_reg_field);
320
+		break;
321
+	case CUDBG_ULPRX_LA:
322
+		len = sizeof(struct cudbg_ulprx_la);
323
+		break;
324
+	case CUDBG_TP_LA:
325
+		len = sizeof(struct cudbg_tp_la) + TPLA_SIZE * sizeof(u64);
326
+		break;
327
+	case CUDBG_MEMINFO:
328
+		len = sizeof(struct cudbg_ver_hdr) +
329
+		      sizeof(struct cudbg_meminfo);
330
+		break;
331
+	case CUDBG_CIM_PIF_LA:
332
+		len = sizeof(struct cudbg_cim_pif_la);
333
+		len += 2 * CIM_PIFLA_SIZE * 6 * sizeof(u32);
334
+		break;
335
+	case CUDBG_CLK:
336
+		len = sizeof(struct cudbg_clk_info);
337
+		break;
338
+	case CUDBG_PCIE_INDIRECT:
339
+		n = sizeof(t5_pcie_pdbg_array) / (IREG_NUM_ELEM * sizeof(u32));
340
+		len = sizeof(struct ireg_buf) * n * 2;
341
+		break;
342
+	case CUDBG_PM_INDIRECT:
343
+		n = sizeof(t5_pm_rx_array) / (IREG_NUM_ELEM * sizeof(u32));
344
+		len = sizeof(struct ireg_buf) * n * 2;
345
+		break;
346
+	case CUDBG_TID_INFO:
347
+		len = sizeof(struct cudbg_tid_info_region_rev1);
348
+		break;
349
+	case CUDBG_PCIE_CONFIG:
350
+		len = sizeof(u32) * CUDBG_NUM_PCIE_CONFIG_REGS;
351
+		break;
352
+	case CUDBG_DUMP_CONTEXT:
353
+		len = cudbg_dump_context_size(adap);
354
+		break;
355
+	case CUDBG_MPS_TCAM:
356
+		len = sizeof(struct cudbg_mps_tcam) *
357
+		      adap->params.arch.mps_tcam_size;
358
+		break;
359
+	case CUDBG_VPD_DATA:
360
+		len = sizeof(struct cudbg_vpd_data);
361
+		break;
362
+	case CUDBG_LE_TCAM:
363
+		cudbg_fill_le_tcam_info(adap, &tcam_region);
364
+		len = sizeof(struct cudbg_tcam) +
365
+		      sizeof(struct cudbg_tid_data) * tcam_region.max_tid;
366
+		break;
367
+	case CUDBG_CCTRL:
368
+		len = sizeof(u16) * NMTUS * NCCTRL_WIN;
369
+		break;
370
+	case CUDBG_MA_INDIRECT:
371
+		if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
372
+			n = sizeof(t6_ma_ireg_array) /
373
+			    (IREG_NUM_ELEM * sizeof(u32));
374
+			len = sizeof(struct ireg_buf) * n * 2;
375
+		}
376
+		break;
377
+	case CUDBG_ULPTX_LA:
378
+		len = sizeof(struct cudbg_ver_hdr) +
379
+		      sizeof(struct cudbg_ulptx_la);
380
+		break;
381
+	case CUDBG_UP_CIM_INDIRECT:
382
+		n = 0;
383
+		if (is_t5(adap->params.chip))
384
+			n = sizeof(t5_up_cim_reg_array) /
385
+			    ((IREG_NUM_ELEM + 1) * sizeof(u32));
386
+		else if (is_t6(adap->params.chip))
387
+			n = sizeof(t6_up_cim_reg_array) /
388
+			    ((IREG_NUM_ELEM + 1) * sizeof(u32));
389
+		len = sizeof(struct ireg_buf) * n;
390
+		break;
391
+	case CUDBG_PBT_TABLE:
392
+		len = sizeof(struct cudbg_pbt_tables);
393
+		break;
394
+	case CUDBG_MBOX_LOG:
395
+		len = sizeof(struct cudbg_mbox_log) * adap->mbox_log->size;
396
+		break;
397
+	case CUDBG_HMA_INDIRECT:
398
+		if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
399
+			n = sizeof(t6_hma_ireg_array) /
400
+			    (IREG_NUM_ELEM * sizeof(u32));
401
+			len = sizeof(struct ireg_buf) * n;
402
+		}
403
+		break;
404
+	case CUDBG_HMA:
405
+		value = t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A);
406
+		if (value & HMA_MUX_F) {
407
+			/* In T6, there's no MC1.  So, HMA shares MC1
408
+			 * address space.
409
+			 */
410
+			value = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
411
+			len = EXT_MEM1_SIZE_G(value);
412
+		}
413
+		len = cudbg_mbytes_to_bytes(len);
414
+		break;
415
+	case CUDBG_QDESC:
416
+		cudbg_fill_qdesc_num_and_size(adap, NULL, &len);
417
+		break;
418
+	default:
419
+		break;
420
+	}
421
+
422
+	return len;
423
+}
27424 
28425 static int cudbg_do_compression(struct cudbg_init *pdbg_init,
29426 				struct cudbg_buffer *pin_buff,
....@@ -80,7 +477,7 @@
80477 {
81478 	struct adapter *padap = pdbg_init->adap;
82479 
83
-	if (!(padap->flags & FW_OK) || padap->use_bd)
480
+	if (!(padap->flags & CXGB4_FW_OK) || padap->use_bd)
84481 		return 0;
85482 
86483 	return 1;
....@@ -787,24 +1184,18 @@
7871184 				struct cudbg_mem_desc *mem_desc)
7881185 {
7891186 	u8 mc, found = 0;
790
-	u32 i, idx = 0;
791
-	int rc;
1187
+	u32 idx = 0;
1188
+	int rc, i;
7921189 
7931190 	rc = cudbg_meminfo_get_mem_index(padap, meminfo, mem_type, &mc);
7941191 	if (rc)
7951192 		return rc;
7961193 
797
-	for (i = 0; i < ARRAY_SIZE(cudbg_region); i++) {
798
-		if (!strcmp(cudbg_region[i], region_name)) {
799
-			found = 1;
800
-			idx = i;
801
-			break;
802
-		}
803
-	}
804
-	if (!found)
1194
+	i = match_string(cudbg_region, ARRAY_SIZE(cudbg_region), region_name);
1195
+	if (i < 0)
8051196 		return -EINVAL;
8061197 
807
-	found = 0;
1198
+	idx = i;
8081199 	for (i = 0; i < meminfo->mem_c; i++) {
8091200 		if (meminfo->mem[i].idx >= ARRAY_SIZE(cudbg_region))
8101201 			continue; /* Skip holes */
....@@ -1248,6 +1639,10 @@
12481639 
12491640 	rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(struct cudbg_hw_sched),
12501641 			    &temp_buff);
1642
+
1643
+	if (rc)
1644
+		return rc;
1645
+
12511646 	hw_sched_buff = (struct cudbg_hw_sched *)temp_buff.data;
12521647 	hw_sched_buff->map = t4_read_reg(padap, TP_TX_MOD_QUEUE_REQ_MAP_A);
12531648 	hw_sched_buff->mode = TIMERMODE_G(t4_read_reg(padap, TP_MOD_CONFIG_A));
....@@ -2927,3 +3322,307 @@
29273322 	}
29283323 	return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
29293324 }
3325
+
3326
+void cudbg_fill_qdesc_num_and_size(const struct adapter *padap,
3327
+				   u32 *num, u32 *size)
3328
+{
3329
+	u32 tot_entries = 0, tot_size = 0;
3330
+
3331
+	/* NIC TXQ, RXQ, FLQ, and CTRLQ */
3332
+	tot_entries += MAX_ETH_QSETS * 3;
3333
+	tot_entries += MAX_CTRL_QUEUES;
3334
+
3335
+	tot_size += MAX_ETH_QSETS * MAX_TXQ_ENTRIES * MAX_TXQ_DESC_SIZE;
3336
+	tot_size += MAX_ETH_QSETS * MAX_RSPQ_ENTRIES * MAX_RXQ_DESC_SIZE;
3337
+	tot_size += MAX_ETH_QSETS * MAX_RX_BUFFERS * MAX_FL_DESC_SIZE;
3338
+	tot_size += MAX_CTRL_QUEUES * MAX_CTRL_TXQ_ENTRIES *
3339
+		    MAX_CTRL_TXQ_DESC_SIZE;
3340
+
3341
+	/* FW_EVTQ and INTRQ */
3342
+	tot_entries += INGQ_EXTRAS;
3343
+	tot_size += INGQ_EXTRAS * MAX_RSPQ_ENTRIES * MAX_RXQ_DESC_SIZE;
3344
+
3345
+	/* PTP_TXQ */
3346
+	tot_entries += 1;
3347
+	tot_size += MAX_TXQ_ENTRIES * MAX_TXQ_DESC_SIZE;
3348
+
3349
+	/* ULD TXQ, RXQ, and FLQ */
3350
+	tot_entries += CXGB4_TX_MAX * MAX_OFLD_QSETS;
3351
+	tot_entries += CXGB4_ULD_MAX * MAX_ULD_QSETS * 2;
3352
+
3353
+	tot_size += CXGB4_TX_MAX * MAX_OFLD_QSETS * MAX_TXQ_ENTRIES *
3354
+		    MAX_TXQ_DESC_SIZE;
3355
+	tot_size += CXGB4_ULD_MAX * MAX_ULD_QSETS * MAX_RSPQ_ENTRIES *
3356
+		    MAX_RXQ_DESC_SIZE;
3357
+	tot_size += CXGB4_ULD_MAX * MAX_ULD_QSETS * MAX_RX_BUFFERS *
3358
+		    MAX_FL_DESC_SIZE;
3359
+
3360
+	/* ULD CIQ */
3361
+	tot_entries += CXGB4_ULD_MAX * MAX_ULD_QSETS;
3362
+	tot_size += CXGB4_ULD_MAX * MAX_ULD_QSETS * SGE_MAX_IQ_SIZE *
3363
+		    MAX_RXQ_DESC_SIZE;
3364
+
3365
+	/* ETHOFLD TXQ, RXQ, and FLQ */
3366
+	tot_entries += MAX_OFLD_QSETS * 3;
3367
+	tot_size += MAX_OFLD_QSETS * MAX_TXQ_ENTRIES * MAX_TXQ_DESC_SIZE;
3368
+
3369
+	tot_size += sizeof(struct cudbg_ver_hdr) +
3370
+		    sizeof(struct cudbg_qdesc_info) +
3371
+		    sizeof(struct cudbg_qdesc_entry) * tot_entries;
3372
+
3373
+	if (num)
3374
+		*num = tot_entries;
3375
+
3376
+	if (size)
3377
+		*size = tot_size;
3378
+}
3379
+
3380
+int cudbg_collect_qdesc(struct cudbg_init *pdbg_init,
3381
+			struct cudbg_buffer *dbg_buff,
3382
+			struct cudbg_error *cudbg_err)
3383
+{
3384
+	u32 num_queues = 0, tot_entries = 0, size = 0;
3385
+	struct adapter *padap = pdbg_init->adap;
3386
+	struct cudbg_buffer temp_buff = { 0 };
3387
+	struct cudbg_qdesc_entry *qdesc_entry;
3388
+	struct cudbg_qdesc_info *qdesc_info;
3389
+	struct cudbg_ver_hdr *ver_hdr;
3390
+	struct sge *s = &padap->sge;
3391
+	u32 i, j, cur_off, tot_len;
3392
+	u8 *data;
3393
+	int rc;
3394
+
3395
+	cudbg_fill_qdesc_num_and_size(padap, &tot_entries, &size);
3396
+	size = min_t(u32, size, CUDBG_DUMP_BUFF_SIZE);
3397
+	tot_len = size;
3398
+	data = kvzalloc(size, GFP_KERNEL);
3399
+	if (!data)
3400
+		return -ENOMEM;
3401
+
3402
+	ver_hdr = (struct cudbg_ver_hdr *)data;
3403
+	ver_hdr->signature = CUDBG_ENTITY_SIGNATURE;
3404
+	ver_hdr->revision = CUDBG_QDESC_REV;
3405
+	ver_hdr->size = sizeof(struct cudbg_qdesc_info);
3406
+	size -= sizeof(*ver_hdr);
3407
+
3408
+	qdesc_info = (struct cudbg_qdesc_info *)(data +
3409
+						 sizeof(*ver_hdr));
3410
+	size -= sizeof(*qdesc_info);
3411
+	qdesc_entry = (struct cudbg_qdesc_entry *)qdesc_info->data;
3412
+
3413
+#define QDESC_GET(q, desc, type, label) do { \
3414
+	if (size <= 0) { \
3415
+		goto label; \
3416
+	} \
3417
+	if (desc) { \
3418
+		cudbg_fill_qdesc_##q(q, type, qdesc_entry); \
3419
+		size -= sizeof(*qdesc_entry) + qdesc_entry->data_size; \
3420
+		num_queues++; \
3421
+		qdesc_entry = cudbg_next_qdesc(qdesc_entry); \
3422
+	} \
3423
+} while (0)
3424
+
3425
+#define QDESC_GET_TXQ(q, type, label) do { \
3426
+	struct sge_txq *txq = (struct sge_txq *)q; \
3427
+	QDESC_GET(txq, txq->desc, type, label); \
3428
+} while (0)
3429
+
3430
+#define QDESC_GET_RXQ(q, type, label) do { \
3431
+	struct sge_rspq *rxq = (struct sge_rspq *)q; \
3432
+	QDESC_GET(rxq, rxq->desc, type, label); \
3433
+} while (0)
3434
+
3435
+#define QDESC_GET_FLQ(q, type, label) do { \
3436
+	struct sge_fl *flq = (struct sge_fl *)q; \
3437
+	QDESC_GET(flq, flq->desc, type, label); \
3438
+} while (0)
3439
+
3440
+	/* NIC TXQ */
3441
+	for (i = 0; i < s->ethqsets; i++)
3442
+		QDESC_GET_TXQ(&s->ethtxq[i].q, CUDBG_QTYPE_NIC_TXQ, out);
3443
+
3444
+	/* NIC RXQ */
3445
+	for (i = 0; i < s->ethqsets; i++)
3446
+		QDESC_GET_RXQ(&s->ethrxq[i].rspq, CUDBG_QTYPE_NIC_RXQ, out);
3447
+
3448
+	/* NIC FLQ */
3449
+	for (i = 0; i < s->ethqsets; i++)
3450
+		QDESC_GET_FLQ(&s->ethrxq[i].fl, CUDBG_QTYPE_NIC_FLQ, out);
3451
+
3452
+	/* NIC CTRLQ */
3453
+	for (i = 0; i < padap->params.nports; i++)
3454
+		QDESC_GET_TXQ(&s->ctrlq[i].q, CUDBG_QTYPE_CTRLQ, out);
3455
+
3456
+	/* FW_EVTQ */
3457
+	QDESC_GET_RXQ(&s->fw_evtq, CUDBG_QTYPE_FWEVTQ, out);
3458
+
3459
+	/* INTRQ */
3460
+	QDESC_GET_RXQ(&s->intrq, CUDBG_QTYPE_INTRQ, out);
3461
+
3462
+	/* PTP_TXQ */
3463
+	QDESC_GET_TXQ(&s->ptptxq.q, CUDBG_QTYPE_PTP_TXQ, out);
3464
+
3465
+	/* ULD Queues */
3466
+	mutex_lock(&uld_mutex);
3467
+
3468
+	if (s->uld_txq_info) {
3469
+		struct sge_uld_txq_info *utxq;
3470
+
3471
+		/* ULD TXQ */
3472
+		for (j = 0; j < CXGB4_TX_MAX; j++) {
3473
+			if (!s->uld_txq_info[j])
3474
+				continue;
3475
+
3476
+			utxq = s->uld_txq_info[j];
3477
+			for (i = 0; i < utxq->ntxq; i++)
3478
+				QDESC_GET_TXQ(&utxq->uldtxq[i].q,
3479
+					      cudbg_uld_txq_to_qtype(j),
3480
+					      out_unlock_uld);
3481
+		}
3482
+	}
3483
+
3484
+	if (s->uld_rxq_info) {
3485
+		struct sge_uld_rxq_info *urxq;
3486
+		u32 base;
3487
+
3488
+		/* ULD RXQ */
3489
+		for (j = 0; j < CXGB4_ULD_MAX; j++) {
3490
+			if (!s->uld_rxq_info[j])
3491
+				continue;
3492
+
3493
+			urxq = s->uld_rxq_info[j];
3494
+			for (i = 0; i < urxq->nrxq; i++)
3495
+				QDESC_GET_RXQ(&urxq->uldrxq[i].rspq,
3496
+					      cudbg_uld_rxq_to_qtype(j),
3497
+					      out_unlock_uld);
3498
+		}
3499
+
3500
+		/* ULD FLQ */
3501
+		for (j = 0; j < CXGB4_ULD_MAX; j++) {
3502
+			if (!s->uld_rxq_info[j])
3503
+				continue;
3504
+
3505
+			urxq = s->uld_rxq_info[j];
3506
+			for (i = 0; i < urxq->nrxq; i++)
3507
+				QDESC_GET_FLQ(&urxq->uldrxq[i].fl,
3508
+					      cudbg_uld_flq_to_qtype(j),
3509
+					      out_unlock_uld);
3510
+		}
3511
+
3512
+		/* ULD CIQ */
3513
+		for (j = 0; j < CXGB4_ULD_MAX; j++) {
3514
+			if (!s->uld_rxq_info[j])
3515
+				continue;
3516
+
3517
+			urxq = s->uld_rxq_info[j];
3518
+			base = urxq->nrxq;
3519
+			for (i = 0; i < urxq->nciq; i++)
3520
+				QDESC_GET_RXQ(&urxq->uldrxq[base + i].rspq,
3521
+					      cudbg_uld_ciq_to_qtype(j),
3522
+					      out_unlock_uld);
3523
+		}
3524
+	}
3525
+	mutex_unlock(&uld_mutex);
3526
+
3527
+	if (!padap->tc_mqprio)
3528
+		goto out;
3529
+
3530
+	mutex_lock(&padap->tc_mqprio->mqprio_mutex);
3531
+	/* ETHOFLD TXQ */
3532
+	if (s->eohw_txq)
3533
+		for (i = 0; i < s->eoqsets; i++)
3534
+			QDESC_GET_TXQ(&s->eohw_txq[i].q,
3535
+				      CUDBG_QTYPE_ETHOFLD_TXQ, out_unlock_mqprio);
3536
+
3537
+	/* ETHOFLD RXQ and FLQ */
3538
+	if (s->eohw_rxq) {
3539
+		for (i = 0; i < s->eoqsets; i++)
3540
+			QDESC_GET_RXQ(&s->eohw_rxq[i].rspq,
3541
+				      CUDBG_QTYPE_ETHOFLD_RXQ, out_unlock_mqprio);
3542
+
3543
+		for (i = 0; i < s->eoqsets; i++)
3544
+			QDESC_GET_FLQ(&s->eohw_rxq[i].fl,
3545
+				      CUDBG_QTYPE_ETHOFLD_FLQ, out_unlock_mqprio);
3546
+	}
3547
+
3548
+out_unlock_mqprio:
3549
+	mutex_unlock(&padap->tc_mqprio->mqprio_mutex);
3550
+
3551
+out:
3552
+	qdesc_info->qdesc_entry_size = sizeof(*qdesc_entry);
3553
+	qdesc_info->num_queues = num_queues;
3554
+	cur_off = 0;
3555
+	while (tot_len) {
3556
+		u32 chunk_size = min_t(u32, tot_len, CUDBG_CHUNK_SIZE);
3557
+
3558
+		rc = cudbg_get_buff(pdbg_init, dbg_buff, chunk_size,
3559
+				    &temp_buff);
3560
+		if (rc) {
3561
+			cudbg_err->sys_warn = CUDBG_STATUS_PARTIAL_DATA;
3562
+			goto out_free;
3563
+		}
3564
+
3565
+		memcpy(temp_buff.data, data + cur_off, chunk_size);
3566
+		tot_len -= chunk_size;
3567
+		cur_off += chunk_size;
3568
+		rc = cudbg_write_and_release_buff(pdbg_init, &temp_buff,
3569
+						  dbg_buff);
3570
+		if (rc) {
3571
+			cudbg_put_buff(pdbg_init, &temp_buff);
3572
+			cudbg_err->sys_warn = CUDBG_STATUS_PARTIAL_DATA;
3573
+			goto out_free;
3574
+		}
3575
+	}
3576
+
3577
+out_free:
3578
+	if (data)
3579
+		kvfree(data);
3580
+
3581
+#undef QDESC_GET_FLQ
3582
+#undef QDESC_GET_RXQ
3583
+#undef QDESC_GET_TXQ
3584
+#undef QDESC_GET
3585
+
3586
+	return rc;
3587
+
3588
+out_unlock_uld:
3589
+	mutex_unlock(&uld_mutex);
3590
+	goto out;
3591
+}
3592
+
3593
+int cudbg_collect_flash(struct cudbg_init *pdbg_init,
3594
+			struct cudbg_buffer *dbg_buff,
3595
+			struct cudbg_error *cudbg_err)
3596
+{
3597
+	struct adapter *padap = pdbg_init->adap;
3598
+	u32 count = padap->params.sf_size, n;
3599
+	struct cudbg_buffer temp_buff = {0};
3600
+	u32 addr, i;
3601
+	int rc;
3602
+
3603
+	addr = FLASH_EXP_ROM_START;
3604
+
3605
+	for (i = 0; i < count; i += SF_PAGE_SIZE) {
3606
+		n = min_t(u32, count - i, SF_PAGE_SIZE);
3607
+
3608
+		rc = cudbg_get_buff(pdbg_init, dbg_buff, n, &temp_buff);
3609
+		if (rc) {
3610
+			cudbg_err->sys_warn = CUDBG_STATUS_PARTIAL_DATA;
3611
+			goto out;
3612
+		}
3613
+		rc = t4_read_flash(padap, addr, n, (u32 *)temp_buff.data, 0);
3614
+		if (rc)
3615
+			goto out;
3616
+
3617
+		addr += (n * 4);
3618
+		rc = cudbg_write_and_release_buff(pdbg_init, &temp_buff,
3619
+						  dbg_buff);
3620
+		if (rc) {
3621
+			cudbg_err->sys_warn = CUDBG_STATUS_PARTIAL_DATA;
3622
+			goto out;
3623
+		}
3624
+	}
3625
+
3626
+out:
3627
+	return rc;
3628
+}