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2024-05-10 23fa18eaa71266feff7ba8d83022d9e1cc83c65a 
 kernel/drivers/mtd/nand/raw/lpc32xx_mlc.c
....@@ -1,3 +1,4 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23  * Driver for NAND MLC Controller in LPC32xx
34  *
....@@ -5,17 +6,6 @@
56  *
67  * Copyright © 2011 WORK Microwave GmbH
78  * Copyright © 2011, 2012 Roland Stigge
8
- *
9
- * This program is free software; you can redistribute it and/or modify
10
- * it under the terms of the GNU General Public License as published by
11
- * the Free Software Foundation; either version 2 of the License, or
12
- * (at your option) any later version.
13
- *
14
- * This program is distributed in the hope that it will be useful,
15
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
16
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17
- * GNU General Public License for more details.
18
- *
199  *
2010  * NAND Flash Controller Operation:
2111  * - Read: Auto Decode
....@@ -286,10 +276,9 @@
286276 /*
287277  * Hardware specific access to control lines
288278  */
289
-static void lpc32xx_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
279
+static void lpc32xx_nand_cmd_ctrl(struct nand_chip *nand_chip, int cmd,
290280 				  unsigned int ctrl)
291281 {
292
-	struct nand_chip *nand_chip = mtd_to_nand(mtd);
293282 	struct lpc32xx_nand_host *host = nand_get_controller_data(nand_chip);
294283 
295284 	if (cmd != NAND_CMD_NONE) {
....@@ -303,9 +292,8 @@
303292 /*
304293  * Read Device Ready (NAND device _and_ controller ready)
305294  */
306
-static int lpc32xx_nand_device_ready(struct mtd_info *mtd)
295
+static int lpc32xx_nand_device_ready(struct nand_chip *nand_chip)
307296 {
308
-	struct nand_chip *nand_chip = mtd_to_nand(mtd);
309297 	struct lpc32xx_nand_host *host = nand_get_controller_data(nand_chip);
310298 
311299 	if ((readb(MLC_ISR(host->io_base)) &
....@@ -330,8 +318,9 @@
330318 	return IRQ_HANDLED;
331319 }
332320 
333
-static int lpc32xx_waitfunc_nand(struct mtd_info *mtd, struct nand_chip *chip)
321
+static int lpc32xx_waitfunc_nand(struct nand_chip *chip)
334322 {
323
+	struct mtd_info *mtd = nand_to_mtd(chip);
335324 	struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
336325 
337326 	if (readb(MLC_ISR(host->io_base)) & MLCISR_NAND_READY)
....@@ -349,9 +338,9 @@
349338 	return NAND_STATUS_READY;
350339 }
351340 
352
-static int lpc32xx_waitfunc_controller(struct mtd_info *mtd,
353
-				       struct nand_chip *chip)
341
+static int lpc32xx_waitfunc_controller(struct nand_chip *chip)
354342 {
343
+	struct mtd_info *mtd = nand_to_mtd(chip);
355344 	struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
356345 
357346 	if (readb(MLC_ISR(host->io_base)) & MLCISR_CONTROLLER_READY)
....@@ -369,10 +358,10 @@
369358 	return NAND_STATUS_READY;
370359 }
371360 
372
-static int lpc32xx_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
361
+static int lpc32xx_waitfunc(struct nand_chip *chip)
373362 {
374
-	lpc32xx_waitfunc_nand(mtd, chip);
375
-	lpc32xx_waitfunc_controller(mtd, chip);
363
+	lpc32xx_waitfunc_nand(chip);
364
+	lpc32xx_waitfunc_controller(chip);
376365 
377366 	return NAND_STATUS_READY;
378367 }
....@@ -442,9 +431,10 @@
442431 	return -ENXIO;
443432 }
444433 
445
-static int lpc32xx_read_page(struct mtd_info *mtd, struct nand_chip *chip,
446
-			     uint8_t *buf, int oob_required, int page)
434
+static int lpc32xx_read_page(struct nand_chip *chip, uint8_t *buf,
435
+			     int oob_required, int page)
447436 {
437
+	struct mtd_info *mtd = nand_to_mtd(chip);
448438 	struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
449439 	int i, j;
450440 	uint8_t *oobbuf = chip->oob_poi;
....@@ -470,7 +460,7 @@
470460 		writeb(0x00, MLC_ECC_AUTO_DEC_REG(host->io_base));
471461 
472462 		/* Wait for Controller Ready */
473
-		lpc32xx_waitfunc_controller(mtd, chip);
463
+		lpc32xx_waitfunc_controller(chip);
474464 
475465 		/* Check ECC Error status */
476466 		mlc_isr = readl(MLC_ISR(host->io_base));
....@@ -507,11 +497,11 @@
507497 	return 0;
508498 }
509499 
510
-static int lpc32xx_write_page_lowlevel(struct mtd_info *mtd,
511
-				       struct nand_chip *chip,
500
+static int lpc32xx_write_page_lowlevel(struct nand_chip *chip,
512501 				       const uint8_t *buf, int oob_required,
513502 				       int page)
514503 {
504
+	struct mtd_info *mtd = nand_to_mtd(chip);
515505 	struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
516506 	const uint8_t *oobbuf = chip->oob_poi;
517507 	uint8_t *dma_buf = (uint8_t *)buf;
....@@ -551,32 +541,30 @@
551541 		writeb(0x00, MLC_ECC_AUTO_ENC_REG(host->io_base));
552542 
553543 		/* Wait for Controller Ready */
554
-		lpc32xx_waitfunc_controller(mtd, chip);
544
+		lpc32xx_waitfunc_controller(chip);
555545 	}
556546 
557547 	return nand_prog_page_end_op(chip);
558548 }
559549 
560
-static int lpc32xx_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
561
-			    int page)
550
+static int lpc32xx_read_oob(struct nand_chip *chip, int page)
562551 {
563552 	struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
564553 
565554 	/* Read whole page - necessary with MLC controller! */
566
-	lpc32xx_read_page(mtd, chip, host->dummy_buf, 1, page);
555
+	lpc32xx_read_page(chip, host->dummy_buf, 1, page);
567556 
568557 	return 0;
569558 }
570559 
571
-static int lpc32xx_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
572
-			      int page)
560
+static int lpc32xx_write_oob(struct nand_chip *chip, int page)
573561 {
574562 	/* None, write_oob conflicts with the automatic LPC MLC ECC decoder! */
575563 	return 0;
576564 }
577565 
578566 /* Prepares MLC for transfers with H/W ECC enabled: always enabled anyway */
579
-static void lpc32xx_ecc_enable(struct mtd_info *mtd, int mode)
567
+static void lpc32xx_ecc_enable(struct nand_chip *chip, int mode)
580568 {
581569 	/* Always enabled! */
582570 }
....@@ -660,6 +648,9 @@
660648 	struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
661649 	struct device *dev = &host->pdev->dev;
662650 
651
+	if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST)
652
+		return 0;
653
+
663654 	host->dma_buf = devm_kzalloc(dev, mtd->writesize, GFP_KERNEL);
664655 	if (!host->dma_buf)
665656 		return -ENOMEM;
....@@ -668,8 +659,17 @@
668659 	if (!host->dummy_buf)
669660 		return -ENOMEM;
670661 
671
-	chip->ecc.mode = NAND_ECC_HW;
672662 	chip->ecc.size = 512;
663
+	chip->ecc.hwctl = lpc32xx_ecc_enable;
664
+	chip->ecc.read_page_raw = lpc32xx_read_page;
665
+	chip->ecc.read_page = lpc32xx_read_page;
666
+	chip->ecc.write_page_raw = lpc32xx_write_page_lowlevel;
667
+	chip->ecc.write_page = lpc32xx_write_page_lowlevel;
668
+	chip->ecc.write_oob = lpc32xx_write_oob;
669
+	chip->ecc.read_oob = lpc32xx_read_oob;
670
+	chip->ecc.strength = 4;
671
+	chip->ecc.bytes = 10;
672
+
673673 	mtd_set_ooblayout(mtd, &lpc32xx_ooblayout_ops);
674674 	host->mlcsubpages = mtd->writesize / 512;
675675 
....@@ -741,11 +741,11 @@
741741 	if (res)
742742 		goto put_clk;
743743 
744
-	nand_chip->cmd_ctrl = lpc32xx_nand_cmd_ctrl;
745
-	nand_chip->dev_ready = lpc32xx_nand_device_ready;
746
-	nand_chip->chip_delay = 25; /* us */
747
-	nand_chip->IO_ADDR_R = MLC_DATA(host->io_base);
748
-	nand_chip->IO_ADDR_W = MLC_DATA(host->io_base);
744
+	nand_chip->legacy.cmd_ctrl = lpc32xx_nand_cmd_ctrl;
745
+	nand_chip->legacy.dev_ready = lpc32xx_nand_device_ready;
746
+	nand_chip->legacy.chip_delay = 25; /* us */
747
+	nand_chip->legacy.IO_ADDR_R = MLC_DATA(host->io_base);
748
+	nand_chip->legacy.IO_ADDR_W = MLC_DATA(host->io_base);
749749 
750750 	/* Init NAND controller */
751751 	lpc32xx_nand_setup(host);
....@@ -753,16 +753,7 @@
753753 	platform_set_drvdata(pdev, host);
754754 
755755 	/* Initialize function pointers */
756
-	nand_chip->ecc.hwctl = lpc32xx_ecc_enable;
757
-	nand_chip->ecc.read_page_raw = lpc32xx_read_page;
758
-	nand_chip->ecc.read_page = lpc32xx_read_page;
759
-	nand_chip->ecc.write_page_raw = lpc32xx_write_page_lowlevel;
760
-	nand_chip->ecc.write_page = lpc32xx_write_page_lowlevel;
761
-	nand_chip->ecc.write_oob = lpc32xx_write_oob;
762
-	nand_chip->ecc.read_oob = lpc32xx_read_oob;
763
-	nand_chip->ecc.strength = 4;
764
-	nand_chip->ecc.bytes = 10;
765
-	nand_chip->waitfunc = lpc32xx_waitfunc;
756
+	nand_chip->legacy.waitfunc = lpc32xx_waitfunc;
766757 
767758 	nand_chip->options = NAND_NO_SUBPAGE_WRITE;
768759 	nand_chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
....@@ -785,7 +776,6 @@
785776 
786777 	host->irq = platform_get_irq(pdev, 0);
787778 	if (host->irq < 0) {
788
-		dev_err(&pdev->dev, "failed to get platform irq\n");
789779 		res = -EINVAL;
790780 		goto release_dma_chan;
791781 	}
....@@ -801,7 +791,7 @@
801791 	 * Scan to find existence of the device and get the type of NAND device:
802792 	 * SMALL block or LARGE block.
803793 	 */
804
-	nand_chip->dummy_controller.ops = &lpc32xx_nand_controller_ops;
794
+	nand_chip->legacy.dummy_controller.ops = &lpc32xx_nand_controller_ops;
805795 	res = nand_scan(nand_chip, 1);
806796 	if (res)
807797 		goto free_irq;
....@@ -839,8 +829,13 @@
839829 static int lpc32xx_nand_remove(struct platform_device *pdev)
840830 {
841831 	struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
832
+	struct nand_chip *chip = &host->nand_chip;
833
+	int ret;
842834 
843
-	nand_release(&host->nand_chip);
835
+	ret = mtd_device_unregister(nand_to_mtd(chip));
836
+	WARN_ON(ret);
837
+	nand_cleanup(chip);
838
+
844839 	free_irq(host->irq, host);
845840 	if (use_dma)
846841 		dma_release_channel(host->dma_chan);