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2024-05-10 23fa18eaa71266feff7ba8d83022d9e1cc83c65a 
 kernel/drivers/mmc/host/sdhci-pci-o2micro.c
....@@ -1,25 +1,17 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * Copyright (C) 2013 BayHub Technology Ltd.
34  *
45  * Authors: Peter Guo <peter.guo@bayhubtech.com>
56  *          Adam Lee <adam.lee@canonical.com>
67  *          Ernest Zhang <ernest.zhang@bayhubtech.com>
7
- *
8
- * This software is licensed under the terms of the GNU General Public
9
- * License version 2, as published by the Free Software Foundation, and
10
- * may be copied, distributed, and modified under those terms.
11
- *
12
- * This program is distributed in the hope that it will be useful,
13
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
14
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15
- * GNU General Public License for more details.
16
- *
178  */
189 
1910 #include <linux/pci.h>
2011 #include <linux/mmc/host.h>
2112 #include <linux/mmc/mmc.h>
2213 #include <linux/delay.h>
14
+#include <linux/iopoll.h>
2315 
2416 #include "sdhci.h"
2517 #include "sdhci-pci.h"
....@@ -39,8 +31,11 @@
3931 #define O2_SD_CAPS		0xE0
4032 #define O2_SD_ADMA1		0xE2
4133 #define O2_SD_ADMA2		0xE7
34
+#define O2_SD_MISC_CTRL2	0xF0
4235 #define O2_SD_INF_MOD		0xF1
4336 #define O2_SD_MISC_CTRL4	0xFC
37
+#define O2_SD_MISC_CTRL		0x1C0
38
+#define O2_SD_PWR_FORCE_L0	0x0002
4439 #define O2_SD_TUNING_CTRL	0x300
4540 #define O2_SD_PLL_SETTING	0x304
4641 #define O2_SD_MISC_SETTING	0x308
....@@ -60,6 +55,138 @@
6055 #define O2_SD_VENDOR_SETTING2	0x1C8
6156 #define O2_SD_HW_TUNING_DISABLE	BIT(4)
6257 
58
+#define O2_PLL_DLL_WDT_CONTROL1	0x1CC
59
+#define  O2_PLL_FORCE_ACTIVE	BIT(18)
60
+#define  O2_PLL_LOCK_STATUS	BIT(14)
61
+#define  O2_PLL_SOFT_RESET	BIT(12)
62
+#define  O2_DLL_LOCK_STATUS	BIT(11)
63
+
64
+#define O2_SD_DETECT_SETTING 0x324
65
+
66
+static const u32 dmdn_table[] = {0x2B1C0000,
67
+	0x2C1A0000, 0x371B0000, 0x35100000};
68
+#define DMDN_SZ ARRAY_SIZE(dmdn_table)
69
+
70
+struct o2_host {
71
+	u8 dll_adjust_count;
72
+};
73
+
74
+static void sdhci_o2_wait_card_detect_stable(struct sdhci_host *host)
75
+{
76
+	ktime_t timeout;
77
+	u32 scratch32;
78
+
79
+	/* Wait max 50 ms */
80
+	timeout = ktime_add_ms(ktime_get(), 50);
81
+	while (1) {
82
+		bool timedout = ktime_after(ktime_get(), timeout);
83
+
84
+		scratch32 = sdhci_readl(host, SDHCI_PRESENT_STATE);
85
+		if ((scratch32 & SDHCI_CARD_PRESENT) >> SDHCI_CARD_PRES_SHIFT
86
+		    == (scratch32 & SDHCI_CD_LVL) >> SDHCI_CD_LVL_SHIFT)
87
+			break;
88
+
89
+		if (timedout) {
90
+			pr_err("%s: Card Detect debounce never finished.\n",
91
+			       mmc_hostname(host->mmc));
92
+			sdhci_dumpregs(host);
93
+			return;
94
+		}
95
+		udelay(10);
96
+	}
97
+}
98
+
99
+static void sdhci_o2_enable_internal_clock(struct sdhci_host *host)
100
+{
101
+	ktime_t timeout;
102
+	u16 scratch;
103
+	u32 scratch32;
104
+
105
+	/* PLL software reset */
106
+	scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
107
+	scratch32 |= O2_PLL_SOFT_RESET;
108
+	sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
109
+	udelay(1);
110
+	scratch32 &= ~(O2_PLL_SOFT_RESET);
111
+	sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
112
+
113
+	/* PLL force active */
114
+	scratch32 |= O2_PLL_FORCE_ACTIVE;
115
+	sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
116
+
117
+	/* Wait max 20 ms */
118
+	timeout = ktime_add_ms(ktime_get(), 20);
119
+	while (1) {
120
+		bool timedout = ktime_after(ktime_get(), timeout);
121
+
122
+		scratch = sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1);
123
+		if (scratch & O2_PLL_LOCK_STATUS)
124
+			break;
125
+		if (timedout) {
126
+			pr_err("%s: Internal clock never stabilised.\n",
127
+			       mmc_hostname(host->mmc));
128
+			sdhci_dumpregs(host);
129
+			goto out;
130
+		}
131
+		udelay(10);
132
+	}
133
+
134
+	/* Wait for card detect finish */
135
+	udelay(1);
136
+	sdhci_o2_wait_card_detect_stable(host);
137
+
138
+out:
139
+	/* Cancel PLL force active */
140
+	scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
141
+	scratch32 &= ~O2_PLL_FORCE_ACTIVE;
142
+	sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
143
+}
144
+
145
+static int sdhci_o2_get_cd(struct mmc_host *mmc)
146
+{
147
+	struct sdhci_host *host = mmc_priv(mmc);
148
+
149
+	if (!(sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1) & O2_PLL_LOCK_STATUS))
150
+		sdhci_o2_enable_internal_clock(host);
151
+	else
152
+		sdhci_o2_wait_card_detect_stable(host);
153
+
154
+	return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
155
+}
156
+
157
+static void o2_pci_set_baseclk(struct sdhci_pci_chip *chip, u32 value)
158
+{
159
+	u32 scratch_32;
160
+
161
+	pci_read_config_dword(chip->pdev,
162
+			      O2_SD_PLL_SETTING, &scratch_32);
163
+
164
+	scratch_32 &= 0x0000FFFF;
165
+	scratch_32 |= value;
166
+
167
+	pci_write_config_dword(chip->pdev,
168
+			       O2_SD_PLL_SETTING, scratch_32);
169
+}
170
+
171
+static u32 sdhci_o2_pll_dll_wdt_control(struct sdhci_host *host)
172
+{
173
+	return sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
174
+}
175
+
176
+/*
177
+ * This function is used to detect dll lock status.
178
+ * Since the dll lock status bit will toggle randomly
179
+ * with very short interval which needs to be polled
180
+ * as fast as possible. Set sleep_us as 1 microsecond.
181
+ */
182
+static int sdhci_o2_wait_dll_detect_lock(struct sdhci_host *host)
183
+{
184
+	u32	scratch32 = 0;
185
+
186
+	return readx_poll_timeout(sdhci_o2_pll_dll_wdt_control, host,
187
+		scratch32, !(scratch32 & O2_DLL_LOCK_STATUS), 1, 1000000);
188
+}
189
+
63190 static void sdhci_o2_set_tuning_mode(struct sdhci_host *host)
64191 {
65192 	u16 reg;
....@@ -74,7 +201,7 @@
74201 {
75202 	int i;
76203 
77
-	sdhci_send_tuning(host, MMC_SEND_TUNING_BLOCK_HS200);
204
+	sdhci_send_tuning(host, opcode);
78205 
79206 	for (i = 0; i < 150; i++) {
80207 		u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
....@@ -97,21 +224,122 @@
97224 	sdhci_reset_tuning(host);
98225 }
99226 
227
+/*
228
+ * This function is used to fix o2 dll shift issue.
229
+ * It isn't necessary to detect card present before recovery.
230
+ * Firstly, it is used by bht emmc card, which is embedded.
231
+ * Second, before call recovery card present will be detected
232
+ * outside of the execute tuning function.
233
+ */
234
+static int sdhci_o2_dll_recovery(struct sdhci_host *host)
235
+{
236
+	int ret = 0;
237
+	u8 scratch_8 = 0;
238
+	u32 scratch_32 = 0;
239
+	struct sdhci_pci_slot *slot = sdhci_priv(host);
240
+	struct sdhci_pci_chip *chip = slot->chip;
241
+	struct o2_host *o2_host = sdhci_pci_priv(slot);
242
+
243
+	/* UnLock WP */
244
+	pci_read_config_byte(chip->pdev,
245
+			O2_SD_LOCK_WP, &scratch_8);
246
+	scratch_8 &= 0x7f;
247
+	pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
248
+	while (o2_host->dll_adjust_count < DMDN_SZ && !ret) {
249
+		/* Disable clock */
250
+		sdhci_writeb(host, 0, SDHCI_CLOCK_CONTROL);
251
+
252
+		/* PLL software reset */
253
+		scratch_32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
254
+		scratch_32 |= O2_PLL_SOFT_RESET;
255
+		sdhci_writel(host, scratch_32, O2_PLL_DLL_WDT_CONTROL1);
256
+
257
+		pci_read_config_dword(chip->pdev,
258
+					    O2_SD_FUNC_REG4,
259
+					    &scratch_32);
260
+		/* Enable Base Clk setting change */
261
+		scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET;
262
+		pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG4, scratch_32);
263
+		o2_pci_set_baseclk(chip, dmdn_table[o2_host->dll_adjust_count]);
264
+
265
+		/* Enable internal clock */
266
+		scratch_8 = SDHCI_CLOCK_INT_EN;
267
+		sdhci_writeb(host, scratch_8, SDHCI_CLOCK_CONTROL);
268
+
269
+		if (sdhci_o2_get_cd(host->mmc)) {
270
+			/*
271
+			 * need wait at least 5ms for dll status stable,
272
+			 * after enable internal clock
273
+			 */
274
+			usleep_range(5000, 6000);
275
+			if (sdhci_o2_wait_dll_detect_lock(host)) {
276
+				scratch_8 |= SDHCI_CLOCK_CARD_EN;
277
+				sdhci_writeb(host, scratch_8,
278
+					SDHCI_CLOCK_CONTROL);
279
+				ret = 1;
280
+			} else {
281
+				pr_warn("%s: DLL unlocked when dll_adjust_count is %d.\n",
282
+					mmc_hostname(host->mmc),
283
+					o2_host->dll_adjust_count);
284
+			}
285
+		} else {
286
+			pr_err("%s: card present detect failed.\n",
287
+				mmc_hostname(host->mmc));
288
+			break;
289
+		}
290
+
291
+		o2_host->dll_adjust_count++;
292
+	}
293
+	if (!ret && o2_host->dll_adjust_count == DMDN_SZ)
294
+		pr_err("%s: DLL adjust over max times\n",
295
+		mmc_hostname(host->mmc));
296
+	/* Lock WP */
297
+	pci_read_config_byte(chip->pdev,
298
+				   O2_SD_LOCK_WP, &scratch_8);
299
+	scratch_8 |= 0x80;
300
+	pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
301
+	return ret;
302
+}
303
+
100304 static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode)
101305 {
102306 	struct sdhci_host *host = mmc_priv(mmc);
103307 	int current_bus_width = 0;
308
+	u32 scratch32 = 0;
309
+	u16 scratch = 0;
104310 
105311 	/*
106312 	 * This handler only implements the eMMC tuning that is specific to
107313 	 * this controller.  Fall back to the standard method for other TIMING.
108314 	 */
109
-	if (host->timing != MMC_TIMING_MMC_HS200)
315
+	if ((host->timing != MMC_TIMING_MMC_HS200) &&
316
+		(host->timing != MMC_TIMING_UHS_SDR104))
110317 		return sdhci_execute_tuning(mmc, opcode);
111318 
112
-	if (WARN_ON(opcode != MMC_SEND_TUNING_BLOCK_HS200))
319
+	if (WARN_ON((opcode != MMC_SEND_TUNING_BLOCK_HS200) &&
320
+			(opcode != MMC_SEND_TUNING_BLOCK)))
113321 		return -EINVAL;
114322 
323
+	/* Force power mode enter L0 */
324
+	scratch = sdhci_readw(host, O2_SD_MISC_CTRL);
325
+	scratch |= O2_SD_PWR_FORCE_L0;
326
+	sdhci_writew(host, scratch, O2_SD_MISC_CTRL);
327
+
328
+	/* wait DLL lock, timeout value 5ms */
329
+	if (readx_poll_timeout(sdhci_o2_pll_dll_wdt_control, host,
330
+		scratch32, (scratch32 & O2_DLL_LOCK_STATUS), 1, 5000))
331
+		pr_warn("%s: DLL can't lock in 5ms after force L0 during tuning.\n",
332
+				mmc_hostname(host->mmc));
333
+	/*
334
+	 * Judge the tuning reason, whether caused by dll shift
335
+	 * If cause by dll shift, should call sdhci_o2_dll_recovery
336
+	 */
337
+	if (!sdhci_o2_wait_dll_detect_lock(host))
338
+		if (!sdhci_o2_dll_recovery(host)) {
339
+			pr_err("%s: o2 dll recovery failed\n",
340
+				mmc_hostname(host->mmc));
341
+			return -EINVAL;
342
+		}
115343 	/*
116344 	 * o2 sdhci host didn't support 8bit emmc tuning
117345 	 */
....@@ -134,21 +362,16 @@
134362 		sdhci_set_bus_width(host, current_bus_width);
135363 	}
136364 
365
+	/* Cancel force power mode enter L0 */
366
+	scratch = sdhci_readw(host, O2_SD_MISC_CTRL);
367
+	scratch &= ~(O2_SD_PWR_FORCE_L0);
368
+	sdhci_writew(host, scratch, O2_SD_MISC_CTRL);
369
+
370
+	sdhci_reset(host, SDHCI_RESET_CMD);
371
+	sdhci_reset(host, SDHCI_RESET_DATA);
372
+
137373 	host->flags &= ~SDHCI_HS400_TUNING;
138374 	return 0;
139
-}
140
-
141
-static void o2_pci_set_baseclk(struct sdhci_pci_chip *chip, u32 value)
142
-{
143
-	u32 scratch_32;
144
-	pci_read_config_dword(chip->pdev,
145
-			      O2_SD_PLL_SETTING, &scratch_32);
146
-
147
-	scratch_32 &= 0x0000FFFF;
148
-	scratch_32 |= value;
149
-
150
-	pci_write_config_dword(chip->pdev,
151
-			       O2_SD_PLL_SETTING, scratch_32);
152375 }
153376 
154377 static void o2_pci_led_enable(struct sdhci_pci_chip *chip)
....@@ -174,7 +397,6 @@
174397 	scratch_32 |= O2_SD_LED_ENABLE;
175398 	pci_write_config_dword(chip->pdev,
176399 			       O2_SD_TEST_REG, scratch_32);
177
-
178400 }
179401 
180402 static void sdhci_pci_o2_fujin2_pci_init(struct sdhci_pci_chip *chip)
....@@ -286,16 +508,67 @@
286508 	host->irq = pci_irq_vector(chip->pdev, 0);
287509 }
288510 
289
-int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot)
511
+static void sdhci_o2_enable_clk(struct sdhci_host *host, u16 clk)
512
+{
513
+	/* Enable internal clock */
514
+	clk |= SDHCI_CLOCK_INT_EN;
515
+	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
516
+
517
+	sdhci_o2_enable_internal_clock(host);
518
+	if (sdhci_o2_get_cd(host->mmc)) {
519
+		clk |= SDHCI_CLOCK_CARD_EN;
520
+		sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
521
+	}
522
+}
523
+
524
+static void sdhci_pci_o2_set_clock(struct sdhci_host *host, unsigned int clock)
525
+{
526
+	u16 clk;
527
+	u8 scratch;
528
+	u32 scratch_32;
529
+	struct sdhci_pci_slot *slot = sdhci_priv(host);
530
+	struct sdhci_pci_chip *chip = slot->chip;
531
+
532
+	host->mmc->actual_clock = 0;
533
+
534
+	sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
535
+
536
+	if (clock == 0)
537
+		return;
538
+
539
+	if ((host->timing == MMC_TIMING_UHS_SDR104) && (clock == 200000000)) {
540
+		pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
541
+
542
+		scratch &= 0x7f;
543
+		pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
544
+
545
+		pci_read_config_dword(chip->pdev, O2_SD_PLL_SETTING, &scratch_32);
546
+
547
+		if ((scratch_32 & 0xFFFF0000) != 0x2c280000)
548
+			o2_pci_set_baseclk(chip, 0x2c280000);
549
+
550
+		pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
551
+
552
+		scratch |= 0x80;
553
+		pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
554
+	}
555
+
556
+	clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
557
+	sdhci_o2_enable_clk(host, clk);
558
+}
559
+
560
+static int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot)
290561 {
291562 	struct sdhci_pci_chip *chip;
292563 	struct sdhci_host *host;
564
+	struct o2_host *o2_host = sdhci_pci_priv(slot);
293565 	u32 reg, caps;
294566 	int ret;
295567 
296568 	chip = slot->chip;
297569 	host = slot->host;
298570 
571
+	o2_host->dll_adjust_count = 0;
299572 	caps = sdhci_readl(host, SDHCI_CAPABILITIES);
300573 
301574 	/*
....@@ -329,7 +602,17 @@
329602 				host->flags |= SDHCI_SIGNALING_180;
330603 				host->mmc->caps2 |= MMC_CAP2_NO_SD;
331604 				host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
605
+				pci_write_config_dword(chip->pdev,
606
+						       O2_SD_DETECT_SETTING, 3);
332607 			}
608
+
609
+			slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd;
610
+		}
611
+
612
+		if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD1) {
613
+			slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd;
614
+			host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
615
+			host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
333616 		}
334617 
335618 		host->mmc_host_ops.execute_tuning = sdhci_o2_execute_tuning;
....@@ -349,7 +632,7 @@
349632 	return 0;
350633 }
351634 
352
-int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip)
635
+static int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip)
353636 {
354637 	int ret;
355638 	u8 scratch;
....@@ -503,9 +786,6 @@
503786 		pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
504787 		break;
505788 	case PCI_DEVICE_ID_O2_SEABIRD0:
506
-		if (chip->pdev->revision == 0x01)
507
-			chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
508
-		/* fall through */
509789 	case PCI_DEVICE_ID_O2_SEABIRD1:
510790 		/* UnLock WP */
511791 		ret = pci_read_config_byte(chip->pdev,
....@@ -543,6 +823,12 @@
543823 		/* Set Tuning Windows to 5 */
544824 		pci_write_config_byte(chip->pdev,
545825 				O2_SD_TUNING_CTRL, 0x55);
826
+		//Adjust 1st and 2nd CD debounce time
827
+		pci_read_config_dword(chip->pdev, O2_SD_MISC_CTRL2, &scratch_32);
828
+		scratch_32 &= 0xFFE7FFFF;
829
+		scratch_32 |= 0x00180000;
830
+		pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL2, scratch_32);
831
+		pci_write_config_dword(chip->pdev, O2_SD_DETECT_SETTING, 1);
546832 		/* Lock WP */
547833 		ret = pci_read_config_byte(chip->pdev,
548834 					   O2_SD_LOCK_WP, &scratch);
....@@ -557,9 +843,29 @@
557843 }
558844 
559845 #ifdef CONFIG_PM_SLEEP
560
-int sdhci_pci_o2_resume(struct sdhci_pci_chip *chip)
846
+static int sdhci_pci_o2_resume(struct sdhci_pci_chip *chip)
561847 {
562848 	sdhci_pci_o2_probe(chip);
563849 	return sdhci_pci_resume_host(chip);
564850 }
565851 #endif
852
+
853
+static const struct sdhci_ops sdhci_pci_o2_ops = {
854
+	.set_clock = sdhci_pci_o2_set_clock,
855
+	.enable_dma = sdhci_pci_enable_dma,
856
+	.set_bus_width = sdhci_set_bus_width,
857
+	.reset = sdhci_reset,
858
+	.set_uhs_signaling = sdhci_set_uhs_signaling,
859
+};
860
+
861
+const struct sdhci_pci_fixes sdhci_o2 = {
862
+	.probe = sdhci_pci_o2_probe,
863
+	.quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
864
+	.quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD,
865
+	.probe_slot = sdhci_pci_o2_probe_slot,
866
+#ifdef CONFIG_PM_SLEEP
867
+	.resume = sdhci_pci_o2_resume,
868
+#endif
869
+	.ops = &sdhci_pci_o2_ops,
870
+	.priv_size = sizeof(struct o2_host),
871
+};