| .. | .. |
|---|
| 1 | +// SPDX-License-Identifier: GPL-2.0-only |
|---|
| 1 | 2 | /* |
|---|
| 2 | 3 | * Copyright (c) 2015 MediaTek Inc. |
|---|
| 3 | | - * |
|---|
| 4 | | - * This program is free software; you can redistribute it and/or modify |
|---|
| 5 | | - * it under the terms of the GNU General Public License version 2 as |
|---|
| 6 | | - * published by the Free Software Foundation. |
|---|
| 7 | | - * |
|---|
| 8 | | - * This program is distributed in the hope that it will be useful, |
|---|
| 9 | | - * but WITHOUT ANY WARRANTY; without even the implied warranty of |
|---|
| 10 | | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|---|
| 11 | | - * GNU General Public License for more details. |
|---|
| 12 | 4 | */ |
|---|
| 13 | 5 | |
|---|
| 14 | | -#include <drm/drmP.h> |
|---|
| 15 | 6 | #include <linux/clk.h> |
|---|
| 16 | 7 | #include <linux/component.h> |
|---|
| 8 | +#include <linux/module.h> |
|---|
| 17 | 9 | #include <linux/of_device.h> |
|---|
| 18 | 10 | #include <linux/of_irq.h> |
|---|
| 19 | 11 | #include <linux/platform_device.h> |
|---|
| 12 | +#include <linux/soc/mediatek/mtk-cmdq.h> |
|---|
| 20 | 13 | |
|---|
| 21 | 14 | #include "mtk_drm_crtc.h" |
|---|
| 22 | 15 | #include "mtk_drm_ddp_comp.h" |
|---|
| .. | .. |
|---|
| 133 | 126 | |
|---|
| 134 | 127 | static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width, |
|---|
| 135 | 128 | unsigned int height, unsigned int vrefresh, |
|---|
| 136 | | - unsigned int bpc) |
|---|
| 129 | + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) |
|---|
| 137 | 130 | { |
|---|
| 138 | 131 | unsigned int threshold; |
|---|
| 139 | 132 | unsigned int reg; |
|---|
| 140 | 133 | struct mtk_disp_rdma *rdma = comp_to_rdma(comp); |
|---|
| 141 | 134 | |
|---|
| 142 | | - rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xfff, width); |
|---|
| 143 | | - rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_1, 0xfffff, height); |
|---|
| 135 | + mtk_ddp_write_mask(cmdq_pkt, width, comp, |
|---|
| 136 | + DISP_REG_RDMA_SIZE_CON_0, 0xfff); |
|---|
| 137 | + mtk_ddp_write_mask(cmdq_pkt, height, comp, |
|---|
| 138 | + DISP_REG_RDMA_SIZE_CON_1, 0xfffff); |
|---|
| 144 | 139 | |
|---|
| 145 | 140 | /* |
|---|
| 146 | 141 | * Enable FIFO underflow since DSI and DPI can't be blocked. |
|---|
| .. | .. |
|---|
| 152 | 147 | reg = RDMA_FIFO_UNDERFLOW_EN | |
|---|
| 153 | 148 | RDMA_FIFO_PSEUDO_SIZE(RDMA_FIFO_SIZE(rdma)) | |
|---|
| 154 | 149 | RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold); |
|---|
| 155 | | - writel(reg, comp->regs + DISP_REG_RDMA_FIFO_CON); |
|---|
| 150 | + mtk_ddp_write(cmdq_pkt, reg, comp, DISP_REG_RDMA_FIFO_CON); |
|---|
| 156 | 151 | } |
|---|
| 157 | 152 | |
|---|
| 158 | 153 | static unsigned int rdma_fmt_convert(struct mtk_disp_rdma *rdma, |
|---|
| .. | .. |
|---|
| 198 | 193 | } |
|---|
| 199 | 194 | |
|---|
| 200 | 195 | static void mtk_rdma_layer_config(struct mtk_ddp_comp *comp, unsigned int idx, |
|---|
| 201 | | - struct mtk_plane_state *state) |
|---|
| 196 | + struct mtk_plane_state *state, |
|---|
| 197 | + struct cmdq_pkt *cmdq_pkt) |
|---|
| 202 | 198 | { |
|---|
| 203 | 199 | struct mtk_disp_rdma *rdma = comp_to_rdma(comp); |
|---|
| 204 | 200 | struct mtk_plane_pending_state *pending = &state->pending; |
|---|
| .. | .. |
|---|
| 208 | 204 | unsigned int con; |
|---|
| 209 | 205 | |
|---|
| 210 | 206 | con = rdma_fmt_convert(rdma, fmt); |
|---|
| 211 | | - writel_relaxed(con, comp->regs + DISP_RDMA_MEM_CON); |
|---|
| 207 | + mtk_ddp_write_relaxed(cmdq_pkt, con, comp, DISP_RDMA_MEM_CON); |
|---|
| 212 | 208 | |
|---|
| 213 | 209 | if (fmt == DRM_FORMAT_UYVY || fmt == DRM_FORMAT_YUYV) { |
|---|
| 214 | | - rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, |
|---|
| 215 | | - RDMA_MATRIX_ENABLE, RDMA_MATRIX_ENABLE); |
|---|
| 216 | | - rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, |
|---|
| 217 | | - RDMA_MATRIX_INT_MTX_SEL, |
|---|
| 218 | | - RDMA_MATRIX_INT_MTX_BT601_to_RGB); |
|---|
| 210 | + mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_ENABLE, comp, |
|---|
| 211 | + DISP_REG_RDMA_SIZE_CON_0, |
|---|
| 212 | + RDMA_MATRIX_ENABLE); |
|---|
| 213 | + mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_INT_MTX_BT601_to_RGB, |
|---|
| 214 | + comp, DISP_REG_RDMA_SIZE_CON_0, |
|---|
| 215 | + RDMA_MATRIX_INT_MTX_SEL); |
|---|
| 219 | 216 | } else { |
|---|
| 220 | | - rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, |
|---|
| 221 | | - RDMA_MATRIX_ENABLE, 0); |
|---|
| 217 | + mtk_ddp_write_mask(cmdq_pkt, 0, comp, |
|---|
| 218 | + DISP_REG_RDMA_SIZE_CON_0, |
|---|
| 219 | + RDMA_MATRIX_ENABLE); |
|---|
| 222 | 220 | } |
|---|
| 221 | + mtk_ddp_write_relaxed(cmdq_pkt, addr, comp, DISP_RDMA_MEM_START_ADDR); |
|---|
| 222 | + mtk_ddp_write_relaxed(cmdq_pkt, pitch, comp, DISP_RDMA_MEM_SRC_PITCH); |
|---|
| 223 | + mtk_ddp_write(cmdq_pkt, RDMA_MEM_GMC, comp, |
|---|
| 224 | + DISP_RDMA_MEM_GMC_SETTING_0); |
|---|
| 225 | + mtk_ddp_write_mask(cmdq_pkt, RDMA_MODE_MEMORY, comp, |
|---|
| 226 | + DISP_REG_RDMA_GLOBAL_CON, RDMA_MODE_MEMORY); |
|---|
| 223 | 227 | |
|---|
| 224 | | - writel_relaxed(addr, comp->regs + DISP_RDMA_MEM_START_ADDR); |
|---|
| 225 | | - writel_relaxed(pitch, comp->regs + DISP_RDMA_MEM_SRC_PITCH); |
|---|
| 226 | | - writel(RDMA_MEM_GMC, comp->regs + DISP_RDMA_MEM_GMC_SETTING_0); |
|---|
| 227 | | - rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON, |
|---|
| 228 | | - RDMA_MODE_MEMORY, RDMA_MODE_MEMORY); |
|---|
| 229 | 228 | } |
|---|
| 230 | 229 | |
|---|
| 231 | 230 | static const struct mtk_ddp_comp_funcs mtk_disp_rdma_funcs = { |
|---|
| .. | .. |
|---|
| 295 | 294 | ret = mtk_ddp_comp_init(dev, dev->of_node, &priv->ddp_comp, comp_id, |
|---|
| 296 | 295 | &mtk_disp_rdma_funcs); |
|---|
| 297 | 296 | if (ret) { |
|---|
| 298 | | - dev_err(dev, "Failed to initialize component: %d\n", ret); |
|---|
| 297 | + if (ret != -EPROBE_DEFER) |
|---|
| 298 | + dev_err(dev, "Failed to initialize component: %d\n", |
|---|
| 299 | + ret); |
|---|
| 300 | + |
|---|
| 299 | 301 | return ret; |
|---|
| 300 | 302 | } |
|---|
| 301 | 303 | |
|---|