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2024-05-10 23fa18eaa71266feff7ba8d83022d9e1cc83c65a 
 kernel/drivers/gpu/drm/armada/armada_plane.c
....@@ -1,15 +1,14 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * Copyright (C) 2012 Russell King
34  *  Rewritten from the dovefb driver, and Armada510 manuals.
4
- *
5
- * This program is free software; you can redistribute it and/or modify
6
- * it under the terms of the GNU General Public License version 2 as
7
- * published by the Free Software Foundation.
85  */
9
-#include <drm/drmP.h>
6
+
107 #include <drm/drm_atomic.h>
118 #include <drm/drm_atomic_helper.h>
9
+#include <drm/drm_fourcc.h>
1210 #include <drm/drm_plane_helper.h>
11
+
1312 #include "armada_crtc.h"
1413 #include "armada_drm.h"
1514 #include "armada_fb.h"
....@@ -79,23 +78,6 @@
7978 	}
8079 }
8180 
82
-static unsigned armada_drm_crtc_calc_fb(struct drm_plane_state *state,
83
-	struct armada_regs *regs, bool interlaced)
84
-{
85
-	u16 pitches[3];
86
-	u32 addrs[2][3];
87
-	unsigned i = 0;
88
-
89
-	armada_drm_plane_calc(state, addrs, pitches, interlaced);
90
-
91
-	/* write offset, base, and pitch */
92
-	armada_reg_queue_set(regs, i, addrs[0][0], LCD_CFG_GRA_START_ADDR0);
93
-	armada_reg_queue_set(regs, i, addrs[1][0], LCD_CFG_GRA_START_ADDR1);
94
-	armada_reg_queue_mod(regs, i, pitches[0], 0xffff, LCD_CFG_GRA_PITCH);
95
-
96
-	return i;
97
-}
98
-
9981 int armada_drm_plane_prepare_fb(struct drm_plane *plane,
10082 	struct drm_plane_state *state)
10183 {
....@@ -126,20 +108,50 @@
126108 int armada_drm_plane_atomic_check(struct drm_plane *plane,
127109 	struct drm_plane_state *state)
128110 {
129
-	if (state->fb && !WARN_ON(!state->crtc)) {
130
-		struct drm_crtc *crtc = state->crtc;
131
-		struct drm_crtc_state *crtc_state;
111
+	struct armada_plane_state *st = to_armada_plane_state(state);
112
+	struct drm_crtc *crtc = state->crtc;
113
+	struct drm_crtc_state *crtc_state;
114
+	bool interlace;
115
+	int ret;
132116 
133
-		if (state->state)
134
-			crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
135
-		else
136
-			crtc_state = crtc->state;
137
-		return drm_atomic_helper_check_plane_state(state, crtc_state,
138
-							   0, INT_MAX,
139
-							   true, false);
140
-	} else {
117
+	if (!state->fb || WARN_ON(!state->crtc)) {
141118 		state->visible = false;
119
+		return 0;
142120 	}
121
+
122
+	if (state->state)
123
+		crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
124
+	else
125
+		crtc_state = crtc->state;
126
+
127
+	ret = drm_atomic_helper_check_plane_state(state, crtc_state, 0,
128
+						  INT_MAX, true, false);
129
+	if (ret)
130
+		return ret;
131
+
132
+	interlace = crtc_state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE;
133
+	if (interlace) {
134
+		if ((state->dst.y1 | state->dst.y2) & 1)
135
+			return -EINVAL;
136
+		st->src_hw = drm_rect_height(&state->src) >> 17;
137
+		st->dst_yx = state->dst.y1 >> 1;
138
+		st->dst_hw = drm_rect_height(&state->dst) >> 1;
139
+	} else {
140
+		st->src_hw = drm_rect_height(&state->src) >> 16;
141
+		st->dst_yx = state->dst.y1;
142
+		st->dst_hw = drm_rect_height(&state->dst);
143
+	}
144
+
145
+	st->src_hw <<= 16;
146
+	st->src_hw |= drm_rect_width(&state->src) >> 16;
147
+	st->dst_yx <<= 16;
148
+	st->dst_yx |= state->dst.x1 & 0x0000ffff;
149
+	st->dst_hw <<= 16;
150
+	st->dst_hw |= drm_rect_width(&state->dst) & 0x0000ffff;
151
+
152
+	armada_drm_plane_calc(state, st->addrs, st->pitches, interlace);
153
+	st->interlace = interlace;
154
+
143155 	return 0;
144156 }
145157 
....@@ -173,21 +185,25 @@
173185 			val |= CFG_PDWN256x24;
174186 		armada_reg_queue_mod(regs, idx, 0, val, LCD_SPU_SRAM_PARA1);
175187 	}
176
-	val = armada_rect_hw_fp(&state->src);
177
-	if (armada_rect_hw_fp(&old_state->src) != val)
188
+	val = armada_src_hw(state);
189
+	if (armada_src_hw(old_state) != val)
178190 		armada_reg_queue_set(regs, idx, val, LCD_SPU_GRA_HPXL_VLN);
179
-	val = armada_rect_yx(&state->dst);
180
-	if (armada_rect_yx(&old_state->dst) != val)
191
+	val = armada_dst_yx(state);
192
+	if (armada_dst_yx(old_state) != val)
181193 		armada_reg_queue_set(regs, idx, val, LCD_SPU_GRA_OVSA_HPXL_VLN);
182
-	val = armada_rect_hw(&state->dst);
183
-	if (armada_rect_hw(&old_state->dst) != val)
194
+	val = armada_dst_hw(state);
195
+	if (armada_dst_hw(old_state) != val)
184196 		armada_reg_queue_set(regs, idx, val, LCD_SPU_GZM_HPXL_VLN);
185197 	if (old_state->src.x1 != state->src.x1 ||
186198 	    old_state->src.y1 != state->src.y1 ||
187199 	    old_state->fb != state->fb ||
188200 	    state->crtc->state->mode_changed) {
189
-		idx += armada_drm_crtc_calc_fb(state, regs + idx,
190
-					       dcrtc->interlaced);
201
+		armada_reg_queue_set(regs, idx, armada_addr(state, 0, 0),
202
+				     LCD_CFG_GRA_START_ADDR0);
203
+		armada_reg_queue_set(regs, idx, armada_addr(state, 1, 0),
204
+				     LCD_CFG_GRA_START_ADDR1);
205
+		armada_reg_queue_mod(regs, idx, armada_pitch(state, 0), 0xffff,
206
+				     LCD_CFG_GRA_PITCH);
191207 	}
192208 	if (old_state->fb != state->fb ||
193209 	    state->crtc->state->mode_changed) {
....@@ -197,7 +213,7 @@
197213 			cfg |= CFG_PALETTE_ENA;
198214 		if (state->visible)
199215 			cfg |= CFG_GRA_ENA;
200
-		if (dcrtc->interlaced)
216
+		if (to_armada_plane_state(state)->interlace)
201217 			cfg |= CFG_GRA_FTOGGLE;
202218 		cfg_mask = CFG_GRAFORMAT |
203219 			   CFG_GRA_MOD(CFG_SWAPRB | CFG_SWAPUV |
....@@ -248,7 +264,7 @@
248264 	/* Disable plane and power down most RAMs and FIFOs */
249265 	armada_reg_queue_mod(regs, idx, 0, CFG_GRA_ENA, LCD_SPU_DMA_CTRL0);
250266 	armada_reg_queue_mod(regs, idx, CFG_PDWN256x32 | CFG_PDWN256x24 |
251
-			     CFG_PDWN256x8 | CFG_PDWN32x32 | CFG_PDWN64x66,
267
+			     CFG_PDWN32x32 | CFG_PDWN64x66,
252268 			     0, LCD_SPU_SRAM_PARA1);
253269 
254270 	dcrtc->regs_idx += idx;
....@@ -262,12 +278,37 @@
262278 	.atomic_disable	= armada_drm_primary_plane_atomic_disable,
263279 };
264280 
281
+void armada_plane_reset(struct drm_plane *plane)
282
+{
283
+	struct armada_plane_state *st;
284
+	if (plane->state)
285
+		__drm_atomic_helper_plane_destroy_state(plane->state);
286
+	kfree(plane->state);
287
+	st = kzalloc(sizeof(*st), GFP_KERNEL);
288
+	if (st)
289
+		__drm_atomic_helper_plane_reset(plane, &st->base);
290
+}
291
+
292
+struct drm_plane_state *armada_plane_duplicate_state(struct drm_plane *plane)
293
+{
294
+	struct armada_plane_state *st;
295
+
296
+	if (WARN_ON(!plane->state))
297
+		return NULL;
298
+
299
+	st = kmemdup(plane->state, sizeof(*st), GFP_KERNEL);
300
+	if (st)
301
+		__drm_atomic_helper_plane_duplicate_state(plane, &st->base);
302
+
303
+	return &st->base;
304
+}
305
+
265306 static const struct drm_plane_funcs armada_primary_plane_funcs = {
266307 	.update_plane	= drm_atomic_helper_update_plane,
267308 	.disable_plane	= drm_atomic_helper_disable_plane,
268309 	.destroy	= drm_primary_helper_destroy,
269
-	.reset		= drm_atomic_helper_plane_reset,
270
-	.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
310
+	.reset		= armada_plane_reset,
311
+	.atomic_duplicate_state = armada_plane_duplicate_state,
271312 	.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
272313 };
273314