~hc/RK356X_SDK_RELEASE.git

..	..	@@ -22,9 +22,10 @@
22	22	*/
23	23
24	24	#include <linux/firmware.h>
25		-#include <drm/drmP.h>
	25	+
26	26	#include "amdgpu.h"
27	27	#include "amdgpu_vcn.h"
	28	+#include "amdgpu_pm.h"
28	29	#include "soc15.h"
29	30	#include "soc15d.h"
30	31	#include "soc15_common.h"
..	..	@@ -36,14 +37,24 @@
36	37	#include "mmhub/mmhub_9_1_sh_mask.h"
37	38
38	39	#include "ivsrcid/vcn/irqsrcs_vcn_1_0.h"
	40	+#include "jpeg_v1_0.h"
	41	+#include "vcn_v1_0.h"
	42	+
	43	+#define mmUVD_RBC_XX_IB_REG_CHECK_1_0 0x05ab
	44	+#define mmUVD_RBC_XX_IB_REG_CHECK_1_0_BASE_IDX 1
	45	+#define mmUVD_REG_XX_MASK_1_0 0x05ac
	46	+#define mmUVD_REG_XX_MASK_1_0_BASE_IDX 1
39	47
40	48	static int vcn_v1_0_stop(struct amdgpu_device *adev);
41	49	static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);
42	50	static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev);
43		-static void vcn_v1_0_set_jpeg_ring_funcs(struct amdgpu_device *adev);
44	51	static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev);
45		-static void vcn_v1_0_jpeg_ring_set_patch_ring(struct amdgpu_ring *ring, uint32_t ptr);
46	52	static int vcn_v1_0_set_powergating_state(void *handle, enum amd_powergating_state state);
	53	+static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
	54	+ int inst_idx, struct dpg_pause_state *new_state);
	55	+
	56	+static void vcn_v1_0_idle_work_handler(struct work_struct *work);
	57	+static void vcn_v1_0_ring_begin_use(struct amdgpu_ring *ring);
47	58
48	59	/**
49	60	* vcn_v1_0_early_init - set function pointers
..	..	@@ -56,12 +67,14 @@
56	67	{
57	68	struct amdgpu_device adev = (struct amdgpu_device )handle;
58	69
	70	+ adev->vcn.num_vcn_inst = 1;
59	71	adev->vcn.num_enc_rings = 2;
60	72
61	73	vcn_v1_0_set_dec_ring_funcs(adev);
62	74	vcn_v1_0_set_enc_ring_funcs(adev);
63		- vcn_v1_0_set_jpeg_ring_funcs(adev);
64	75	vcn_v1_0_set_irq_funcs(adev);
	76	+
	77	+ jpeg_v1_0_early_init(handle);
65	78
66	79	return 0;
67	80	}
..	..	@@ -80,26 +93,25 @@
80	93	struct amdgpu_device adev = (struct amdgpu_device )handle;
81	94
82	95	/* VCN DEC TRAP */
83		- r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, VCN_1_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.irq);
	96	+ r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
	97	+ VCN_1_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst->irq);
84	98	if (r)
85	99	return r;
86	100
87	101	/* VCN ENC TRAP */
88	102	for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
89	103	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, i + VCN_1_0__SRCID__UVD_ENC_GENERAL_PURPOSE,
90		- &adev->vcn.irq);
	104	+ &adev->vcn.inst->irq);
91	105	if (r)
92	106	return r;
93	107	}
94	108
95		- /* VCN JPEG TRAP */
96		- r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 126, &adev->vcn.irq);
97		- if (r)
98		- return r;
99		-
100	109	r = amdgpu_vcn_sw_init(adev);
101	110	if (r)
102	111	return r;
	112	+
	113	+ /* Override the work func */
	114	+ adev->vcn.idle_work.work.func = vcn_v1_0_idle_work_handler;
103	115
104	116	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
105	117	const struct common_firmware_header *hdr;
..	..	@@ -108,32 +120,43 @@
108	120	adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
109	121	adev->firmware.fw_size +=
110	122	ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
111		- DRM_INFO("PSP loading VCN firmware\n");
	123	+ dev_info(adev->dev, "Will use PSP to load VCN firmware\n");
112	124	}
113	125
114	126	r = amdgpu_vcn_resume(adev);
115	127	if (r)
116	128	return r;
117	129
118		- ring = &adev->vcn.ring_dec;
	130	+ ring = &adev->vcn.inst->ring_dec;
119	131	sprintf(ring->name, "vcn_dec");
120		- r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
	132	+ r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,
	133	+ AMDGPU_RING_PRIO_DEFAULT);
121	134	if (r)
122	135	return r;
123	136
	137	+ adev->vcn.internal.scratch9 = adev->vcn.inst->external.scratch9 =
	138	+ SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9);
	139	+ adev->vcn.internal.data0 = adev->vcn.inst->external.data0 =
	140	+ SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0);
	141	+ adev->vcn.internal.data1 = adev->vcn.inst->external.data1 =
	142	+ SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1);
	143	+ adev->vcn.internal.cmd = adev->vcn.inst->external.cmd =
	144	+ SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD);
	145	+ adev->vcn.internal.nop = adev->vcn.inst->external.nop =
	146	+ SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP);
	147	+
124	148	for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
125		- ring = &adev->vcn.ring_enc[i];
	149	+ ring = &adev->vcn.inst->ring_enc[i];
126	150	sprintf(ring->name, "vcn_enc%d", i);
127		- r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
	151	+ r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,
	152	+ AMDGPU_RING_PRIO_DEFAULT);
128	153	if (r)
129	154	return r;
130	155	}
131	156
132		- ring = &adev->vcn.ring_jpeg;
133		- sprintf(ring->name, "vcn_jpeg");
134		- r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
135		- if (r)
136		- return r;
	157	+ adev->vcn.pause_dpg_mode = vcn_v1_0_pause_dpg_mode;
	158	+
	159	+ r = jpeg_v1_0_sw_init(handle);
137	160
138	161	return r;
139	162	}
..	..	@@ -154,6 +177,8 @@
154	177	if (r)
155	178	return r;
156	179
	180	+ jpeg_v1_0_sw_fini(handle);
	181	+
157	182	r = amdgpu_vcn_sw_fini(adev);
158	183
159	184	return r;
..	..	@@ -169,37 +194,29 @@
169	194	static int vcn_v1_0_hw_init(void *handle)
170	195	{
171	196	struct amdgpu_device adev = (struct amdgpu_device )handle;
172		- struct amdgpu_ring *ring = &adev->vcn.ring_dec;
	197	+ struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
173	198	int i, r;
174	199
175		- ring->ready = true;
176		- r = amdgpu_ring_test_ring(ring);
177		- if (r) {
178		- ring->ready = false;
	200	+ r = amdgpu_ring_test_helper(ring);
	201	+ if (r)
179	202	goto done;
180		- }
181	203
182	204	for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
183		- ring = &adev->vcn.ring_enc[i];
184		- ring->ready = true;
185		- r = amdgpu_ring_test_ring(ring);
186		- if (r) {
187		- ring->ready = false;
	205	+ ring = &adev->vcn.inst->ring_enc[i];
	206	+ r = amdgpu_ring_test_helper(ring);
	207	+ if (r)
188	208	goto done;
189		- }
190	209	}
191	210
192		- ring = &adev->vcn.ring_jpeg;
193		- ring->ready = true;
194		- r = amdgpu_ring_test_ring(ring);
195		- if (r) {
196		- ring->ready = false;
	211	+ ring = &adev->jpeg.inst->ring_dec;
	212	+ r = amdgpu_ring_test_helper(ring);
	213	+ if (r)
197	214	goto done;
198		- }
199	215
200	216	done:
201	217	if (!r)
202		- DRM_INFO("VCN decode and encode initialized successfully.\n");
	218	+ DRM_INFO("VCN decode and encode initialized successfully(under %s).\n",
	219	+ (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode");
203	220
204	221	return r;
205	222	}
..	..	@@ -214,12 +231,14 @@
214	231	static int vcn_v1_0_hw_fini(void *handle)
215	232	{
216	233	struct amdgpu_device adev = (struct amdgpu_device )handle;
217		- struct amdgpu_ring *ring = &adev->vcn.ring_dec;
218	234
219		- if (RREG32_SOC15(VCN, 0, mmUVD_STATUS))
	235	+ cancel_delayed_work_sync(&adev->vcn.idle_work);
	236	+
	237	+ if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) \|\|
	238	+ (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
	239	+ RREG32_SOC15(VCN, 0, mmUVD_STATUS))) {
220	240	vcn_v1_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
221		-
222		- ring->ready = false;
	241	+ }
223	242
224	243	return 0;
225	244	}
..	..	@@ -235,6 +254,13 @@
235	254	{
236	255	int r;
237	256	struct amdgpu_device adev = (struct amdgpu_device )handle;
	257	+ bool idle_work_unexecuted;
	258	+
	259	+ idle_work_unexecuted = cancel_delayed_work_sync(&adev->vcn.idle_work);
	260	+ if (idle_work_unexecuted) {
	261	+ if (adev->pm.dpm_enabled)
	262	+ amdgpu_dpm_enable_uvd(adev, false);
	263	+ }
238	264
239	265	r = vcn_v1_0_hw_fini(adev);
240	266	if (r)
..	..	@@ -267,17 +293,18 @@
267	293	}
268	294
269	295	/**
270		- * vcn_v1_0_mc_resume - memory controller programming
	296	+ * vcn_v1_0_mc_resume_spg_mode - memory controller programming
271	297	*
272	298	* @adev: amdgpu_device pointer
273	299	*
274	300	* Let the VCN memory controller know it's offsets
275	301	*/
276		-static void vcn_v1_0_mc_resume(struct amdgpu_device *adev)
	302	+static void vcn_v1_0_mc_resume_spg_mode(struct amdgpu_device *adev)
277	303	{
278	304	uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
279	305	uint32_t offset;
280	306
	307	+ /* cache window 0: fw */
281	308	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
282	309	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
283	310	(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo));
..	..	@@ -287,9 +314,9 @@
287	314	offset = 0;
288	315	} else {
289	316	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
290		- lower_32_bits(adev->vcn.gpu_addr));
	317	+ lower_32_bits(adev->vcn.inst->gpu_addr));
291	318	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
292		- upper_32_bits(adev->vcn.gpu_addr));
	319	+ upper_32_bits(adev->vcn.inst->gpu_addr));
293	320	offset = size;
294	321	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
295	322	AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
..	..	@@ -297,20 +324,21 @@
297	324
298	325	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);
299	326
	327	+ /* cache window 1: stack */
300	328	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
301		- lower_32_bits(adev->vcn.gpu_addr + offset));
	329	+ lower_32_bits(adev->vcn.inst->gpu_addr + offset));
302	330	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
303		- upper_32_bits(adev->vcn.gpu_addr + offset));
	331	+ upper_32_bits(adev->vcn.inst->gpu_addr + offset));
304	332	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0);
305		- WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_HEAP_SIZE);
	333	+ WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
306	334
	335	+ /* cache window 2: context */
307	336	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
308		- lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_HEAP_SIZE));
	337	+ lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
309	338	WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
310		- upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_HEAP_SIZE));
	339	+ upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
311	340	WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0);
312		- WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2,
313		- AMDGPU_VCN_STACK_SIZE + (AMDGPU_VCN_SESSION_SIZE * 40));
	341	+ WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
314	342
315	343	WREG32_SOC15(UVD, 0, mmUVD_UDEC_ADDR_CONFIG,
316	344	adev->gfx.config.gb_addr_config);
..	..	@@ -318,6 +346,96 @@
318	346	adev->gfx.config.gb_addr_config);
319	347	WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG,
320	348	adev->gfx.config.gb_addr_config);
	349	+ WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG,
	350	+ adev->gfx.config.gb_addr_config);
	351	+ WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG,
	352	+ adev->gfx.config.gb_addr_config);
	353	+ WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG,
	354	+ adev->gfx.config.gb_addr_config);
	355	+ WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG,
	356	+ adev->gfx.config.gb_addr_config);
	357	+ WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG,
	358	+ adev->gfx.config.gb_addr_config);
	359	+ WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG,
	360	+ adev->gfx.config.gb_addr_config);
	361	+ WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG,
	362	+ adev->gfx.config.gb_addr_config);
	363	+ WREG32_SOC15(UVD, 0, mmUVD_JPEG_ADDR_CONFIG,
	364	+ adev->gfx.config.gb_addr_config);
	365	+ WREG32_SOC15(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG,
	366	+ adev->gfx.config.gb_addr_config);
	367	+}
	368	+
	369	+static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device *adev)
	370	+{
	371	+ uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
	372	+ uint32_t offset;
	373	+
	374	+ /* cache window 0: fw */
	375	+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
	376	+ WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
	377	+ (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo),
	378	+ 0xFFFFFFFF, 0);
	379	+ WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
	380	+ (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi),
	381	+ 0xFFFFFFFF, 0);
	382	+ WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0,
	383	+ 0xFFFFFFFF, 0);
	384	+ offset = 0;
	385	+ } else {
	386	+ WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
	387	+ lower_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0);
	388	+ WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
	389	+ upper_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0);
	390	+ offset = size;
	391	+ WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
	392	+ AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0xFFFFFFFF, 0);
	393	+ }
	394	+
	395	+ WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size, 0xFFFFFFFF, 0);
	396	+
	397	+ /* cache window 1: stack */
	398	+ WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
	399	+ lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0);
	400	+ WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
	401	+ upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0);
	402	+ WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0,
	403	+ 0xFFFFFFFF, 0);
	404	+ WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE,
	405	+ 0xFFFFFFFF, 0);
	406	+
	407	+ /* cache window 2: context */
	408	+ WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
	409	+ lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),
	410	+ 0xFFFFFFFF, 0);
	411	+ WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
	412	+ upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),
	413	+ 0xFFFFFFFF, 0);
	414	+ WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0, 0xFFFFFFFF, 0);
	415	+ WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE,
	416	+ 0xFFFFFFFF, 0);
	417	+
	418	+ /* VCN global tiling registers */
	419	+ WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_ADDR_CONFIG,
	420	+ adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
	421	+ WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG,
	422	+ adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
	423	+ WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG,
	424	+ adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
	425	+ WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG,
	426	+ adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
	427	+ WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG,
	428	+ adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
	429	+ WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG,
	430	+ adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
	431	+ WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG,
	432	+ adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
	433	+ WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG,
	434	+ adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
	435	+ WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG,
	436	+ adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
	437	+ WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG,
	438	+ adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
321	439	}
322	440
323	441	/**
..	..	@@ -520,10 +638,63 @@
520	638	WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
521	639	}
522	640
	641	+static void vcn_v1_0_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel)
	642	+{
	643	+ uint32_t reg_data = 0;
	644	+
	645	+ /* disable JPEG CGC */
	646	+ if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
	647	+ reg_data = 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
	648	+ else
	649	+ reg_data = 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
	650	+ reg_data \|= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
	651	+ reg_data \|= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
	652	+ WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmJPEG_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel);
	653	+
	654	+ WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmJPEG_CGC_GATE, 0, 0xFFFFFFFF, sram_sel);
	655	+
	656	+ /* enable sw clock gating control */
	657	+ if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
	658	+ reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
	659	+ else
	660	+ reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
	661	+ reg_data \|= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
	662	+ reg_data \|= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
	663	+ reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK \|
	664	+ UVD_CGC_CTRL__UDEC_CM_MODE_MASK \|
	665	+ UVD_CGC_CTRL__UDEC_IT_MODE_MASK \|
	666	+ UVD_CGC_CTRL__UDEC_DB_MODE_MASK \|
	667	+ UVD_CGC_CTRL__UDEC_MP_MODE_MASK \|
	668	+ UVD_CGC_CTRL__SYS_MODE_MASK \|
	669	+ UVD_CGC_CTRL__UDEC_MODE_MASK \|
	670	+ UVD_CGC_CTRL__MPEG2_MODE_MASK \|
	671	+ UVD_CGC_CTRL__REGS_MODE_MASK \|
	672	+ UVD_CGC_CTRL__RBC_MODE_MASK \|
	673	+ UVD_CGC_CTRL__LMI_MC_MODE_MASK \|
	674	+ UVD_CGC_CTRL__LMI_UMC_MODE_MASK \|
	675	+ UVD_CGC_CTRL__IDCT_MODE_MASK \|
	676	+ UVD_CGC_CTRL__MPRD_MODE_MASK \|
	677	+ UVD_CGC_CTRL__MPC_MODE_MASK \|
	678	+ UVD_CGC_CTRL__LBSI_MODE_MASK \|
	679	+ UVD_CGC_CTRL__LRBBM_MODE_MASK \|
	680	+ UVD_CGC_CTRL__WCB_MODE_MASK \|
	681	+ UVD_CGC_CTRL__VCPU_MODE_MASK \|
	682	+ UVD_CGC_CTRL__SCPU_MODE_MASK);
	683	+ WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel);
	684	+
	685	+ /* turn off clock gating */
	686	+ WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_CGC_GATE, 0, 0xFFFFFFFF, sram_sel);
	687	+
	688	+ /* turn on SUVD clock gating */
	689	+ WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SUVD_CGC_GATE, 1, 0xFFFFFFFF, sram_sel);
	690	+
	691	+ /* turn on sw mode in UVD_SUVD_CGC_CTRL */
	692	+ WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SUVD_CGC_CTRL, 0, 0xFFFFFFFF, sram_sel);
	693	+}
	694	+
523	695	static void vcn_1_0_disable_static_power_gating(struct amdgpu_device *adev)
524	696	{
525	697	uint32_t data = 0;
526		- int ret;
527	698
528	699	if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
529	700	data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
..	..	@@ -539,7 +710,7 @@
539	710	\| 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
540	711
541	712	WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
542		- SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON, 0xFFFFFF, ret);
	713	+ SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON, 0xFFFFFF);
543	714	} else {
544	715	data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
545	716	\| 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
..	..	@@ -553,7 +724,7 @@
553	724	\| 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
554	725	\| 1 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
555	726	WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
556		- SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFFFFF, ret);
	727	+ SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFFFFF);
557	728	}
558	729
559	730	/* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS , UVDU_PWR_STATUS are 0 (power on) */
..	..	@@ -569,7 +740,6 @@
569	740	static void vcn_1_0_enable_static_power_gating(struct amdgpu_device *adev)
570	741	{
571	742	uint32_t data = 0;
572		- int ret;
573	743
574	744	if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
575	745	/* Before power off, this indicator has to be turned on */
..	..	@@ -604,7 +774,7 @@
604	774	\| 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT
605	775	\| 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT
606	776	\| 2 << UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT);
607		- SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFFFFF, ret);
	777	+ SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFFFFF);
608	778	}
609	779	}
610	780
..	..	@@ -615,9 +785,9 @@
615	785	*
616	786	* Setup and start the VCN block
617	787	*/
618		-static int vcn_v1_0_start(struct amdgpu_device *adev)
	788	+static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev)
619	789	{
620		- struct amdgpu_ring *ring = &adev->vcn.ring_dec;
	790	+ struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
621	791	uint32_t rb_bufsz, tmp;
622	792	uint32_t lmi_swap_cntl;
623	793	int i, j, r;
..	..	@@ -626,41 +796,24 @@
626	796	lmi_swap_cntl = 0;
627	797
628	798	vcn_1_0_disable_static_power_gating(adev);
	799	+
	800	+ tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) \| UVD_STATUS__UVD_BUSY;
	801	+ WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
	802	+
629	803	/* disable clock gating */
630	804	vcn_v1_0_disable_clock_gating(adev);
631		-
632		- vcn_v1_0_mc_resume(adev);
633	805
634	806	/* disable interupt */
635	807	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
636	808	~UVD_MASTINT_EN__VCPU_EN_MASK);
637	809
638		- /* stall UMC and register bus before resetting VCPU */
639		- WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2),
640		- UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
641		- ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
642		- mdelay(1);
643		-
644		- /* put LMI, VCPU, RBC etc... into reset */
645		- WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET,
646		- UVD_SOFT_RESET__LMI_SOFT_RESET_MASK \|
647		- UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK \|
648		- UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK \|
649		- UVD_SOFT_RESET__RBC_SOFT_RESET_MASK \|
650		- UVD_SOFT_RESET__CSM_SOFT_RESET_MASK \|
651		- UVD_SOFT_RESET__CXW_SOFT_RESET_MASK \|
652		- UVD_SOFT_RESET__TAP_SOFT_RESET_MASK \|
653		- UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
654		- mdelay(5);
655		-
656	810	/* initialize VCN memory controller */
657		- WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL,
658		- (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) \|
659		- UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK \|
660		- UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK \|
661		- UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK \|
662		- UVD_LMI_CTRL__REQ_MODE_MASK \|
663		- 0x00100000L);
	811	+ tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL);
	812	+ WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp \|
	813	+ UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK \|
	814	+ UVD_LMI_CTRL__MASK_MC_URGENT_MASK \|
	815	+ UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK \|
	816	+ UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
664	817
665	818	#ifdef __BIG_ENDIAN
666	819	/* swap (8 in 32) RB and IB */
..	..	@@ -668,41 +821,61 @@
668	821	#endif
669	822	WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
670	823
671		- WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0, 0x40c2040);
672		- WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA1, 0x0);
673		- WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0, 0x40c2040);
674		- WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB1, 0x0);
675		- WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_ALU, 0);
676		- WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX, 0x88);
	824	+ tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL);
	825	+ tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
	826	+ tmp \|= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
	827	+ WREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL, tmp);
677	828
678		- /* take all subblocks out of reset, except VCPU */
679		- WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET,
680		- UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
681		- mdelay(5);
	829	+ WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0,
	830	+ ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) \|
	831	+ (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) \|
	832	+ (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) \|
	833	+ (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
	834	+
	835	+ WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0,
	836	+ ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) \|
	837	+ (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) \|
	838	+ (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) \|
	839	+ (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
	840	+
	841	+ WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX,
	842	+ ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) \|
	843	+ (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) \|
	844	+ (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
	845	+
	846	+ vcn_v1_0_mc_resume_spg_mode(adev);
	847	+
	848	+ WREG32_SOC15(UVD, 0, mmUVD_REG_XX_MASK_1_0, 0x10);
	849	+ WREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK_1_0,
	850	+ RREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK_1_0) \| 0x3);
682	851
683	852	/* enable VCPU clock */
684		- WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL,
685		- UVD_VCPU_CNTL__CLK_EN_MASK);
	853	+ WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK);
	854	+
	855	+ /* boot up the VCPU */
	856	+ WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
	857	+ ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
686	858
687	859	/* enable UMC */
688	860	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
689	861	~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
690	862
691		- /* boot up the VCPU */
692		- WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, 0);
693		- mdelay(10);
	863	+ tmp = RREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET);
	864	+ tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
	865	+ tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
	866	+ WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, tmp);
694	867
695	868	for (i = 0; i < 10; ++i) {
696	869	uint32_t status;
697	870
698	871	for (j = 0; j < 100; ++j) {
699	872	status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);
700		- if (status & 2)
	873	+ if (status & UVD_STATUS__IDLE)
701	874	break;
702	875	mdelay(10);
703	876	}
704	877	r = 0;
705		- if (status & 2)
	878	+ if (status & UVD_STATUS__IDLE)
706	879	break;
707	880
708	881	DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n");
..	..	@@ -722,19 +895,22 @@
722	895	}
723	896	/* enable master interrupt */
724	897	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
725		- (UVD_MASTINT_EN__VCPU_EN_MASK\|UVD_MASTINT_EN__SYS_EN_MASK),
726		- ~(UVD_MASTINT_EN__VCPU_EN_MASK\|UVD_MASTINT_EN__SYS_EN_MASK));
	898	+ UVD_MASTINT_EN__VCPU_EN_MASK, ~UVD_MASTINT_EN__VCPU_EN_MASK);
727	899
728		- /* clear the bit 4 of VCN_STATUS */
729		- WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0,
730		- ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
	900	+ /* enable system interrupt for JRBC, TODO: move to set interrupt*/
	901	+ WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SYS_INT_EN),
	902	+ UVD_SYS_INT_EN__UVD_JRBC_EN_MASK,
	903	+ ~UVD_SYS_INT_EN__UVD_JRBC_EN_MASK);
	904	+
	905	+ /* clear the busy bit of UVD_STATUS */
	906	+ tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) & ~UVD_STATUS__UVD_BUSY;
	907	+ WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
731	908
732	909	/* force RBC into idle state */
733	910	rb_bufsz = order_base_2(ring->ring_size);
734	911	tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
735	912	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
736	913	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
737		- tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
738	914	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
739	915	tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
740	916	WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
..	..	@@ -746,7 +922,7 @@
746	922	WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR,
747	923	(upper_32_bits(ring->gpu_addr) >> 2));
748	924
749		- /* programm the RB_BASE for ring buffer */
	925	+ /* program the RB_BASE for ring buffer */
750	926	WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
751	927	lower_32_bits(ring->gpu_addr));
752	928	WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
..	..	@@ -755,6 +931,8 @@
755	931	/* Initialize the ring buffer's read and write pointers */
756	932	WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
757	933
	934	+ WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0);
	935	+
758	936	ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
759	937	WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
760	938	lower_32_bits(ring->wptr));
..	..	@@ -762,37 +940,178 @@
762	940	WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
763	941	~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
764	942
765		- ring = &adev->vcn.ring_enc[0];
	943	+ ring = &adev->vcn.inst->ring_enc[0];
766	944	WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
767	945	WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
768	946	WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
769	947	WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
770	948	WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
771	949
772		- ring = &adev->vcn.ring_enc[1];
	950	+ ring = &adev->vcn.inst->ring_enc[1];
773	951	WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
774	952	WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
775	953	WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
776	954	WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
777	955	WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
778	956
779		- ring = &adev->vcn.ring_jpeg;
780		- WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
781		- WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L \| 0x00000002L));
782		- WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, lower_32_bits(ring->gpu_addr));
783		- WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, upper_32_bits(ring->gpu_addr));
784		- WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, 0);
785		- WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, 0);
786		- WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L);
787		-
788		- /* initialize wptr */
789		- ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
790		-
791		- /* copy patch commands to the jpeg ring */
792		- vcn_v1_0_jpeg_ring_set_patch_ring(ring,
793		- (ring->wptr + ring->max_dw * amdgpu_sched_hw_submission));
	957	+ jpeg_v1_0_start(adev, 0);
794	958
795	959	return 0;
	960	+}
	961	+
	962	+static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev)
	963	+{
	964	+ struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
	965	+ uint32_t rb_bufsz, tmp;
	966	+ uint32_t lmi_swap_cntl;
	967	+
	968	+ /* disable byte swapping */
	969	+ lmi_swap_cntl = 0;
	970	+
	971	+ vcn_1_0_enable_static_power_gating(adev);
	972	+
	973	+ /* enable dynamic power gating mode */
	974	+ tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);
	975	+ tmp \|= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
	976	+ tmp \|= UVD_POWER_STATUS__UVD_PG_EN_MASK;
	977	+ WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp);
	978	+
	979	+ /* enable clock gating */
	980	+ vcn_v1_0_clock_gating_dpg_mode(adev, 0);
	981	+
	982	+ /* enable VCPU clock */
	983	+ tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
	984	+ tmp \|= UVD_VCPU_CNTL__CLK_EN_MASK;
	985	+ tmp \|= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK;
	986	+ WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CNTL, tmp, 0xFFFFFFFF, 0);
	987	+
	988	+ /* disable interupt */
	989	+ WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MASTINT_EN,
	990	+ 0, UVD_MASTINT_EN__VCPU_EN_MASK, 0);
	991	+
	992	+ /* initialize VCN memory controller */
	993	+ WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL,
	994	+ (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) \|
	995	+ UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK \|
	996	+ UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK \|
	997	+ UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK \|
	998	+ UVD_LMI_CTRL__REQ_MODE_MASK \|
	999	+ UVD_LMI_CTRL__CRC_RESET_MASK \|
	1000	+ UVD_LMI_CTRL__MASK_MC_URGENT_MASK \|
	1001	+ 0x00100000L, 0xFFFFFFFF, 0);
	1002	+
	1003	+#ifdef __BIG_ENDIAN
	1004	+ /* swap (8 in 32) RB and IB */
	1005	+ lmi_swap_cntl = 0xa;
	1006	+#endif
	1007	+ WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl, 0xFFFFFFFF, 0);
	1008	+
	1009	+ WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_CNTL,
	1010	+ 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0xFFFFFFFF, 0);
	1011	+
	1012	+ WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUXA0,
	1013	+ ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) \|
	1014	+ (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) \|
	1015	+ (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) \|
	1016	+ (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0xFFFFFFFF, 0);
	1017	+
	1018	+ WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUXB0,
	1019	+ ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) \|
	1020	+ (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) \|
	1021	+ (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) \|
	1022	+ (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0xFFFFFFFF, 0);
	1023	+
	1024	+ WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUX,
	1025	+ ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) \|
	1026	+ (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) \|
	1027	+ (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0xFFFFFFFF, 0);
	1028	+
	1029	+ vcn_v1_0_mc_resume_dpg_mode(adev);
	1030	+
	1031	+ WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_REG_XX_MASK, 0x10, 0xFFFFFFFF, 0);
	1032	+ WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK, 0x3, 0xFFFFFFFF, 0);
	1033	+
	1034	+ /* boot up the VCPU */
	1035	+ WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SOFT_RESET, 0, 0xFFFFFFFF, 0);
	1036	+
	1037	+ /* enable UMC */
	1038	+ WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL2,
	1039	+ 0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT,
	1040	+ 0xFFFFFFFF, 0);
	1041	+
	1042	+ /* enable master interrupt */
	1043	+ WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MASTINT_EN,
	1044	+ UVD_MASTINT_EN__VCPU_EN_MASK, UVD_MASTINT_EN__VCPU_EN_MASK, 0);
	1045	+
	1046	+ vcn_v1_0_clock_gating_dpg_mode(adev, 1);
	1047	+ /* setup mmUVD_LMI_CTRL */
	1048	+ WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL,
	1049	+ (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) \|
	1050	+ UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK \|
	1051	+ UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK \|
	1052	+ UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK \|
	1053	+ UVD_LMI_CTRL__REQ_MODE_MASK \|
	1054	+ UVD_LMI_CTRL__CRC_RESET_MASK \|
	1055	+ UVD_LMI_CTRL__MASK_MC_URGENT_MASK \|
	1056	+ 0x00100000L, 0xFFFFFFFF, 1);
	1057	+
	1058	+ tmp = adev->gfx.config.gb_addr_config;
	1059	+ /* setup VCN global tiling registers */
	1060	+ WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_JPEG_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1);
	1061	+ WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1);
	1062	+
	1063	+ /* enable System Interrupt for JRBC */
	1064	+ WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SYS_INT_EN,
	1065	+ UVD_SYS_INT_EN__UVD_JRBC_EN_MASK, 0xFFFFFFFF, 1);
	1066	+
	1067	+ /* force RBC into idle state */
	1068	+ rb_bufsz = order_base_2(ring->ring_size);
	1069	+ tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
	1070	+ tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
	1071	+ tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
	1072	+ tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
	1073	+ tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
	1074	+ WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
	1075	+
	1076	+ /* set the write pointer delay */
	1077	+ WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);
	1078	+
	1079	+ /* set the wb address */
	1080	+ WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR,
	1081	+ (upper_32_bits(ring->gpu_addr) >> 2));
	1082	+
	1083	+ /* program the RB_BASE for ring buffer */
	1084	+ WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
	1085	+ lower_32_bits(ring->gpu_addr));
	1086	+ WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
	1087	+ upper_32_bits(ring->gpu_addr));
	1088	+
	1089	+ /* Initialize the ring buffer's read and write pointers */
	1090	+ WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
	1091	+
	1092	+ WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0);
	1093	+
	1094	+ ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
	1095	+ WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
	1096	+ lower_32_bits(ring->wptr));
	1097	+
	1098	+ WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
	1099	+ ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
	1100	+
	1101	+ jpeg_v1_0_start(adev, 1);
	1102	+
	1103	+ return 0;
	1104	+}
	1105	+
	1106	+static int vcn_v1_0_start(struct amdgpu_device *adev)
	1107	+{
	1108	+ int r;
	1109	+
	1110	+ if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
	1111	+ r = vcn_v1_0_start_dpg_mode(adev);
	1112	+ else
	1113	+ r = vcn_v1_0_start_spg_mode(adev);
	1114	+ return r;
796	1115	}
797	1116
798	1117	/**
..	..	@@ -802,33 +1121,217 @@
802	1121	*
803	1122	* stop the VCN block
804	1123	*/
805		-static int vcn_v1_0_stop(struct amdgpu_device *adev)
	1124	+static int vcn_v1_0_stop_spg_mode(struct amdgpu_device *adev)
806	1125	{
807		- /* force RBC into idle state */
808		- WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, 0x11010101);
	1126	+ int tmp;
809	1127
810		- /* Stall UMC and register bus before resetting VCPU */
811		- WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2),
812		- UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
813		- ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
814		- mdelay(1);
	1128	+ SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);
	1129	+
	1130	+ tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK \|
	1131	+ UVD_LMI_STATUS__READ_CLEAN_MASK \|
	1132	+ UVD_LMI_STATUS__WRITE_CLEAN_MASK \|
	1133	+ UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
	1134	+ SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp);
815	1135
816	1136	/* put VCPU into reset */
817		- WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET,
818		- UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
819		- mdelay(5);
	1137	+ WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
	1138	+ UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
	1139	+ ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
	1140	+
	1141	+ tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK \|
	1142	+ UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
	1143	+ SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp);
820	1144
821	1145	/* disable VCPU clock */
822		- WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, 0x0);
	1146	+ WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
	1147	+ ~UVD_VCPU_CNTL__CLK_EN_MASK);
823	1148
824		- /* Unstall UMC and register bus */
825		- WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
826		- ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
	1149	+ /* reset LMI UMC/LMI */
	1150	+ WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
	1151	+ UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK,
	1152	+ ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
827	1153
828		- WREG32_SOC15(VCN, 0, mmUVD_STATUS, 0);
	1154	+ WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
	1155	+ UVD_SOFT_RESET__LMI_SOFT_RESET_MASK,
	1156	+ ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK);
	1157	+
	1158	+ WREG32_SOC15(UVD, 0, mmUVD_STATUS, 0);
829	1159
830	1160	vcn_v1_0_enable_clock_gating(adev);
831	1161	vcn_1_0_enable_static_power_gating(adev);
	1162	+ return 0;
	1163	+}
	1164	+
	1165	+static int vcn_v1_0_stop_dpg_mode(struct amdgpu_device *adev)
	1166	+{
	1167	+ uint32_t tmp;
	1168	+
	1169	+ /* Wait for power status to be UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF */
	1170	+ SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
	1171	+ UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
	1172	+ UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
	1173	+
	1174	+ /* wait for read ptr to be equal to write ptr */
	1175	+ tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
	1176	+ SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF);
	1177	+
	1178	+ tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
	1179	+ SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF);
	1180	+
	1181	+ tmp = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
	1182	+ SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_JRBC_RB_RPTR, tmp, 0xFFFFFFFF);
	1183	+
	1184	+ tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
	1185	+ SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF);
	1186	+
	1187	+ SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
	1188	+ UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
	1189	+ UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
	1190	+
	1191	+ /* disable dynamic power gating mode */
	1192	+ WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
	1193	+ ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
	1194	+
	1195	+ return 0;
	1196	+}
	1197	+
	1198	+static int vcn_v1_0_stop(struct amdgpu_device *adev)
	1199	+{
	1200	+ int r;
	1201	+
	1202	+ if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
	1203	+ r = vcn_v1_0_stop_dpg_mode(adev);
	1204	+ else
	1205	+ r = vcn_v1_0_stop_spg_mode(adev);
	1206	+
	1207	+ return r;
	1208	+}
	1209	+
	1210	+static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
	1211	+ int inst_idx, struct dpg_pause_state *new_state)
	1212	+{
	1213	+ int ret_code;
	1214	+ uint32_t reg_data = 0;
	1215	+ uint32_t reg_data2 = 0;
	1216	+ struct amdgpu_ring *ring;
	1217	+
	1218	+ /* pause/unpause if state is changed */
	1219	+ if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
	1220	+ DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d",
	1221	+ adev->vcn.inst[inst_idx].pause_state.fw_based,
	1222	+ adev->vcn.inst[inst_idx].pause_state.jpeg,
	1223	+ new_state->fw_based, new_state->jpeg);
	1224	+
	1225	+ reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &
	1226	+ (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
	1227	+
	1228	+ if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {
	1229	+ ret_code = 0;
	1230	+
	1231	+ if (!(reg_data & UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK))
	1232	+ ret_code = SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
	1233	+ UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
	1234	+ UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
	1235	+
	1236	+ if (!ret_code) {
	1237	+ /* pause DPG non-jpeg */
	1238	+ reg_data \|= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
	1239	+ WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
	1240	+ SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE,
	1241	+ UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
	1242	+ UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
	1243	+
	1244	+ /* Restore */
	1245	+ ring = &adev->vcn.inst->ring_enc[0];
	1246	+ WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
	1247	+ WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
	1248	+ WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
	1249	+ WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
	1250	+ WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
	1251	+
	1252	+ ring = &adev->vcn.inst->ring_enc[1];
	1253	+ WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
	1254	+ WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
	1255	+ WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
	1256	+ WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
	1257	+ WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
	1258	+
	1259	+ ring = &adev->vcn.inst->ring_dec;
	1260	+ WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
	1261	+ RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);
	1262	+ SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
	1263	+ UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,
	1264	+ UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
	1265	+ }
	1266	+ } else {
	1267	+ /* unpause dpg non-jpeg, no need to wait */
	1268	+ reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
	1269	+ WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
	1270	+ }
	1271	+ adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
	1272	+ }
	1273	+
	1274	+ /* pause/unpause if state is changed */
	1275	+ if (adev->vcn.inst[inst_idx].pause_state.jpeg != new_state->jpeg) {
	1276	+ DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d",
	1277	+ adev->vcn.inst[inst_idx].pause_state.fw_based,
	1278	+ adev->vcn.inst[inst_idx].pause_state.jpeg,
	1279	+ new_state->fw_based, new_state->jpeg);
	1280	+
	1281	+ reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &
	1282	+ (~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK);
	1283	+
	1284	+ if (new_state->jpeg == VCN_DPG_STATE__PAUSE) {
	1285	+ ret_code = 0;
	1286	+
	1287	+ if (!(reg_data & UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK))
	1288	+ ret_code = SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
	1289	+ UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
	1290	+ UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
	1291	+
	1292	+ if (!ret_code) {
	1293	+ /* Make sure JPRG Snoop is disabled before sending the pause */
	1294	+ reg_data2 = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);
	1295	+ reg_data2 \|= UVD_POWER_STATUS__JRBC_SNOOP_DIS_MASK;
	1296	+ WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, reg_data2);
	1297	+
	1298	+ /* pause DPG jpeg */
	1299	+ reg_data \|= UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK;
	1300	+ WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
	1301	+ SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE,
	1302	+ UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK,
	1303	+ UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK);
	1304	+
	1305	+ /* Restore */
	1306	+ ring = &adev->jpeg.inst->ring_dec;
	1307	+ WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
	1308	+ WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL,
	1309	+ UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK \|
	1310	+ UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
	1311	+ WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
	1312	+ lower_32_bits(ring->gpu_addr));
	1313	+ WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
	1314	+ upper_32_bits(ring->gpu_addr));
	1315	+ WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, ring->wptr);
	1316	+ WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, ring->wptr);
	1317	+ WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL,
	1318	+ UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
	1319	+
	1320	+ ring = &adev->vcn.inst->ring_dec;
	1321	+ WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
	1322	+ RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);
	1323	+ SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
	1324	+ UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,
	1325	+ UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
	1326	+ }
	1327	+ } else {
	1328	+ /* unpause dpg jpeg, no need to wait */
	1329	+ reg_data &= ~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK;
	1330	+ WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
	1331	+ }
	1332	+ adev->vcn.inst[inst_idx].pause_state.jpeg = new_state->jpeg;
	1333	+ }
	1334	+
832	1335	return 0;
833	1336	}
834	1337
..	..	@@ -836,15 +1339,16 @@
836	1339	{
837	1340	struct amdgpu_device adev = (struct amdgpu_device )handle;
838	1341
839		- return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == 0x2);
	1342	+ return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);
840	1343	}
841	1344
842	1345	static int vcn_v1_0_wait_for_idle(void *handle)
843	1346	{
844	1347	struct amdgpu_device adev = (struct amdgpu_device )handle;
845		- int ret = 0;
	1348	+ int ret;
846	1349
847		- SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, 0x2, 0x2, ret);
	1350	+ ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE,
	1351	+ UVD_STATUS__IDLE);
848	1352
849	1353	return ret;
850	1354	}
..	..	@@ -853,7 +1357,7 @@
853	1357	enum amd_clockgating_state state)
854	1358	{
855	1359	struct amdgpu_device adev = (struct amdgpu_device )handle;
856		- bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
	1360	+ bool enable = (state == AMD_CG_STATE_GATE);
857	1361
858	1362	if (enable) {
859	1363	/* wait for STATUS to clear */
..	..	@@ -905,6 +1409,10 @@
905	1409	static void vcn_v1_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
906	1410	{
907	1411	struct amdgpu_device *adev = ring->adev;
	1412	+
	1413	+ if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
	1414	+ WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2,
	1415	+ lower_32_bits(ring->wptr) \| 0x80000000);
908	1416
909	1417	WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
910	1418	}
..	..	@@ -992,10 +1500,12 @@
992	1500	* Write ring commands to execute the indirect buffer
993	1501	*/
994	1502	static void vcn_v1_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
995		- struct amdgpu_ib *ib,
996		- unsigned vmid, bool ctx_switch)
	1503	+ struct amdgpu_job *job,
	1504	+ struct amdgpu_ib *ib,
	1505	+ uint32_t flags)
997	1506	{
998	1507	struct amdgpu_device *adev = ring->adev;
	1508	+ unsigned vmid = AMDGPU_JOB_GET_VMID(job);
999	1509
1000	1510	amdgpu_ring_write(ring,
1001	1511	PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0));
..	..	@@ -1041,7 +1551,7 @@
1041	1551	pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1042	1552
1043	1553	/* wait for register write */
1044		- data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2;
	1554	+ data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance;
1045	1555	data1 = lower_32_bits(pd_addr);
1046	1556	mask = 0xffffffff;
1047	1557	vcn_v1_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);
..	..	@@ -1074,7 +1584,7 @@
1074	1584	{
1075	1585	struct amdgpu_device *adev = ring->adev;
1076	1586
1077		- if (ring == &adev->vcn.ring_enc[0])
	1587	+ if (ring == &adev->vcn.inst->ring_enc[0])
1078	1588	return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR);
1079	1589	else
1080	1590	return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2);
..	..	@@ -1091,7 +1601,7 @@
1091	1601	{
1092	1602	struct amdgpu_device *adev = ring->adev;
1093	1603
1094		- if (ring == &adev->vcn.ring_enc[0])
	1604	+ if (ring == &adev->vcn.inst->ring_enc[0])
1095	1605	return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
1096	1606	else
1097	1607	return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
..	..	@@ -1108,7 +1618,7 @@
1108	1618	{
1109	1619	struct amdgpu_device *adev = ring->adev;
1110	1620
1111		- if (ring == &adev->vcn.ring_enc[0])
	1621	+ if (ring == &adev->vcn.inst->ring_enc[0])
1112	1622	WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR,
1113	1623	lower_32_bits(ring->wptr));
1114	1624	else
..	..	@@ -1150,8 +1660,12 @@
1150	1660	* Write enc ring commands to execute the indirect buffer
1151	1661	*/
1152	1662	static void vcn_v1_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1153		- struct amdgpu_ib *ib, unsigned int vmid, bool ctx_switch)
	1663	+ struct amdgpu_job *job,
	1664	+ struct amdgpu_ib *ib,
	1665	+ uint32_t flags)
1154	1666	{
	1667	+ unsigned vmid = AMDGPU_JOB_GET_VMID(job);
	1668	+
1155	1669	amdgpu_ring_write(ring, VCN_ENC_CMD_IB);
1156	1670	amdgpu_ring_write(ring, vmid);
1157	1671	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
..	..	@@ -1177,7 +1691,8 @@
1177	1691	pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1178	1692
1179	1693	/* wait for reg writes */
1180		- vcn_v1_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2,
	1694	+ vcn_v1_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 +
	1695	+ vmid * hub->ctx_addr_distance,
1181	1696	lower_32_bits(pd_addr), 0xffffffff);
1182	1697	}
1183	1698
..	..	@@ -1187,383 +1702,6 @@
1187	1702	amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
1188	1703	amdgpu_ring_write(ring, reg << 2);
1189	1704	amdgpu_ring_write(ring, val);
1190		-}
1191		-
1192		-
1193		-/**
1194		- * vcn_v1_0_jpeg_ring_get_rptr - get read pointer
1195		- *
1196		- * @ring: amdgpu_ring pointer
1197		- *
1198		- * Returns the current hardware read pointer
1199		- */
1200		-static uint64_t vcn_v1_0_jpeg_ring_get_rptr(struct amdgpu_ring *ring)
1201		-{
1202		- struct amdgpu_device *adev = ring->adev;
1203		-
1204		- return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR);
1205		-}
1206		-
1207		-/**
1208		- * vcn_v1_0_jpeg_ring_get_wptr - get write pointer
1209		- *
1210		- * @ring: amdgpu_ring pointer
1211		- *
1212		- * Returns the current hardware write pointer
1213		- */
1214		-static uint64_t vcn_v1_0_jpeg_ring_get_wptr(struct amdgpu_ring *ring)
1215		-{
1216		- struct amdgpu_device *adev = ring->adev;
1217		-
1218		- return RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
1219		-}
1220		-
1221		-/**
1222		- * vcn_v1_0_jpeg_ring_set_wptr - set write pointer
1223		- *
1224		- * @ring: amdgpu_ring pointer
1225		- *
1226		- * Commits the write pointer to the hardware
1227		- */
1228		-static void vcn_v1_0_jpeg_ring_set_wptr(struct amdgpu_ring *ring)
1229		-{
1230		- struct amdgpu_device *adev = ring->adev;
1231		-
1232		- WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
1233		-}
1234		-
1235		-/**
1236		- * vcn_v1_0_jpeg_ring_insert_start - insert a start command
1237		- *
1238		- * @ring: amdgpu_ring pointer
1239		- *
1240		- * Write a start command to the ring.
1241		- */
1242		-static void vcn_v1_0_jpeg_ring_insert_start(struct amdgpu_ring *ring)
1243		-{
1244		- struct amdgpu_device *adev = ring->adev;
1245		-
1246		- amdgpu_ring_write(ring,
1247		- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
1248		- amdgpu_ring_write(ring, 0x68e04);
1249		-
1250		- amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0));
1251		- amdgpu_ring_write(ring, 0x80010000);
1252		-}
1253		-
1254		-/**
1255		- * vcn_v1_0_jpeg_ring_insert_end - insert a end command
1256		- *
1257		- * @ring: amdgpu_ring pointer
1258		- *
1259		- * Write a end command to the ring.
1260		- */
1261		-static void vcn_v1_0_jpeg_ring_insert_end(struct amdgpu_ring *ring)
1262		-{
1263		- struct amdgpu_device *adev = ring->adev;
1264		-
1265		- amdgpu_ring_write(ring,
1266		- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
1267		- amdgpu_ring_write(ring, 0x68e04);
1268		-
1269		- amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0));
1270		- amdgpu_ring_write(ring, 0x00010000);
1271		-}
1272		-
1273		-/**
1274		- * vcn_v1_0_jpeg_ring_emit_fence - emit an fence & trap command
1275		- *
1276		- * @ring: amdgpu_ring pointer
1277		- * @fence: fence to emit
1278		- *
1279		- * Write a fence and a trap command to the ring.
1280		- */
1281		-static void vcn_v1_0_jpeg_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1282		- unsigned flags)
1283		-{
1284		- struct amdgpu_device *adev = ring->adev;
1285		-
1286		- WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1287		-
1288		- amdgpu_ring_write(ring,
1289		- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_DATA0), 0, 0, PACKETJ_TYPE0));
1290		- amdgpu_ring_write(ring, seq);
1291		-
1292		- amdgpu_ring_write(ring,
1293		- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_DATA1), 0, 0, PACKETJ_TYPE0));
1294		- amdgpu_ring_write(ring, seq);
1295		-
1296		- amdgpu_ring_write(ring,
1297		- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
1298		- amdgpu_ring_write(ring, lower_32_bits(addr));
1299		-
1300		- amdgpu_ring_write(ring,
1301		- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
1302		- amdgpu_ring_write(ring, upper_32_bits(addr));
1303		-
1304		- amdgpu_ring_write(ring,
1305		- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_CMD), 0, 0, PACKETJ_TYPE0));
1306		- amdgpu_ring_write(ring, 0x8);
1307		-
1308		- amdgpu_ring_write(ring,
1309		- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JPEG_GPCOM_CMD), 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4));
1310		- amdgpu_ring_write(ring, 0);
1311		-
1312		- amdgpu_ring_write(ring,
1313		- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0));
1314		- amdgpu_ring_write(ring, 0x01400200);
1315		-
1316		- amdgpu_ring_write(ring,
1317		- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0));
1318		- amdgpu_ring_write(ring, seq);
1319		-
1320		- amdgpu_ring_write(ring,
1321		- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
1322		- amdgpu_ring_write(ring, lower_32_bits(addr));
1323		-
1324		- amdgpu_ring_write(ring,
1325		- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
1326		- amdgpu_ring_write(ring, upper_32_bits(addr));
1327		-
1328		- amdgpu_ring_write(ring,
1329		- PACKETJ(0, 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE2));
1330		- amdgpu_ring_write(ring, 0xffffffff);
1331		-
1332		- amdgpu_ring_write(ring,
1333		- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
1334		- amdgpu_ring_write(ring, 0x3fbc);
1335		-
1336		- amdgpu_ring_write(ring,
1337		- PACKETJ(0, 0, 0, PACKETJ_TYPE0));
1338		- amdgpu_ring_write(ring, 0x1);
1339		-}
1340		-
1341		-/**
1342		- * vcn_v1_0_jpeg_ring_emit_ib - execute indirect buffer
1343		- *
1344		- * @ring: amdgpu_ring pointer
1345		- * @ib: indirect buffer to execute
1346		- *
1347		- * Write ring commands to execute the indirect buffer.
1348		- */
1349		-static void vcn_v1_0_jpeg_ring_emit_ib(struct amdgpu_ring *ring,
1350		- struct amdgpu_ib *ib,
1351		- unsigned vmid, bool ctx_switch)
1352		-{
1353		- struct amdgpu_device *adev = ring->adev;
1354		-
1355		- amdgpu_ring_write(ring,
1356		- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_IB_VMID), 0, 0, PACKETJ_TYPE0));
1357		- amdgpu_ring_write(ring, (vmid \| (vmid << 4)));
1358		-
1359		- amdgpu_ring_write(ring,
1360		- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JPEG_VMID), 0, 0, PACKETJ_TYPE0));
1361		- amdgpu_ring_write(ring, (vmid \| (vmid << 4)));
1362		-
1363		- amdgpu_ring_write(ring,
1364		- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
1365		- amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1366		-
1367		- amdgpu_ring_write(ring,
1368		- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
1369		- amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1370		-
1371		- amdgpu_ring_write(ring,
1372		- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_IB_SIZE), 0, 0, PACKETJ_TYPE0));
1373		- amdgpu_ring_write(ring, ib->length_dw);
1374		-
1375		- amdgpu_ring_write(ring,
1376		- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW), 0, 0, PACKETJ_TYPE0));
1377		- amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr));
1378		-
1379		- amdgpu_ring_write(ring,
1380		- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH), 0, 0, PACKETJ_TYPE0));
1381		- amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr));
1382		-
1383		- amdgpu_ring_write(ring,
1384		- PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2));
1385		- amdgpu_ring_write(ring, 0);
1386		-
1387		- amdgpu_ring_write(ring,
1388		- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0));
1389		- amdgpu_ring_write(ring, 0x01400200);
1390		-
1391		- amdgpu_ring_write(ring,
1392		- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0));
1393		- amdgpu_ring_write(ring, 0x2);
1394		-
1395		- amdgpu_ring_write(ring,
1396		- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_STATUS), 0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3));
1397		- amdgpu_ring_write(ring, 0x2);
1398		-}
1399		-
1400		-static void vcn_v1_0_jpeg_ring_emit_reg_wait(struct amdgpu_ring *ring,
1401		- uint32_t reg, uint32_t val,
1402		- uint32_t mask)
1403		-{
1404		- struct amdgpu_device *adev = ring->adev;
1405		- uint32_t reg_offset = (reg << 2);
1406		-
1407		- amdgpu_ring_write(ring,
1408		- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0));
1409		- amdgpu_ring_write(ring, 0x01400200);
1410		-
1411		- amdgpu_ring_write(ring,
1412		- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0));
1413		- amdgpu_ring_write(ring, val);
1414		-
1415		- amdgpu_ring_write(ring,
1416		- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
1417		- if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) \|\|
1418		- ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
1419		- amdgpu_ring_write(ring, 0);
1420		- amdgpu_ring_write(ring,
1421		- PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3));
1422		- } else {
1423		- amdgpu_ring_write(ring, reg_offset);
1424		- amdgpu_ring_write(ring,
1425		- PACKETJ(0, 0, 0, PACKETJ_TYPE3));
1426		- }
1427		- amdgpu_ring_write(ring, mask);
1428		-}
1429		-
1430		-static void vcn_v1_0_jpeg_ring_emit_vm_flush(struct amdgpu_ring *ring,
1431		- unsigned vmid, uint64_t pd_addr)
1432		-{
1433		- struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1434		- uint32_t data0, data1, mask;
1435		-
1436		- pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1437		-
1438		- /* wait for register write */
1439		- data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2;
1440		- data1 = lower_32_bits(pd_addr);
1441		- mask = 0xffffffff;
1442		- vcn_v1_0_jpeg_ring_emit_reg_wait(ring, data0, data1, mask);
1443		-}
1444		-
1445		-static void vcn_v1_0_jpeg_ring_emit_wreg(struct amdgpu_ring *ring,
1446		- uint32_t reg, uint32_t val)
1447		-{
1448		- struct amdgpu_device *adev = ring->adev;
1449		- uint32_t reg_offset = (reg << 2);
1450		-
1451		- amdgpu_ring_write(ring,
1452		- PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0));
1453		- if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) \|\|
1454		- ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
1455		- amdgpu_ring_write(ring, 0);
1456		- amdgpu_ring_write(ring,
1457		- PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0));
1458		- } else {
1459		- amdgpu_ring_write(ring, reg_offset);
1460		- amdgpu_ring_write(ring,
1461		- PACKETJ(0, 0, 0, PACKETJ_TYPE0));
1462		- }
1463		- amdgpu_ring_write(ring, val);
1464		-}
1465		-
1466		-static void vcn_v1_0_jpeg_ring_nop(struct amdgpu_ring *ring, uint32_t count)
1467		-{
1468		- int i;
1469		-
1470		- WARN_ON(ring->wptr % 2 \|\| count % 2);
1471		-
1472		- for (i = 0; i < count / 2; i++) {
1473		- amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
1474		- amdgpu_ring_write(ring, 0);
1475		- }
1476		-}
1477		-
1478		-static void vcn_v1_0_jpeg_ring_patch_wreg(struct amdgpu_ring ring, uint32_t ptr, uint32_t reg_offset, uint32_t val)
1479		-{
1480		- struct amdgpu_device *adev = ring->adev;
1481		- ring->ring[(*ptr)++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0);
1482		- if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) \|\|
1483		- ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
1484		- ring->ring[(*ptr)++] = 0;
1485		- ring->ring[(*ptr)++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0);
1486		- } else {
1487		- ring->ring[(*ptr)++] = reg_offset;
1488		- ring->ring[(*ptr)++] = PACKETJ(0, 0, 0, PACKETJ_TYPE0);
1489		- }
1490		- ring->ring[(*ptr)++] = val;
1491		-}
1492		-
1493		-static void vcn_v1_0_jpeg_ring_set_patch_ring(struct amdgpu_ring *ring, uint32_t ptr)
1494		-{
1495		- struct amdgpu_device *adev = ring->adev;
1496		-
1497		- uint32_t reg, reg_offset, val, mask, i;
1498		-
1499		- // 1st: program mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW
1500		- reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW);
1501		- reg_offset = (reg << 2);
1502		- val = lower_32_bits(ring->gpu_addr);
1503		- vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);
1504		-
1505		- // 2nd: program mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH
1506		- reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH);
1507		- reg_offset = (reg << 2);
1508		- val = upper_32_bits(ring->gpu_addr);
1509		- vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);
1510		-
1511		- // 3rd to 5th: issue MEM_READ commands
1512		- for (i = 0; i <= 2; i++) {
1513		- ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE2);
1514		- ring->ring[ptr++] = 0;
1515		- }
1516		-
1517		- // 6th: program mmUVD_JRBC_RB_CNTL register to enable NO_FETCH and RPTR write ability
1518		- reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL);
1519		- reg_offset = (reg << 2);
1520		- val = 0x13;
1521		- vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);
1522		-
1523		- // 7th: program mmUVD_JRBC_RB_REF_DATA
1524		- reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA);
1525		- reg_offset = (reg << 2);
1526		- val = 0x1;
1527		- vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);
1528		-
1529		- // 8th: issue conditional register read mmUVD_JRBC_RB_CNTL
1530		- reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL);
1531		- reg_offset = (reg << 2);
1532		- val = 0x1;
1533		- mask = 0x1;
1534		-
1535		- ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_COND_RD_TIMER), 0, 0, PACKETJ_TYPE0);
1536		- ring->ring[ptr++] = 0x01400200;
1537		- ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0);
1538		- ring->ring[ptr++] = val;
1539		- ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_EXTERNAL_REG_BASE), 0, 0, PACKETJ_TYPE0);
1540		- if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) \|\|
1541		- ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) {
1542		- ring->ring[ptr++] = 0;
1543		- ring->ring[ptr++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3);
1544		- } else {
1545		- ring->ring[ptr++] = reg_offset;
1546		- ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE3);
1547		- }
1548		- ring->ring[ptr++] = mask;
1549		-
1550		- //9th to 21st: insert no-op
1551		- for (i = 0; i <= 12; i++) {
1552		- ring->ring[ptr++] = PACKETJ(0, 0, 0, PACKETJ_TYPE6);
1553		- ring->ring[ptr++] = 0;
1554		- }
1555		-
1556		- //22nd: reset mmUVD_JRBC_RB_RPTR
1557		- reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_RPTR);
1558		- reg_offset = (reg << 2);
1559		- val = 0;
1560		- vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);
1561		-
1562		- //23rd: program mmUVD_JRBC_RB_CNTL to disable no_fetch
1563		- reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL);
1564		- reg_offset = (reg << 2);
1565		- val = 0x12;
1566		- vcn_v1_0_jpeg_ring_patch_wreg(ring, &ptr, reg_offset, val);
1567	1705	}
1568	1706
1569	1707	static int vcn_v1_0_set_interrupt_state(struct amdgpu_device *adev,
..	..	@@ -1582,16 +1720,13 @@
1582	1720
1583	1721	switch (entry->src_id) {
1584	1722	case 124:
1585		- amdgpu_fence_process(&adev->vcn.ring_dec);
	1723	+ amdgpu_fence_process(&adev->vcn.inst->ring_dec);
1586	1724	break;
1587	1725	case 119:
1588		- amdgpu_fence_process(&adev->vcn.ring_enc[0]);
	1726	+ amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]);
1589	1727	break;
1590	1728	case 120:
1591		- amdgpu_fence_process(&adev->vcn.ring_enc[1]);
1592		- break;
1593		- case 126:
1594		- amdgpu_fence_process(&adev->vcn.ring_jpeg);
	1729	+ amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]);
1595	1730	break;
1596	1731	default:
1597	1732	DRM_ERROR("Unhandled interrupt: %d %d\n",
..	..	@@ -1625,12 +1760,119 @@
1625	1760	* revisit this when there is a cleaner line between
1626	1761	* the smc and the hw blocks
1627	1762	*/
	1763	+ int ret;
1628	1764	struct amdgpu_device adev = (struct amdgpu_device )handle;
1629	1765
	1766	+ if(state == adev->vcn.cur_state)
	1767	+ return 0;
	1768	+
1630	1769	if (state == AMD_PG_STATE_GATE)
1631		- return vcn_v1_0_stop(adev);
	1770	+ ret = vcn_v1_0_stop(adev);
1632	1771	else
1633		- return vcn_v1_0_start(adev);
	1772	+ ret = vcn_v1_0_start(adev);
	1773	+
	1774	+ if(!ret)
	1775	+ adev->vcn.cur_state = state;
	1776	+ return ret;
	1777	+}
	1778	+
	1779	+static void vcn_v1_0_idle_work_handler(struct work_struct *work)
	1780	+{
	1781	+ struct amdgpu_device *adev =
	1782	+ container_of(work, struct amdgpu_device, vcn.idle_work.work);
	1783	+ unsigned int fences = 0, i;
	1784	+
	1785	+ for (i = 0; i < adev->vcn.num_enc_rings; ++i)
	1786	+ fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_enc[i]);
	1787	+
	1788	+ if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
	1789	+ struct dpg_pause_state new_state;
	1790	+
	1791	+ if (fences)
	1792	+ new_state.fw_based = VCN_DPG_STATE__PAUSE;
	1793	+ else
	1794	+ new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
	1795	+
	1796	+ if (amdgpu_fence_count_emitted(&adev->jpeg.inst->ring_dec))
	1797	+ new_state.jpeg = VCN_DPG_STATE__PAUSE;
	1798	+ else
	1799	+ new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
	1800	+
	1801	+ adev->vcn.pause_dpg_mode(adev, 0, &new_state);
	1802	+ }
	1803	+
	1804	+ fences += amdgpu_fence_count_emitted(&adev->jpeg.inst->ring_dec);
	1805	+ fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_dec);
	1806	+
	1807	+ if (fences == 0) {
	1808	+ amdgpu_gfx_off_ctrl(adev, true);
	1809	+ if (adev->pm.dpm_enabled)
	1810	+ amdgpu_dpm_enable_uvd(adev, false);
	1811	+ else
	1812	+ amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
	1813	+ AMD_PG_STATE_GATE);
	1814	+ } else {
	1815	+ schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
	1816	+ }
	1817	+}
	1818	+
	1819	+static void vcn_v1_0_ring_begin_use(struct amdgpu_ring *ring)
	1820	+{
	1821	+ struct amdgpu_device *adev = ring->adev;
	1822	+ bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.idle_work);
	1823	+
	1824	+ mutex_lock(&adev->vcn.vcn1_jpeg1_workaround);
	1825	+
	1826	+ if (amdgpu_fence_wait_empty(&ring->adev->jpeg.inst->ring_dec))
	1827	+ DRM_ERROR("VCN dec: jpeg dec ring may not be empty\n");
	1828	+
	1829	+ vcn_v1_0_set_pg_for_begin_use(ring, set_clocks);
	1830	+
	1831	+}
	1832	+
	1833	+void vcn_v1_0_set_pg_for_begin_use(struct amdgpu_ring *ring, bool set_clocks)
	1834	+{
	1835	+ struct amdgpu_device *adev = ring->adev;
	1836	+
	1837	+ if (set_clocks) {
	1838	+ amdgpu_gfx_off_ctrl(adev, false);
	1839	+ if (adev->pm.dpm_enabled)
	1840	+ amdgpu_dpm_enable_uvd(adev, true);
	1841	+ else
	1842	+ amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
	1843	+ AMD_PG_STATE_UNGATE);
	1844	+ }
	1845	+
	1846	+ if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
	1847	+ struct dpg_pause_state new_state;
	1848	+ unsigned int fences = 0, i;
	1849	+
	1850	+ for (i = 0; i < adev->vcn.num_enc_rings; ++i)
	1851	+ fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_enc[i]);
	1852	+
	1853	+ if (fences)
	1854	+ new_state.fw_based = VCN_DPG_STATE__PAUSE;
	1855	+ else
	1856	+ new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
	1857	+
	1858	+ if (amdgpu_fence_count_emitted(&adev->jpeg.inst->ring_dec))
	1859	+ new_state.jpeg = VCN_DPG_STATE__PAUSE;
	1860	+ else
	1861	+ new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
	1862	+
	1863	+ if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC)
	1864	+ new_state.fw_based = VCN_DPG_STATE__PAUSE;
	1865	+ else if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG)
	1866	+ new_state.jpeg = VCN_DPG_STATE__PAUSE;
	1867	+
	1868	+ adev->vcn.pause_dpg_mode(adev, 0, &new_state);
	1869	+ }
	1870	+}
	1871	+
	1872	+void vcn_v1_0_ring_end_use(struct amdgpu_ring *ring)
	1873	+{
	1874	+ schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
	1875	+ mutex_unlock(&ring->adev->vcn.vcn1_jpeg1_workaround);
1634	1876	}
1635	1877
1636	1878	static const struct amd_ip_funcs vcn_v1_0_ip_funcs = {
..	..	@@ -1657,7 +1899,8 @@
1657	1899	.type = AMDGPU_RING_TYPE_VCN_DEC,
1658	1900	.align_mask = 0xf,
1659	1901	.support_64bit_ptrs = false,
1660		- .vmhub = AMDGPU_MMHUB,
	1902	+ .no_user_fence = true,
	1903	+ .vmhub = AMDGPU_MMHUB_0,
1661	1904	.get_rptr = vcn_v1_0_dec_ring_get_rptr,
1662	1905	.get_wptr = vcn_v1_0_dec_ring_get_wptr,
1663	1906	.set_wptr = vcn_v1_0_dec_ring_set_wptr,
..	..	@@ -1678,8 +1921,8 @@
1678	1921	.insert_start = vcn_v1_0_dec_ring_insert_start,
1679	1922	.insert_end = vcn_v1_0_dec_ring_insert_end,
1680	1923	.pad_ib = amdgpu_ring_generic_pad_ib,
1681		- .begin_use = amdgpu_vcn_ring_begin_use,
1682		- .end_use = amdgpu_vcn_ring_end_use,
	1924	+ .begin_use = vcn_v1_0_ring_begin_use,
	1925	+ .end_use = vcn_v1_0_ring_end_use,
1683	1926	.emit_wreg = vcn_v1_0_dec_ring_emit_wreg,
1684	1927	.emit_reg_wait = vcn_v1_0_dec_ring_emit_reg_wait,
1685	1928	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
..	..	@@ -1690,7 +1933,8 @@
1690	1933	.align_mask = 0x3f,
1691	1934	.nop = VCN_ENC_CMD_NO_OP,
1692	1935	.support_64bit_ptrs = false,
1693		- .vmhub = AMDGPU_MMHUB,
	1936	+ .no_user_fence = true,
	1937	+ .vmhub = AMDGPU_MMHUB_0,
1694	1938	.get_rptr = vcn_v1_0_enc_ring_get_rptr,
1695	1939	.get_wptr = vcn_v1_0_enc_ring_get_wptr,
1696	1940	.set_wptr = vcn_v1_0_enc_ring_set_wptr,
..	..	@@ -1709,49 +1953,16 @@
1709	1953	.insert_nop = amdgpu_ring_insert_nop,
1710	1954	.insert_end = vcn_v1_0_enc_ring_insert_end,
1711	1955	.pad_ib = amdgpu_ring_generic_pad_ib,
1712		- .begin_use = amdgpu_vcn_ring_begin_use,
1713		- .end_use = amdgpu_vcn_ring_end_use,
	1956	+ .begin_use = vcn_v1_0_ring_begin_use,
	1957	+ .end_use = vcn_v1_0_ring_end_use,
1714	1958	.emit_wreg = vcn_v1_0_enc_ring_emit_wreg,
1715	1959	.emit_reg_wait = vcn_v1_0_enc_ring_emit_reg_wait,
1716	1960	.emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1717	1961	};
1718	1962
1719		-static const struct amdgpu_ring_funcs vcn_v1_0_jpeg_ring_vm_funcs = {
1720		- .type = AMDGPU_RING_TYPE_VCN_JPEG,
1721		- .align_mask = 0xf,
1722		- .nop = PACKET0(0x81ff, 0),
1723		- .support_64bit_ptrs = false,
1724		- .vmhub = AMDGPU_MMHUB,
1725		- .extra_dw = 64,
1726		- .get_rptr = vcn_v1_0_jpeg_ring_get_rptr,
1727		- .get_wptr = vcn_v1_0_jpeg_ring_get_wptr,
1728		- .set_wptr = vcn_v1_0_jpeg_ring_set_wptr,
1729		- .emit_frame_size =
1730		- 6 + 6 + /* hdp invalidate / flush */
1731		- SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
1732		- SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
1733		- 8 + /* vcn_v1_0_dec_ring_emit_vm_flush */
1734		- 14 + 14 + /* vcn_v1_0_dec_ring_emit_fence x2 vm fence */
1735		- 6,
1736		- .emit_ib_size = 22, /* vcn_v1_0_dec_ring_emit_ib */
1737		- .emit_ib = vcn_v1_0_jpeg_ring_emit_ib,
1738		- .emit_fence = vcn_v1_0_jpeg_ring_emit_fence,
1739		- .emit_vm_flush = vcn_v1_0_jpeg_ring_emit_vm_flush,
1740		- .test_ring = amdgpu_vcn_jpeg_ring_test_ring,
1741		- .test_ib = amdgpu_vcn_jpeg_ring_test_ib,
1742		- .insert_nop = vcn_v1_0_jpeg_ring_nop,
1743		- .insert_start = vcn_v1_0_jpeg_ring_insert_start,
1744		- .insert_end = vcn_v1_0_jpeg_ring_insert_end,
1745		- .pad_ib = amdgpu_ring_generic_pad_ib,
1746		- .begin_use = amdgpu_vcn_ring_begin_use,
1747		- .end_use = amdgpu_vcn_ring_end_use,
1748		- .emit_wreg = vcn_v1_0_jpeg_ring_emit_wreg,
1749		- .emit_reg_wait = vcn_v1_0_jpeg_ring_emit_reg_wait,
1750		-};
1751		-
1752	1963	static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev)
1753	1964	{
1754		- adev->vcn.ring_dec.funcs = &vcn_v1_0_dec_ring_vm_funcs;
	1965	+ adev->vcn.inst->ring_dec.funcs = &vcn_v1_0_dec_ring_vm_funcs;
1755	1966	DRM_INFO("VCN decode is enabled in VM mode\n");
1756	1967	}
1757	1968
..	..	@@ -1760,15 +1971,9 @@
1760	1971	int i;
1761	1972
1762	1973	for (i = 0; i < adev->vcn.num_enc_rings; ++i)
1763		- adev->vcn.ring_enc[i].funcs = &vcn_v1_0_enc_ring_vm_funcs;
	1974	+ adev->vcn.inst->ring_enc[i].funcs = &vcn_v1_0_enc_ring_vm_funcs;
1764	1975
1765	1976	DRM_INFO("VCN encode is enabled in VM mode\n");
1766		-}
1767		-
1768		-static void vcn_v1_0_set_jpeg_ring_funcs(struct amdgpu_device *adev)
1769		-{
1770		- adev->vcn.ring_jpeg.funcs = &vcn_v1_0_jpeg_ring_vm_funcs;
1771		- DRM_INFO("VCN jpeg decode is enabled in VM mode\n");
1772	1977	}
1773	1978
1774	1979	static const struct amdgpu_irq_src_funcs vcn_v1_0_irq_funcs = {
..	..	@@ -1778,8 +1983,8 @@
1778	1983
1779	1984	static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev)
1780	1985	{
1781		- adev->vcn.irq.num_types = adev->vcn.num_enc_rings + 1;
1782		- adev->vcn.irq.funcs = &vcn_v1_0_irq_funcs;
	1986	+ adev->vcn.inst->irq.num_types = adev->vcn.num_enc_rings + 2;
	1987	+ adev->vcn.inst->irq.funcs = &vcn_v1_0_irq_funcs;
1783	1988	}
1784	1989
1785	1990	const struct amdgpu_ip_block_version vcn_v1_0_ip_block =