disable pwm7

hc

2024-05-10 23fa18eaa71266feff7ba8d83022d9e1cc83c65a

 kernel/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
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@@ -27,25 +27,23 @@
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 #include "nbio/nbio_7_0_default.h"
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 #include "nbio/nbio_7_0_offset.h"
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 #include "nbio/nbio_7_0_sh_mask.h"
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+#include "nbio/nbio_7_0_smn.h"
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 #include "vega10_enum.h"
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+#include <uapi/linux/kfd_ioctl.h>
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 #define smnNBIF_MGCG_CTRL_LCLK	0x1013a05c
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-#define smnCPM_CONTROL                                                                                  0x11180460
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-#define smnPCIE_CNTL2                                                                                   0x11180070
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-
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-/* vega20 */
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-#define mmRCC_DEV0_EPF0_STRAP0_VG20                                                                         0x0011
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-#define mmRCC_DEV0_EPF0_STRAP0_VG20_BASE_IDX                                                                2
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+static void nbio_v7_0_remap_hdp_registers(struct amdgpu_device *adev)
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+{
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+	WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
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+		adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
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+	WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
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+		adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
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+}
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 static u32 nbio_v7_0_get_rev_id(struct amdgpu_device *adev)
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 {
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         u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
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-
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-	if (adev->asic_type == CHIP_VEGA20)
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-		tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0_VG20);
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-	else
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-		tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
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 	tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
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 	tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
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@@ -66,10 +64,9 @@
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 				struct amdgpu_ring *ring)
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 {
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 	if (!ring || !ring->funcs->emit_wreg)
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-		WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
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+		WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
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 	else
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-		amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
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-			NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0);
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+		amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
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 }
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71
 
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 static u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev)
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@@ -78,22 +75,38 @@
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 }
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 static void nbio_v7_0_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
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-					  bool use_doorbell, int doorbell_index)
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+			bool use_doorbell, int doorbell_index, int doorbell_size)
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 {
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 	u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
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 			SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);
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 	u32 doorbell_range = RREG32(reg);
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-	u32 range = 2;
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-
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-	if (adev->asic_type == CHIP_VEGA20)
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-		range = 8;
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 	if (use_doorbell) {
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 		doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
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-		doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, range);
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+		doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size);
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 	} else
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 		doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
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+
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+	WREG32(reg, doorbell_range);
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+}
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+
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+static void nbio_v7_0_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
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+					 int doorbell_index, int instance)
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+{
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+	u32 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE);
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+
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+	u32 doorbell_range = RREG32(reg);
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+
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+	if (use_doorbell) {
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+		doorbell_range = REG_SET_FIELD(doorbell_range,
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+					       BIF_MMSCH0_DOORBELL_RANGE, OFFSET,
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+					       doorbell_index);
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+		doorbell_range = REG_SET_FIELD(doorbell_range,
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+					       BIF_MMSCH0_DOORBELL_RANGE, SIZE, 8);
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+	} else
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+		doorbell_range = REG_SET_FIELD(doorbell_range,
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+					       BIF_MMSCH0_DOORBELL_RANGE, SIZE, 0);
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 	WREG32(reg, doorbell_range);
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 }
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@@ -145,9 +158,6 @@
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 						       bool enable)
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 {
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 	uint32_t def, data;
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-
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-	if (adev->asic_type == CHIP_VEGA20)
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-		return;
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 	/* NBIF_MGCG_CTRL_LCLK */
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 	def = data = RREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK);
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@@ -270,19 +280,12 @@
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 	.ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK,
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 };
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-static void nbio_v7_0_detect_hw_virt(struct amdgpu_device *adev)
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-{
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-	if (is_virtual_machine())	/* passthrough mode exclus sriov mod */
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-		adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
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-}
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-
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 static void nbio_v7_0_init_registers(struct amdgpu_device *adev)
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 {
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 }
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 const struct amdgpu_nbio_funcs nbio_v7_0_funcs = {
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-	.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg,
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 	.get_hdp_flush_req_offset = nbio_v7_0_get_hdp_flush_req_offset,
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 	.get_hdp_flush_done_offset = nbio_v7_0_get_hdp_flush_done_offset,
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 	.get_pcie_index_offset = nbio_v7_0_get_pcie_index_offset,
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@@ -292,6 +295,7 @@
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 	.hdp_flush = nbio_v7_0_hdp_flush,
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 	.get_memsize = nbio_v7_0_get_memsize,
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 	.sdma_doorbell_range = nbio_v7_0_sdma_doorbell_range,
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+	.vcn_doorbell_range = nbio_v7_0_vcn_doorbell_range,
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 	.enable_doorbell_aperture = nbio_v7_0_enable_doorbell_aperture,
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 	.enable_doorbell_selfring_aperture = nbio_v7_0_enable_doorbell_selfring_aperture,
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 	.ih_doorbell_range = nbio_v7_0_ih_doorbell_range,
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@@ -300,5 +304,5 @@
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 	.get_clockgating_state = nbio_v7_0_get_clockgating_state,
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 	.ih_control = nbio_v7_0_ih_control,
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 	.init_registers = nbio_v7_0_init_registers,
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-	.detect_hw_virt = nbio_v7_0_detect_hw_virt,
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+	.remap_hdp_registers = nbio_v7_0_remap_hdp_registers,
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 };