disable pwm7

hc

2024-05-10 23fa18eaa71266feff7ba8d83022d9e1cc83c65a

 kernel/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
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@@ -37,7 +37,6 @@
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 #include "gmc/gmc_8_2_sh_mask.h"
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 #include "oss/oss_3_0_d.h"
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 #include "oss/oss_3_0_sh_mask.h"
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-#include "gca/gfx_8_0_sh_mask.h"
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 #include "dce/dce_10_0_d.h"
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 #include "dce/dce_10_0_sh_mask.h"
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 #include "smu/smu_7_1_3_d.h"
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@@ -516,12 +515,13 @@
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 	/* wait until RCV_MSG become 3 */
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 	if (xgpu_vi_poll_msg(adev, IDH_FLR_NOTIFICATION_CMPL)) {
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-		pr_err("failed to recieve FLR_CMPL\n");
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+		pr_err("failed to receive FLR_CMPL\n");
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 		return;
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 	}
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 	/* Trigger recovery due to world switch failure */
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-	amdgpu_device_gpu_recover(adev, NULL, false);
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+	if (amdgpu_device_should_recover_gpu(adev))
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+		amdgpu_device_gpu_recover(adev, NULL);
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 }
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 static int xgpu_vi_set_mailbox_rcv_irq(struct amdgpu_device *adev,
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@@ -579,11 +579,11 @@
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 {
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 	int r;
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-	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 135, &adev->virt.rcv_irq);
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+	r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 135, &adev->virt.rcv_irq);
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 	if (r)
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 		return r;
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-	r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 138, &adev->virt.ack_irq);
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+	r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 138, &adev->virt.ack_irq);
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 	if (r) {
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 		amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);
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 		return r;