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2024-05-10 23fa18eaa71266feff7ba8d83022d9e1cc83c65a 
 kernel/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
....@@ -24,28 +24,309 @@
2424 #ifndef __AMDGPU_GFX_H__
2525 #define __AMDGPU_GFX_H__
2626 
27
-int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg);
28
-void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg);
27
+/*
28
+ * GFX stuff
29
+ */
30
+#include "clearstate_defs.h"
31
+#include "amdgpu_ring.h"
32
+#include "amdgpu_rlc.h"
2933 
30
-void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se,
31
-		unsigned max_sh);
34
+/* GFX current status */
35
+#define AMDGPU_GFX_NORMAL_MODE			0x00000000L
36
+#define AMDGPU_GFX_SAFE_MODE			0x00000001L
37
+#define AMDGPU_GFX_PG_DISABLED_MODE		0x00000002L
38
+#define AMDGPU_GFX_CG_DISABLED_MODE		0x00000004L
39
+#define AMDGPU_GFX_LBPW_DISABLED_MODE		0x00000008L
3240 
33
-void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev);
41
+#define AMDGPU_MAX_GFX_QUEUES KGD_MAX_QUEUES
42
+#define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES
3443 
35
-int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
36
-			     struct amdgpu_ring *ring,
37
-			     struct amdgpu_irq_src *irq);
44
+enum gfx_pipe_priority {
45
+	AMDGPU_GFX_PIPE_PRIO_NORMAL = 1,
46
+	AMDGPU_GFX_PIPE_PRIO_HIGH,
47
+	AMDGPU_GFX_PIPE_PRIO_MAX
48
+};
3849 
39
-void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring,
40
-			      struct amdgpu_irq_src *irq);
50
+#define AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM  0
51
+#define AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM  15
4152 
42
-void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev);
43
-int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
44
-			unsigned hpd_size);
53
+struct amdgpu_mec {
54
+	struct amdgpu_bo	*hpd_eop_obj;
55
+	u64			hpd_eop_gpu_addr;
56
+	struct amdgpu_bo	*mec_fw_obj;
57
+	u64			mec_fw_gpu_addr;
58
+	u32 num_mec;
59
+	u32 num_pipe_per_mec;
60
+	u32 num_queue_per_pipe;
61
+	void			*mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1];
4562 
46
-int amdgpu_gfx_compute_mqd_sw_init(struct amdgpu_device *adev,
47
-				   unsigned mqd_size);
48
-void amdgpu_gfx_compute_mqd_sw_fini(struct amdgpu_device *adev);
63
+	/* These are the resources for which amdgpu takes ownership */
64
+	DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
65
+};
66
+
67
+enum amdgpu_unmap_queues_action {
68
+	PREEMPT_QUEUES = 0,
69
+	RESET_QUEUES,
70
+	DISABLE_PROCESS_QUEUES,
71
+	PREEMPT_QUEUES_NO_UNMAP,
72
+};
73
+
74
+struct kiq_pm4_funcs {
75
+	/* Support ASIC-specific kiq pm4 packets*/
76
+	void (*kiq_set_resources)(struct amdgpu_ring *kiq_ring,
77
+					uint64_t queue_mask);
78
+	void (*kiq_map_queues)(struct amdgpu_ring *kiq_ring,
79
+					struct amdgpu_ring *ring);
80
+	void (*kiq_unmap_queues)(struct amdgpu_ring *kiq_ring,
81
+				 struct amdgpu_ring *ring,
82
+				 enum amdgpu_unmap_queues_action action,
83
+				 u64 gpu_addr, u64 seq);
84
+	void (*kiq_query_status)(struct amdgpu_ring *kiq_ring,
85
+					struct amdgpu_ring *ring,
86
+					u64 addr,
87
+					u64 seq);
88
+	void (*kiq_invalidate_tlbs)(struct amdgpu_ring *kiq_ring,
89
+				uint16_t pasid, uint32_t flush_type,
90
+				bool all_hub);
91
+	/* Packet sizes */
92
+	int set_resources_size;
93
+	int map_queues_size;
94
+	int unmap_queues_size;
95
+	int query_status_size;
96
+	int invalidate_tlbs_size;
97
+};
98
+
99
+struct amdgpu_kiq {
100
+	u64			eop_gpu_addr;
101
+	struct amdgpu_bo	*eop_obj;
102
+	spinlock_t              ring_lock;
103
+	struct amdgpu_ring	ring;
104
+	struct amdgpu_irq_src	irq;
105
+	const struct kiq_pm4_funcs *pmf;
106
+};
107
+
108
+/*
109
+ * GPU scratch registers structures, functions & helpers
110
+ */
111
+struct amdgpu_scratch {
112
+	unsigned		num_reg;
113
+	uint32_t                reg_base;
114
+	uint32_t		free_mask;
115
+};
116
+
117
+/*
118
+ * GFX configurations
119
+ */
120
+#define AMDGPU_GFX_MAX_SE 4
121
+#define AMDGPU_GFX_MAX_SH_PER_SE 2
122
+
123
+struct amdgpu_rb_config {
124
+	uint32_t rb_backend_disable;
125
+	uint32_t user_rb_backend_disable;
126
+	uint32_t raster_config;
127
+	uint32_t raster_config_1;
128
+};
129
+
130
+struct gb_addr_config {
131
+	uint16_t pipe_interleave_size;
132
+	uint8_t num_pipes;
133
+	uint8_t max_compress_frags;
134
+	uint8_t num_banks;
135
+	uint8_t num_se;
136
+	uint8_t num_rb_per_se;
137
+	uint8_t num_pkrs;
138
+};
139
+
140
+struct amdgpu_gfx_config {
141
+	unsigned max_shader_engines;
142
+	unsigned max_tile_pipes;
143
+	unsigned max_cu_per_sh;
144
+	unsigned max_sh_per_se;
145
+	unsigned max_backends_per_se;
146
+	unsigned max_texture_channel_caches;
147
+	unsigned max_gprs;
148
+	unsigned max_gs_threads;
149
+	unsigned max_hw_contexts;
150
+	unsigned sc_prim_fifo_size_frontend;
151
+	unsigned sc_prim_fifo_size_backend;
152
+	unsigned sc_hiz_tile_fifo_size;
153
+	unsigned sc_earlyz_tile_fifo_size;
154
+
155
+	unsigned num_tile_pipes;
156
+	unsigned backend_enable_mask;
157
+	unsigned mem_max_burst_length_bytes;
158
+	unsigned mem_row_size_in_kb;
159
+	unsigned shader_engine_tile_size;
160
+	unsigned num_gpus;
161
+	unsigned multi_gpu_tile_size;
162
+	unsigned mc_arb_ramcfg;
163
+	unsigned num_banks;
164
+	unsigned num_ranks;
165
+	unsigned gb_addr_config;
166
+	unsigned num_rbs;
167
+	unsigned gs_vgt_table_depth;
168
+	unsigned gs_prim_buffer_depth;
169
+
170
+	uint32_t tile_mode_array[32];
171
+	uint32_t macrotile_mode_array[16];
172
+
173
+	struct gb_addr_config gb_addr_config_fields;
174
+	struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
175
+
176
+	/* gfx configure feature */
177
+	uint32_t double_offchip_lds_buf;
178
+	/* cached value of DB_DEBUG2 */
179
+	uint32_t db_debug2;
180
+	/* gfx10 specific config */
181
+	uint32_t num_sc_per_sh;
182
+	uint32_t num_packer_per_sc;
183
+	uint32_t pa_sc_tile_steering_override;
184
+	uint64_t tcc_disabled_mask;
185
+};
186
+
187
+struct amdgpu_cu_info {
188
+	uint32_t simd_per_cu;
189
+	uint32_t max_waves_per_simd;
190
+	uint32_t wave_front_size;
191
+	uint32_t max_scratch_slots_per_cu;
192
+	uint32_t lds_size;
193
+
194
+	/* total active CU number */
195
+	uint32_t number;
196
+	uint32_t ao_cu_mask;
197
+	uint32_t ao_cu_bitmap[4][4];
198
+	uint32_t bitmap[4][4];
199
+};
200
+
201
+struct amdgpu_gfx_funcs {
202
+	/* get the gpu clock counter */
203
+	uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
204
+	void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num,
205
+			     u32 sh_num, u32 instance);
206
+	void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd,
207
+			       uint32_t wave, uint32_t *dst, int *no_fields);
208
+	void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd,
209
+				uint32_t wave, uint32_t thread, uint32_t start,
210
+				uint32_t size, uint32_t *dst);
211
+	void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd,
212
+				uint32_t wave, uint32_t start, uint32_t size,
213
+				uint32_t *dst);
214
+	void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe,
215
+				 u32 queue, u32 vmid);
216
+	int (*ras_error_inject)(struct amdgpu_device *adev, void *inject_if);
217
+	int (*query_ras_error_count) (struct amdgpu_device *adev, void *ras_error_status);
218
+	void (*reset_ras_error_count) (struct amdgpu_device *adev);
219
+	void (*init_spm_golden)(struct amdgpu_device *adev);
220
+	void (*query_ras_error_status) (struct amdgpu_device *adev);
221
+};
222
+
223
+struct sq_work {
224
+	struct work_struct	work;
225
+	unsigned ih_data;
226
+};
227
+
228
+struct amdgpu_pfp {
229
+	struct amdgpu_bo		*pfp_fw_obj;
230
+	uint64_t			pfp_fw_gpu_addr;
231
+	uint32_t			*pfp_fw_ptr;
232
+};
233
+
234
+struct amdgpu_ce {
235
+	struct amdgpu_bo		*ce_fw_obj;
236
+	uint64_t			ce_fw_gpu_addr;
237
+	uint32_t			*ce_fw_ptr;
238
+};
239
+
240
+struct amdgpu_me {
241
+	struct amdgpu_bo		*me_fw_obj;
242
+	uint64_t			me_fw_gpu_addr;
243
+	uint32_t			*me_fw_ptr;
244
+	uint32_t			num_me;
245
+	uint32_t			num_pipe_per_me;
246
+	uint32_t			num_queue_per_pipe;
247
+	void				*mqd_backup[AMDGPU_MAX_GFX_RINGS];
248
+
249
+	/* These are the resources for which amdgpu takes ownership */
250
+	DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
251
+};
252
+
253
+struct amdgpu_gfx {
254
+	struct mutex			gpu_clock_mutex;
255
+	struct amdgpu_gfx_config	config;
256
+	struct amdgpu_rlc		rlc;
257
+	struct amdgpu_pfp		pfp;
258
+	struct amdgpu_ce		ce;
259
+	struct amdgpu_me		me;
260
+	struct amdgpu_mec		mec;
261
+	struct amdgpu_kiq		kiq;
262
+	struct amdgpu_scratch		scratch;
263
+	const struct firmware		*me_fw;	/* ME firmware */
264
+	uint32_t			me_fw_version;
265
+	const struct firmware		*pfp_fw; /* PFP firmware */
266
+	uint32_t			pfp_fw_version;
267
+	const struct firmware		*ce_fw;	/* CE firmware */
268
+	uint32_t			ce_fw_version;
269
+	const struct firmware		*rlc_fw; /* RLC firmware */
270
+	uint32_t			rlc_fw_version;
271
+	const struct firmware		*mec_fw; /* MEC firmware */
272
+	uint32_t			mec_fw_version;
273
+	const struct firmware		*mec2_fw; /* MEC2 firmware */
274
+	uint32_t			mec2_fw_version;
275
+	uint32_t			me_feature_version;
276
+	uint32_t			ce_feature_version;
277
+	uint32_t			pfp_feature_version;
278
+	uint32_t			rlc_feature_version;
279
+	uint32_t			rlc_srlc_fw_version;
280
+	uint32_t			rlc_srlc_feature_version;
281
+	uint32_t			rlc_srlg_fw_version;
282
+	uint32_t			rlc_srlg_feature_version;
283
+	uint32_t			rlc_srls_fw_version;
284
+	uint32_t			rlc_srls_feature_version;
285
+	uint32_t			mec_feature_version;
286
+	uint32_t			mec2_feature_version;
287
+	bool				mec_fw_write_wait;
288
+	bool				me_fw_write_wait;
289
+	bool				cp_fw_write_wait;
290
+	struct amdgpu_ring		gfx_ring[AMDGPU_MAX_GFX_RINGS];
291
+	unsigned			num_gfx_rings;
292
+	struct amdgpu_ring		compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
293
+	unsigned			num_compute_rings;
294
+	struct amdgpu_irq_src		eop_irq;
295
+	struct amdgpu_irq_src		priv_reg_irq;
296
+	struct amdgpu_irq_src		priv_inst_irq;
297
+	struct amdgpu_irq_src		cp_ecc_error_irq;
298
+	struct amdgpu_irq_src		sq_irq;
299
+	struct sq_work			sq_work;
300
+
301
+	/* gfx status */
302
+	uint32_t			gfx_current_status;
303
+	/* ce ram size*/
304
+	unsigned			ce_ram_size;
305
+	struct amdgpu_cu_info		cu_info;
306
+	const struct amdgpu_gfx_funcs	*funcs;
307
+
308
+	/* reset mask */
309
+	uint32_t                        grbm_soft_reset;
310
+	uint32_t                        srbm_soft_reset;
311
+
312
+	/* gfx off */
313
+	bool                            gfx_off_state; /* true: enabled, false: disabled */
314
+	struct mutex                    gfx_off_mutex;
315
+	uint32_t                        gfx_off_req_count; /* default 1, enable gfx off: dec 1, disable gfx off: add 1 */
316
+	struct delayed_work             gfx_off_delay_work;
317
+
318
+	/* pipe reservation */
319
+	struct mutex			pipe_reserve_mutex;
320
+	DECLARE_BITMAP			(pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
321
+
322
+	/*ras */
323
+	struct ras_common_if		*ras_if;
324
+};
325
+
326
+#define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
327
+#define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
328
+#define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid))
329
+#define amdgpu_gfx_init_spm_golden(adev) (adev)->gfx.funcs->init_spm_golden((adev))
49330 
50331 /**
51332  * amdgpu_gfx_create_bitmask - create a bitmask
....@@ -60,34 +341,55 @@
60341 	return (u32)((1ULL << bit_width) - 1);
61342 }
62343 
63
-static inline int amdgpu_gfx_queue_to_bit(struct amdgpu_device *adev,
64
-					  int mec, int pipe, int queue)
65
-{
66
-	int bit = 0;
344
+int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg);
345
+void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg);
67346 
68
-	bit += mec * adev->gfx.mec.num_pipe_per_mec
69
-		* adev->gfx.mec.num_queue_per_pipe;
70
-	bit += pipe * adev->gfx.mec.num_queue_per_pipe;
71
-	bit += queue;
347
+void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se,
348
+				 unsigned max_sh);
72349 
73
-	return bit;
74
-}
350
+int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
351
+			     struct amdgpu_ring *ring,
352
+			     struct amdgpu_irq_src *irq);
75353 
76
-static inline void amdgpu_gfx_bit_to_queue(struct amdgpu_device *adev, int bit,
77
-					   int *mec, int *pipe, int *queue)
78
-{
79
-	*queue = bit % adev->gfx.mec.num_queue_per_pipe;
80
-	*pipe = (bit / adev->gfx.mec.num_queue_per_pipe)
81
-		% adev->gfx.mec.num_pipe_per_mec;
82
-	*mec = (bit / adev->gfx.mec.num_queue_per_pipe)
83
-	       / adev->gfx.mec.num_pipe_per_mec;
354
+void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring);
84355 
85
-}
86
-static inline bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev,
87
-						   int mec, int pipe, int queue)
88
-{
89
-	return test_bit(amdgpu_gfx_queue_to_bit(adev, mec, pipe, queue),
90
-			adev->gfx.mec.queue_bitmap);
91
-}
356
+void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev);
357
+int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
358
+			unsigned hpd_size);
92359 
360
+int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
361
+			   unsigned mqd_size);
362
+void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev);
363
+int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev);
364
+int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev);
365
+
366
+void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev);
367
+void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev);
368
+
369
+int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec,
370
+				int pipe, int queue);
371
+void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit,
372
+				 int *mec, int *pipe, int *queue);
373
+bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int mec,
374
+				     int pipe, int queue);
375
+bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
376
+					       int pipe, int queue);
377
+int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me,
378
+			       int pipe, int queue);
379
+void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
380
+				int *me, int *pipe, int *queue);
381
+bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me,
382
+				    int pipe, int queue);
383
+void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable);
384
+int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value);
385
+int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev);
386
+void amdgpu_gfx_ras_fini(struct amdgpu_device *adev);
387
+int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev,
388
+		void *err_data,
389
+		struct amdgpu_iv_entry *entry);
390
+int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev,
391
+				  struct amdgpu_irq_src *source,
392
+				  struct amdgpu_iv_entry *entry);
393
+uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg);
394
+void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v);
93395 #endif