forked from ~ljy/RK356X_SDK_RELEASE

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2024-05-10 23fa18eaa71266feff7ba8d83022d9e1cc83c65a 
 kernel/drivers/clk/ti/clk-7xx.c
....@@ -1,13 +1,10 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * DRA7 Clock init
34  *
45  * Copyright (C) 2013 Texas Instruments, Inc.
56  *
67  * Tero Kristo (t-kristo@ti.com)
7
- *
8
- * This program is free software; you can redistribute it and/or modify
9
- * it under the terms of the GNU General Public License version 2 as
10
- * published by the Free Software Foundation.
118  */
129 
1310 #include <linux/kernel.h>
....@@ -23,7 +20,28 @@
2320 #define DRA7_DPLL_USB_DEFFREQ				960000000
2421 
2522 static const struct omap_clkctrl_reg_data dra7_mpu_clkctrl_regs[] __initconst = {
26
-	{ DRA7_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" },
23
+	{ DRA7_MPU_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" },
24
+	{ 0 },
25
+};
26
+
27
+static const struct omap_clkctrl_reg_data dra7_dsp1_clkctrl_regs[] __initconst = {
28
+	{ DRA7_DSP1_MMU0_DSP1_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_dsp_m2_ck" },
29
+	{ 0 },
30
+};
31
+
32
+static const char * const dra7_ipu1_gfclk_mux_parents[] __initconst = {
33
+	"dpll_abe_m2x2_ck",
34
+	"dpll_core_h22x2_ck",
35
+	NULL,
36
+};
37
+
38
+static const struct omap_clkctrl_bit_data dra7_mmu_ipu1_bit_data[] __initconst = {
39
+	{ 24, TI_CLK_MUX, dra7_ipu1_gfclk_mux_parents, NULL },
40
+	{ 0 },
41
+};
42
+
43
+static const struct omap_clkctrl_reg_data dra7_ipu1_clkctrl_regs[] __initconst = {
44
+	{ DRA7_IPU1_MMU_IPU1_CLKCTRL, dra7_mmu_ipu1_bit_data, CLKF_HW_SUP | CLKF_NO_IDLEST, "ipu1-clkctrl:0000:24" },
2745 	{ 0 },
2846 };
2947 
....@@ -108,45 +126,78 @@
108126 };
109127 
110128 static const struct omap_clkctrl_reg_data dra7_ipu_clkctrl_regs[] __initconst = {
111
-	{ DRA7_MCASP1_CLKCTRL, dra7_mcasp1_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0010:22" },
112
-	{ DRA7_TIMER5_CLKCTRL, dra7_timer5_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0018:24" },
113
-	{ DRA7_TIMER6_CLKCTRL, dra7_timer6_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0020:24" },
114
-	{ DRA7_TIMER7_CLKCTRL, dra7_timer7_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0028:24" },
115
-	{ DRA7_TIMER8_CLKCTRL, dra7_timer8_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0030:24" },
116
-	{ DRA7_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
117
-	{ DRA7_UART6_CLKCTRL, dra7_uart6_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0040:24" },
129
+	{ DRA7_IPU_MCASP1_CLKCTRL, dra7_mcasp1_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0000:22" },
130
+	{ DRA7_IPU_TIMER5_CLKCTRL, dra7_timer5_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0008:24" },
131
+	{ DRA7_IPU_TIMER6_CLKCTRL, dra7_timer6_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0010:24" },
132
+	{ DRA7_IPU_TIMER7_CLKCTRL, dra7_timer7_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0018:24" },
133
+	{ DRA7_IPU_TIMER8_CLKCTRL, dra7_timer8_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0020:24" },
134
+	{ DRA7_IPU_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
135
+	{ DRA7_IPU_UART6_CLKCTRL, dra7_uart6_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0030:24" },
136
+	{ 0 },
137
+};
138
+
139
+static const struct omap_clkctrl_reg_data dra7_dsp2_clkctrl_regs[] __initconst = {
140
+	{ DRA7_DSP2_MMU0_DSP2_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_dsp_m2_ck" },
118141 	{ 0 },
119142 };
120143 
121144 static const struct omap_clkctrl_reg_data dra7_rtc_clkctrl_regs[] __initconst = {
122
-	{ DRA7_RTCSS_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
145
+	{ DRA7_RTC_RTCSS_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
146
+	{ 0 },
147
+};
148
+
149
+static const char * const dra7_cam_gfclk_mux_parents[] __initconst = {
150
+	"l3_iclk_div",
151
+	"core_iss_main_clk",
152
+	NULL,
153
+};
154
+
155
+static const struct omap_clkctrl_bit_data dra7_cam_bit_data[] __initconst = {
156
+	{ 24, TI_CLK_MUX, dra7_cam_gfclk_mux_parents, NULL },
157
+	{ 0 },
158
+};
159
+
160
+static const struct omap_clkctrl_reg_data dra7_cam_clkctrl_regs[] __initconst = {
161
+	{ DRA7_CAM_VIP1_CLKCTRL, dra7_cam_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
162
+	{ DRA7_CAM_VIP2_CLKCTRL, dra7_cam_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
163
+	{ DRA7_CAM_VIP3_CLKCTRL, dra7_cam_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
164
+	{ 0 },
165
+};
166
+
167
+static const struct omap_clkctrl_reg_data dra7_vpe_clkctrl_regs[] __initconst = {
168
+	{ DRA7_VPE_VPE_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h23x2_ck" },
123169 	{ 0 },
124170 };
125171 
126172 static const struct omap_clkctrl_reg_data dra7_coreaon_clkctrl_regs[] __initconst = {
127
-	{ DRA7_SMARTREFLEX_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
128
-	{ DRA7_SMARTREFLEX_CORE_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
173
+	{ DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
174
+	{ DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
129175 	{ 0 },
130176 };
131177 
132178 static const struct omap_clkctrl_reg_data dra7_l3main1_clkctrl_regs[] __initconst = {
133
-	{ DRA7_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" },
134
-	{ DRA7_GPMC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
135
-	{ DRA7_TPCC_CLKCTRL, NULL, 0, "l3_iclk_div" },
136
-	{ DRA7_TPTC0_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
137
-	{ DRA7_TPTC1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
138
-	{ DRA7_VCP1_CLKCTRL, NULL, 0, "l3_iclk_div" },
139
-	{ DRA7_VCP2_CLKCTRL, NULL, 0, "l3_iclk_div" },
179
+	{ DRA7_L3MAIN1_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" },
180
+	{ DRA7_L3MAIN1_GPMC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
181
+	{ DRA7_L3MAIN1_TPCC_CLKCTRL, NULL, 0, "l3_iclk_div" },
182
+	{ DRA7_L3MAIN1_TPTC0_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
183
+	{ DRA7_L3MAIN1_TPTC1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
184
+	{ DRA7_L3MAIN1_VCP1_CLKCTRL, NULL, 0, "l3_iclk_div" },
185
+	{ DRA7_L3MAIN1_VCP2_CLKCTRL, NULL, 0, "l3_iclk_div" },
186
+	{ 0 },
187
+};
188
+
189
+static const struct omap_clkctrl_reg_data dra7_ipu2_clkctrl_regs[] __initconst = {
190
+	{ DRA7_IPU2_MMU_IPU2_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_core_h22x2_ck" },
140191 	{ 0 },
141192 };
142193 
143194 static const struct omap_clkctrl_reg_data dra7_dma_clkctrl_regs[] __initconst = {
144
-	{ DRA7_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" },
195
+	{ DRA7_DMA_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" },
145196 	{ 0 },
146197 };
147198 
148199 static const struct omap_clkctrl_reg_data dra7_emif_clkctrl_regs[] __initconst = {
149
-	{ DRA7_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" },
200
+	{ DRA7_EMIF_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" },
150201 	{ 0 },
151202 };
152203 
....@@ -161,7 +212,7 @@
161212 static const char * const dra7_atl_gfclk_mux_parents[] __initconst = {
162213 	"l3_iclk_div",
163214 	"dpll_abe_m2_ck",
164
-	"atl_cm:clk:0000:24",
215
+	"atl-clkctrl:0000:24",
165216 	NULL,
166217 };
167218 
....@@ -172,32 +223,32 @@
172223 };
173224 
174225 static const struct omap_clkctrl_reg_data dra7_atl_clkctrl_regs[] __initconst = {
175
-	{ DRA7_ATL_CLKCTRL, dra7_atl_bit_data, CLKF_SW_SUP, "atl_cm:clk:0000:26" },
226
+	{ DRA7_ATL_ATL_CLKCTRL, dra7_atl_bit_data, CLKF_SW_SUP, "atl-clkctrl:0000:26" },
176227 	{ 0 },
177228 };
178229 
179230 static const struct omap_clkctrl_reg_data dra7_l4cfg_clkctrl_regs[] __initconst = {
180
-	{ DRA7_L4_CFG_CLKCTRL, NULL, 0, "l3_iclk_div" },
181
-	{ DRA7_SPINLOCK_CLKCTRL, NULL, 0, "l3_iclk_div" },
182
-	{ DRA7_MAILBOX1_CLKCTRL, NULL, 0, "l3_iclk_div" },
183
-	{ DRA7_MAILBOX2_CLKCTRL, NULL, 0, "l3_iclk_div" },
184
-	{ DRA7_MAILBOX3_CLKCTRL, NULL, 0, "l3_iclk_div" },
185
-	{ DRA7_MAILBOX4_CLKCTRL, NULL, 0, "l3_iclk_div" },
186
-	{ DRA7_MAILBOX5_CLKCTRL, NULL, 0, "l3_iclk_div" },
187
-	{ DRA7_MAILBOX6_CLKCTRL, NULL, 0, "l3_iclk_div" },
188
-	{ DRA7_MAILBOX7_CLKCTRL, NULL, 0, "l3_iclk_div" },
189
-	{ DRA7_MAILBOX8_CLKCTRL, NULL, 0, "l3_iclk_div" },
190
-	{ DRA7_MAILBOX9_CLKCTRL, NULL, 0, "l3_iclk_div" },
191
-	{ DRA7_MAILBOX10_CLKCTRL, NULL, 0, "l3_iclk_div" },
192
-	{ DRA7_MAILBOX11_CLKCTRL, NULL, 0, "l3_iclk_div" },
193
-	{ DRA7_MAILBOX12_CLKCTRL, NULL, 0, "l3_iclk_div" },
194
-	{ DRA7_MAILBOX13_CLKCTRL, NULL, 0, "l3_iclk_div" },
231
+	{ DRA7_L4CFG_L4_CFG_CLKCTRL, NULL, 0, "l3_iclk_div" },
232
+	{ DRA7_L4CFG_SPINLOCK_CLKCTRL, NULL, 0, "l3_iclk_div" },
233
+	{ DRA7_L4CFG_MAILBOX1_CLKCTRL, NULL, 0, "l3_iclk_div" },
234
+	{ DRA7_L4CFG_MAILBOX2_CLKCTRL, NULL, 0, "l3_iclk_div" },
235
+	{ DRA7_L4CFG_MAILBOX3_CLKCTRL, NULL, 0, "l3_iclk_div" },
236
+	{ DRA7_L4CFG_MAILBOX4_CLKCTRL, NULL, 0, "l3_iclk_div" },
237
+	{ DRA7_L4CFG_MAILBOX5_CLKCTRL, NULL, 0, "l3_iclk_div" },
238
+	{ DRA7_L4CFG_MAILBOX6_CLKCTRL, NULL, 0, "l3_iclk_div" },
239
+	{ DRA7_L4CFG_MAILBOX7_CLKCTRL, NULL, 0, "l3_iclk_div" },
240
+	{ DRA7_L4CFG_MAILBOX8_CLKCTRL, NULL, 0, "l3_iclk_div" },
241
+	{ DRA7_L4CFG_MAILBOX9_CLKCTRL, NULL, 0, "l3_iclk_div" },
242
+	{ DRA7_L4CFG_MAILBOX10_CLKCTRL, NULL, 0, "l3_iclk_div" },
243
+	{ DRA7_L4CFG_MAILBOX11_CLKCTRL, NULL, 0, "l3_iclk_div" },
244
+	{ DRA7_L4CFG_MAILBOX12_CLKCTRL, NULL, 0, "l3_iclk_div" },
245
+	{ DRA7_L4CFG_MAILBOX13_CLKCTRL, NULL, 0, "l3_iclk_div" },
195246 	{ 0 },
196247 };
197248 
198249 static const struct omap_clkctrl_reg_data dra7_l3instr_clkctrl_regs[] __initconst = {
199
-	{ DRA7_L3_MAIN_2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
200
-	{ DRA7_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
250
+	{ DRA7_L3INSTR_L3_MAIN_2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
251
+	{ DRA7_L3INSTR_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
201252 	{ 0 },
202253 };
203254 
....@@ -242,8 +293,33 @@
242293 };
243294 
244295 static const struct omap_clkctrl_reg_data dra7_dss_clkctrl_regs[] __initconst = {
245
-	{ DRA7_DSS_CORE_CLKCTRL, dra7_dss_core_bit_data, CLKF_SW_SUP, "dss_cm:clk:0000:8" },
246
-	{ DRA7_BB2D_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_h24x2_ck" },
296
+	{ DRA7_DSS_DSS_CORE_CLKCTRL, dra7_dss_core_bit_data, CLKF_SW_SUP, "dss-clkctrl:0000:8" },
297
+	{ DRA7_DSS_BB2D_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_h24x2_ck" },
298
+	{ 0 },
299
+};
300
+
301
+static const char * const dra7_gpu_core_mux_parents[] __initconst = {
302
+	"dpll_core_h14x2_ck",
303
+	"dpll_per_h14x2_ck",
304
+	"dpll_gpu_m2_ck",
305
+	NULL,
306
+};
307
+
308
+static const char * const dra7_gpu_hyd_mux_parents[] __initconst = {
309
+	"dpll_core_h14x2_ck",
310
+	"dpll_per_h14x2_ck",
311
+	"dpll_gpu_m2_ck",
312
+	NULL,
313
+};
314
+
315
+static const struct omap_clkctrl_bit_data dra7_gpu_core_bit_data[] __initconst = {
316
+	{ 24, TI_CLK_MUX, dra7_gpu_core_mux_parents, NULL, },
317
+	{ 26, TI_CLK_MUX, dra7_gpu_hyd_mux_parents, NULL, },
318
+	{ 0 },
319
+};
320
+
321
+static const struct omap_clkctrl_reg_data dra7_gpu_clkctrl_regs[] __initconst = {
322
+	{ DRA7_GPU_CLKCTRL, dra7_gpu_core_bit_data, CLKF_SW_SUP, "gpu-clkctrl:0000:24", },
247323 	{ 0 },
248324 };
249325 
....@@ -254,7 +330,7 @@
254330 };
255331 
256332 static const char * const dra7_mmc1_fclk_div_parents[] __initconst = {
257
-	"l3init_cm:clk:0008:24",
333
+	"l3init-clkctrl:0008:24",
258334 	NULL,
259335 };
260336 
....@@ -271,7 +347,7 @@
271347 };
272348 
273349 static const char * const dra7_mmc2_fclk_div_parents[] __initconst = {
274
-	"l3init_cm:clk:0010:24",
350
+	"l3init-clkctrl:0010:24",
275351 	NULL,
276352 };
277353 
....@@ -307,6 +383,24 @@
307383 	{ 0 },
308384 };
309385 
386
+static const struct omap_clkctrl_bit_data dra7_usb_otg_ss1_bit_data[] __initconst = {
387
+	{ 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
388
+	{ 0 },
389
+};
390
+
391
+static const struct omap_clkctrl_reg_data dra7_l3init_clkctrl_regs[] __initconst = {
392
+	{ DRA7_L3INIT_MMC1_CLKCTRL, dra7_mmc1_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0008:25" },
393
+	{ DRA7_L3INIT_MMC2_CLKCTRL, dra7_mmc2_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0010:25" },
394
+	{ DRA7_L3INIT_USB_OTG_SS2_CLKCTRL, dra7_usb_otg_ss2_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
395
+	{ DRA7_L3INIT_USB_OTG_SS3_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
396
+	{ DRA7_L3INIT_USB_OTG_SS4_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_DRA74 | CLKF_SOC_DRA76, "dpll_core_h13x2_ck" },
397
+	{ DRA7_L3INIT_SATA_CLKCTRL, dra7_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" },
398
+	{ DRA7_L3INIT_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
399
+	{ DRA7_L3INIT_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
400
+	{ DRA7_L3INIT_USB_OTG_SS1_CLKCTRL, dra7_usb_otg_ss1_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
401
+	{ 0 },
402
+};
403
+
310404 static const char * const dra7_optfclk_pciephy1_clk_parents[] __initconst = {
311405 	"apll_pcie_ck",
312406 	NULL,
....@@ -331,6 +425,12 @@
331425 	{ 0 },
332426 };
333427 
428
+static const struct omap_clkctrl_reg_data dra7_pcie_clkctrl_regs[] __initconst = {
429
+	{ DRA7_PCIE_PCIE1_CLKCTRL, dra7_pcie1_bit_data, CLKF_SW_SUP, "l4_root_clk_div" },
430
+	{ DRA7_PCIE_PCIE2_CLKCTRL, dra7_pcie2_bit_data, CLKF_SW_SUP, "l4_root_clk_div" },
431
+	{ 0 },
432
+};
433
+
334434 static const char * const dra7_rmii_50mhz_clk_mux_parents[] __initconst = {
335435 	"dpll_gmac_h11x2_ck",
336436 	"rmii_clk_ck",
....@@ -352,24 +452,8 @@
352452 	{ 0 },
353453 };
354454 
355
-static const struct omap_clkctrl_bit_data dra7_usb_otg_ss1_bit_data[] __initconst = {
356
-	{ 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
357
-	{ 0 },
358
-};
359
-
360
-static const struct omap_clkctrl_reg_data dra7_l3init_clkctrl_regs[] __initconst = {
361
-	{ DRA7_MMC1_CLKCTRL, dra7_mmc1_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0008:25" },
362
-	{ DRA7_MMC2_CLKCTRL, dra7_mmc2_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0010:25" },
363
-	{ DRA7_USB_OTG_SS2_CLKCTRL, dra7_usb_otg_ss2_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
364
-	{ DRA7_USB_OTG_SS3_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
365
-	{ DRA7_USB_OTG_SS4_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
366
-	{ DRA7_SATA_CLKCTRL, dra7_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" },
367
-	{ DRA7_PCIE1_CLKCTRL, dra7_pcie1_bit_data, CLKF_SW_SUP, "l4_root_clk_div", "pcie_clkdm" },
368
-	{ DRA7_PCIE2_CLKCTRL, dra7_pcie2_bit_data, CLKF_SW_SUP, "l4_root_clk_div", "pcie_clkdm" },
369
-	{ DRA7_GMAC_CLKCTRL, dra7_gmac_bit_data, CLKF_SW_SUP, "dpll_gmac_ck", "gmac_clkdm" },
370
-	{ DRA7_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
371
-	{ DRA7_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
372
-	{ DRA7_USB_OTG_SS1_CLKCTRL, dra7_usb_otg_ss1_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
455
+static const struct omap_clkctrl_reg_data dra7_gmac_clkctrl_regs[] __initconst = {
456
+	{ DRA7_GMAC_GMAC_CLKCTRL, dra7_gmac_bit_data, CLKF_SW_SUP, "gmac_main_clk" },
373457 	{ 0 },
374458 };
375459 
....@@ -443,21 +527,6 @@
443527 	{ 0 },
444528 };
445529 
446
-static const struct omap_clkctrl_bit_data dra7_timer13_bit_data[] __initconst = {
447
-	{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
448
-	{ 0 },
449
-};
450
-
451
-static const struct omap_clkctrl_bit_data dra7_timer14_bit_data[] __initconst = {
452
-	{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
453
-	{ 0 },
454
-};
455
-
456
-static const struct omap_clkctrl_bit_data dra7_timer15_bit_data[] __initconst = {
457
-	{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
458
-	{ 0 },
459
-};
460
-
461530 static const struct omap_clkctrl_bit_data dra7_gpio7_bit_data[] __initconst = {
462531 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
463532 	{ 0 },
....@@ -469,7 +538,7 @@
469538 };
470539 
471540 static const char * const dra7_mmc3_gfclk_div_parents[] __initconst = {
472
-	"l4per_cm:clk:0120:24",
541
+	"l4per-clkctrl:00f8:24",
473542 	NULL,
474543 };
475544 
....@@ -486,7 +555,7 @@
486555 };
487556 
488557 static const char * const dra7_mmc4_gfclk_div_parents[] __initconst = {
489
-	"l4per_cm:clk:0128:24",
558
+	"l4per-clkctrl:0100:24",
490559 	NULL,
491560 };
492561 
....@@ -499,33 +568,6 @@
499568 	{ 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
500569 	{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
501570 	{ 25, TI_CLK_DIVIDER, dra7_mmc4_gfclk_div_parents, &dra7_mmc4_gfclk_div_data },
502
-	{ 0 },
503
-};
504
-
505
-static const struct omap_clkctrl_bit_data dra7_timer16_bit_data[] __initconst = {
506
-	{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
507
-	{ 0 },
508
-};
509
-
510
-static const char * const dra7_qspi_gfclk_mux_parents[] __initconst = {
511
-	"func_128m_clk",
512
-	"dpll_per_h13x2_ck",
513
-	NULL,
514
-};
515
-
516
-static const char * const dra7_qspi_gfclk_div_parents[] __initconst = {
517
-	"l4per_cm:clk:0138:24",
518
-	NULL,
519
-};
520
-
521
-static const struct omap_clkctrl_div_data dra7_qspi_gfclk_div_data __initconst = {
522
-	.max_div = 4,
523
-	.flags = CLK_DIVIDER_POWER_OF_TWO,
524
-};
525
-
526
-static const struct omap_clkctrl_bit_data dra7_qspi_bit_data[] __initconst = {
527
-	{ 24, TI_CLK_MUX, dra7_qspi_gfclk_mux_parents, NULL },
528
-	{ 25, TI_CLK_DIVIDER, dra7_qspi_gfclk_div_parents, &dra7_qspi_gfclk_div_data },
529571 	{ 0 },
530572 };
531573 
....@@ -549,6 +591,78 @@
549591 	{ 0 },
550592 };
551593 
594
+static const struct omap_clkctrl_bit_data dra7_uart5_bit_data[] __initconst = {
595
+	{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
596
+	{ 0 },
597
+};
598
+
599
+static const struct omap_clkctrl_reg_data dra7_l4per_clkctrl_regs[] __initconst = {
600
+	{ DRA7_L4PER_TIMER10_CLKCTRL, dra7_timer10_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0000:24" },
601
+	{ DRA7_L4PER_TIMER11_CLKCTRL, dra7_timer11_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0008:24" },
602
+	{ DRA7_L4PER_TIMER2_CLKCTRL, dra7_timer2_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0010:24" },
603
+	{ DRA7_L4PER_TIMER3_CLKCTRL, dra7_timer3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0018:24" },
604
+	{ DRA7_L4PER_TIMER4_CLKCTRL, dra7_timer4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0020:24" },
605
+	{ DRA7_L4PER_TIMER9_CLKCTRL, dra7_timer9_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0028:24" },
606
+	{ DRA7_L4PER_ELM_CLKCTRL, NULL, 0, "l3_iclk_div" },
607
+	{ DRA7_L4PER_GPIO2_CLKCTRL, dra7_gpio2_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
608
+	{ DRA7_L4PER_GPIO3_CLKCTRL, dra7_gpio3_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
609
+	{ DRA7_L4PER_GPIO4_CLKCTRL, dra7_gpio4_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
610
+	{ DRA7_L4PER_GPIO5_CLKCTRL, dra7_gpio5_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
611
+	{ DRA7_L4PER_GPIO6_CLKCTRL, dra7_gpio6_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
612
+	{ DRA7_L4PER_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_fclk" },
613
+	{ DRA7_L4PER_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
614
+	{ DRA7_L4PER_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
615
+	{ DRA7_L4PER_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
616
+	{ DRA7_L4PER_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
617
+	{ DRA7_L4PER_L4_PER1_CLKCTRL, NULL, 0, "l3_iclk_div" },
618
+	{ DRA7_L4PER_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
619
+	{ DRA7_L4PER_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
620
+	{ DRA7_L4PER_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
621
+	{ DRA7_L4PER_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
622
+	{ DRA7_L4PER_GPIO7_CLKCTRL, dra7_gpio7_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
623
+	{ DRA7_L4PER_GPIO8_CLKCTRL, dra7_gpio8_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
624
+	{ DRA7_L4PER_MMC3_CLKCTRL, dra7_mmc3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:00f8:25" },
625
+	{ DRA7_L4PER_MMC4_CLKCTRL, dra7_mmc4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0100:25" },
626
+	{ DRA7_L4PER_UART1_CLKCTRL, dra7_uart1_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0118:24" },
627
+	{ DRA7_L4PER_UART2_CLKCTRL, dra7_uart2_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0120:24" },
628
+	{ DRA7_L4PER_UART3_CLKCTRL, dra7_uart3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0128:24" },
629
+	{ DRA7_L4PER_UART4_CLKCTRL, dra7_uart4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0130:24" },
630
+	{ DRA7_L4PER_UART5_CLKCTRL, dra7_uart5_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0148:24" },
631
+	{ 0 },
632
+};
633
+
634
+static const struct omap_clkctrl_reg_data dra7_l4sec_clkctrl_regs[] __initconst = {
635
+	{ DRA7_L4SEC_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
636
+	{ DRA7_L4SEC_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
637
+	{ DRA7_L4SEC_DES_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
638
+	{ DRA7_L4SEC_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "l4_root_clk_div" },
639
+	{ DRA7_L4SEC_SHAM_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
640
+	{ DRA7_L4SEC_SHAM2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
641
+	{ 0 },
642
+};
643
+
644
+static const char * const dra7_qspi_gfclk_mux_parents[] __initconst = {
645
+	"func_128m_clk",
646
+	"dpll_per_h13x2_ck",
647
+	NULL,
648
+};
649
+
650
+static const char * const dra7_qspi_gfclk_div_parents[] __initconst = {
651
+	"l4per2-clkctrl:012c:24",
652
+	NULL,
653
+};
654
+
655
+static const struct omap_clkctrl_div_data dra7_qspi_gfclk_div_data __initconst = {
656
+	.max_div = 4,
657
+	.flags = CLK_DIVIDER_POWER_OF_TWO,
658
+};
659
+
660
+static const struct omap_clkctrl_bit_data dra7_qspi_bit_data[] __initconst = {
661
+	{ 24, TI_CLK_MUX, dra7_qspi_gfclk_mux_parents, NULL },
662
+	{ 25, TI_CLK_DIVIDER, dra7_qspi_gfclk_div_parents, &dra7_qspi_gfclk_div_data },
663
+	{ 0 },
664
+};
665
+
552666 static const struct omap_clkctrl_bit_data dra7_mcasp2_bit_data[] __initconst = {
553667 	{ 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
554668 	{ 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
....@@ -559,11 +673,6 @@
559673 static const struct omap_clkctrl_bit_data dra7_mcasp3_bit_data[] __initconst = {
560674 	{ 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
561675 	{ 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
562
-	{ 0 },
563
-};
564
-
565
-static const struct omap_clkctrl_bit_data dra7_uart5_bit_data[] __initconst = {
566
-	{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
567676 	{ 0 },
568677 };
569678 
....@@ -612,64 +721,54 @@
612721 	{ 0 },
613722 };
614723 
615
-static const struct omap_clkctrl_reg_data dra7_l4per_clkctrl_regs[] __initconst = {
616
-	{ DRA7_L4_PER2_CLKCTRL, NULL, 0, "l3_iclk_div", "l4per2_clkdm" },
617
-	{ DRA7_L4_PER3_CLKCTRL, NULL, 0, "l3_iclk_div", "l4per3_clkdm" },
618
-	{ DRA7_TIMER10_CLKCTRL, dra7_timer10_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0028:24" },
619
-	{ DRA7_TIMER11_CLKCTRL, dra7_timer11_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0030:24" },
620
-	{ DRA7_TIMER2_CLKCTRL, dra7_timer2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0038:24" },
621
-	{ DRA7_TIMER3_CLKCTRL, dra7_timer3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0040:24" },
622
-	{ DRA7_TIMER4_CLKCTRL, dra7_timer4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0048:24" },
623
-	{ DRA7_TIMER9_CLKCTRL, dra7_timer9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0050:24" },
624
-	{ DRA7_ELM_CLKCTRL, NULL, 0, "l3_iclk_div" },
625
-	{ DRA7_GPIO2_CLKCTRL, dra7_gpio2_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
626
-	{ DRA7_GPIO3_CLKCTRL, dra7_gpio3_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
627
-	{ DRA7_GPIO4_CLKCTRL, dra7_gpio4_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
628
-	{ DRA7_GPIO5_CLKCTRL, dra7_gpio5_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
629
-	{ DRA7_GPIO6_CLKCTRL, dra7_gpio6_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
630
-	{ DRA7_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_fclk" },
631
-	{ DRA7_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" },
632
-	{ DRA7_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" },
633
-	{ DRA7_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
634
-	{ DRA7_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
635
-	{ DRA7_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
636
-	{ DRA7_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
637
-	{ DRA7_L4_PER1_CLKCTRL, NULL, 0, "l3_iclk_div" },
638
-	{ DRA7_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" },
639
-	{ DRA7_TIMER13_CLKCTRL, dra7_timer13_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00c8:24", "l4per3_clkdm" },
640
-	{ DRA7_TIMER14_CLKCTRL, dra7_timer14_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00d0:24", "l4per3_clkdm" },
641
-	{ DRA7_TIMER15_CLKCTRL, dra7_timer15_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00d8:24", "l4per3_clkdm" },
642
-	{ DRA7_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
643
-	{ DRA7_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
644
-	{ DRA7_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
645
-	{ DRA7_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
646
-	{ DRA7_GPIO7_CLKCTRL, dra7_gpio7_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
647
-	{ DRA7_GPIO8_CLKCTRL, dra7_gpio8_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
648
-	{ DRA7_MMC3_CLKCTRL, dra7_mmc3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0120:25" },
649
-	{ DRA7_MMC4_CLKCTRL, dra7_mmc4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0128:25" },
650
-	{ DRA7_TIMER16_CLKCTRL, dra7_timer16_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0130:24", "l4per3_clkdm" },
651
-	{ DRA7_QSPI_CLKCTRL, dra7_qspi_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0138:25", "l4per2_clkdm" },
652
-	{ DRA7_UART1_CLKCTRL, dra7_uart1_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0140:24" },
653
-	{ DRA7_UART2_CLKCTRL, dra7_uart2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0148:24" },
654
-	{ DRA7_UART3_CLKCTRL, dra7_uart3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0150:24" },
655
-	{ DRA7_UART4_CLKCTRL, dra7_uart4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0158:24" },
656
-	{ DRA7_MCASP2_CLKCTRL, dra7_mcasp2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0160:22", "l4per2_clkdm" },
657
-	{ DRA7_MCASP3_CLKCTRL, dra7_mcasp3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0168:22", "l4per2_clkdm" },
658
-	{ DRA7_UART5_CLKCTRL, dra7_uart5_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0170:24" },
659
-	{ DRA7_MCASP5_CLKCTRL, dra7_mcasp5_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0178:22", "l4per2_clkdm" },
660
-	{ DRA7_MCASP8_CLKCTRL, dra7_mcasp8_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0190:24", "l4per2_clkdm" },
661
-	{ DRA7_MCASP4_CLKCTRL, dra7_mcasp4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0198:22", "l4per2_clkdm" },
662
-	{ DRA7_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
663
-	{ DRA7_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
664
-	{ DRA7_DES_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
665
-	{ DRA7_RNG_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
666
-	{ DRA7_SHAM_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
667
-	{ DRA7_UART7_CLKCTRL, dra7_uart7_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01d0:24", "l4per2_clkdm" },
668
-	{ DRA7_UART8_CLKCTRL, dra7_uart8_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01e0:24", "l4per2_clkdm" },
669
-	{ DRA7_UART9_CLKCTRL, dra7_uart9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01e8:24", "l4per2_clkdm" },
670
-	{ DRA7_DCAN2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin1", "l4per2_clkdm" },
671
-	{ DRA7_MCASP6_CLKCTRL, dra7_mcasp6_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0204:22", "l4per2_clkdm" },
672
-	{ DRA7_MCASP7_CLKCTRL, dra7_mcasp7_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0208:22", "l4per2_clkdm" },
724
+static const struct omap_clkctrl_reg_data dra7_l4per2_clkctrl_regs[] __initconst = {
725
+	{ DRA7_L4PER2_L4_PER2_CLKCTRL, NULL, 0, "l3_iclk_div" },
726
+	{ DRA7_L4PER2_PRUSS1_CLKCTRL, NULL, CLKF_SW_SUP, "" },
727
+	{ DRA7_L4PER2_PRUSS2_CLKCTRL, NULL, CLKF_SW_SUP, "" },
728
+	{ DRA7_L4PER2_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" },
729
+	{ DRA7_L4PER2_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" },
730
+	{ DRA7_L4PER2_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" },
731
+	{ DRA7_L4PER2_QSPI_CLKCTRL, dra7_qspi_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:012c:25" },
732
+	{ DRA7_L4PER2_MCASP2_CLKCTRL, dra7_mcasp2_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0154:22" },
733
+	{ DRA7_L4PER2_MCASP3_CLKCTRL, dra7_mcasp3_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:015c:22" },
734
+	{ DRA7_L4PER2_MCASP5_CLKCTRL, dra7_mcasp5_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:016c:22" },
735
+	{ DRA7_L4PER2_MCASP8_CLKCTRL, dra7_mcasp8_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0184:22" },
736
+	{ DRA7_L4PER2_MCASP4_CLKCTRL, dra7_mcasp4_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:018c:22" },
737
+	{ DRA7_L4PER2_UART7_CLKCTRL, dra7_uart7_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01c4:24" },
738
+	{ DRA7_L4PER2_UART8_CLKCTRL, dra7_uart8_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01d4:24" },
739
+	{ DRA7_L4PER2_UART9_CLKCTRL, dra7_uart9_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01dc:24" },
740
+	{ DRA7_L4PER2_DCAN2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin1" },
741
+	{ DRA7_L4PER2_MCASP6_CLKCTRL, dra7_mcasp6_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01f8:22" },
742
+	{ DRA7_L4PER2_MCASP7_CLKCTRL, dra7_mcasp7_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01fc:22" },
743
+	{ 0 },
744
+};
745
+
746
+static const struct omap_clkctrl_bit_data dra7_timer13_bit_data[] __initconst = {
747
+	{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
748
+	{ 0 },
749
+};
750
+
751
+static const struct omap_clkctrl_bit_data dra7_timer14_bit_data[] __initconst = {
752
+	{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
753
+	{ 0 },
754
+};
755
+
756
+static const struct omap_clkctrl_bit_data dra7_timer15_bit_data[] __initconst = {
757
+	{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
758
+	{ 0 },
759
+};
760
+
761
+static const struct omap_clkctrl_bit_data dra7_timer16_bit_data[] __initconst = {
762
+	{ 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
763
+	{ 0 },
764
+};
765
+
766
+static const struct omap_clkctrl_reg_data dra7_l4per3_clkctrl_regs[] __initconst = {
767
+	{ DRA7_L4PER3_L4_PER3_CLKCTRL, NULL, 0, "l3_iclk_div" },
768
+	{ DRA7_L4PER3_TIMER13_CLKCTRL, dra7_timer13_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:00b4:24" },
769
+	{ DRA7_L4PER3_TIMER14_CLKCTRL, dra7_timer14_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:00bc:24" },
770
+	{ DRA7_L4PER3_TIMER15_CLKCTRL, dra7_timer15_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:00c4:24" },
771
+	{ DRA7_L4PER3_TIMER16_CLKCTRL, dra7_timer16_bit_data, CLKF_SW_SUP, "l4per3-clkctrl:011c:24" },
673772 	{ 0 },
674773 };
675774 
....@@ -700,32 +799,44 @@
700799 };
701800 
702801 static const struct omap_clkctrl_reg_data dra7_wkupaon_clkctrl_regs[] __initconst = {
703
-	{ DRA7_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
704
-	{ DRA7_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
705
-	{ DRA7_GPIO1_CLKCTRL, dra7_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" },
706
-	{ DRA7_TIMER1_CLKCTRL, dra7_timer1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0020:24" },
707
-	{ DRA7_TIMER12_CLKCTRL, NULL, 0, "secure_32k_clk_src_ck" },
708
-	{ DRA7_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
709
-	{ DRA7_UART10_CLKCTRL, dra7_uart10_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0060:24" },
710
-	{ DRA7_DCAN1_CLKCTRL, dra7_dcan1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0068:24" },
711
-	{ DRA7_ADC_CLKCTRL, NULL, CLKF_SW_SUP, "mcan_clk"},
802
+	{ DRA7_WKUPAON_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
803
+	{ DRA7_WKUPAON_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
804
+	{ DRA7_WKUPAON_GPIO1_CLKCTRL, dra7_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" },
805
+	{ DRA7_WKUPAON_TIMER1_CLKCTRL, dra7_timer1_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0020:24" },
806
+	{ DRA7_WKUPAON_TIMER12_CLKCTRL, NULL, CLKF_SOC_NONSEC, "secure_32k_clk_src_ck" },
807
+	{ DRA7_WKUPAON_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
808
+	{ DRA7_WKUPAON_UART10_CLKCTRL, dra7_uart10_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0060:24" },
809
+	{ DRA7_WKUPAON_DCAN1_CLKCTRL, dra7_dcan1_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0068:24" },
810
+	{ DRA7_WKUPAON_ADC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SOC_DRA76, "mcan_clk" },
712811 	{ 0 },
713812 };
714813 
715814 const struct omap_clkctrl_data dra7_clkctrl_data[] __initconst = {
716815 	{ 0x4a005320, dra7_mpu_clkctrl_regs },
717
-	{ 0x4a005540, dra7_ipu_clkctrl_regs },
718
-	{ 0x4a005740, dra7_rtc_clkctrl_regs },
816
+	{ 0x4a005420, dra7_dsp1_clkctrl_regs },
817
+	{ 0x4a005520, dra7_ipu1_clkctrl_regs },
818
+	{ 0x4a005550, dra7_ipu_clkctrl_regs },
819
+	{ 0x4a005620, dra7_dsp2_clkctrl_regs },
820
+	{ 0x4a005720, dra7_rtc_clkctrl_regs },
821
+	{ 0x4a005760, dra7_vpe_clkctrl_regs },
719822 	{ 0x4a008620, dra7_coreaon_clkctrl_regs },
720823 	{ 0x4a008720, dra7_l3main1_clkctrl_regs },
824
+	{ 0x4a008920, dra7_ipu2_clkctrl_regs },
721825 	{ 0x4a008a20, dra7_dma_clkctrl_regs },
722826 	{ 0x4a008b20, dra7_emif_clkctrl_regs },
723827 	{ 0x4a008c00, dra7_atl_clkctrl_regs },
724828 	{ 0x4a008d20, dra7_l4cfg_clkctrl_regs },
725829 	{ 0x4a008e20, dra7_l3instr_clkctrl_regs },
830
+	{ 0x4a009020, dra7_cam_clkctrl_regs },
726831 	{ 0x4a009120, dra7_dss_clkctrl_regs },
832
+	{ 0x4a009220, dra7_gpu_clkctrl_regs },
727833 	{ 0x4a009320, dra7_l3init_clkctrl_regs },
728
-	{ 0x4a009700, dra7_l4per_clkctrl_regs },
834
+	{ 0x4a0093b0, dra7_pcie_clkctrl_regs },
835
+	{ 0x4a0093d0, dra7_gmac_clkctrl_regs },
836
+	{ 0x4a009728, dra7_l4per_clkctrl_regs },
837
+	{ 0x4a0098a0, dra7_l4sec_clkctrl_regs },
838
+	{ 0x4a00970c, dra7_l4per2_clkctrl_regs },
839
+	{ 0x4a009714, dra7_l4per3_clkctrl_regs },
729840 	{ 0x4ae07820, dra7_wkupaon_clkctrl_regs },
730841 	{ 0 },
731842 };
....@@ -734,91 +845,92 @@
734845 	DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
735846 	DT_CLK(NULL, "sys_clkin_ck", "timer_sys_clk_div"),
736847 	DT_CLK(NULL, "sys_clkin", "sys_clkin1"),
737
-	DT_CLK(NULL, "atl_dpll_clk_mux", "atl_cm:0000:24"),
738
-	DT_CLK(NULL, "atl_gfclk_mux", "atl_cm:0000:26"),
739
-	DT_CLK(NULL, "dcan1_sys_clk_mux", "wkupaon_cm:0068:24"),
740
-	DT_CLK(NULL, "dss_32khz_clk", "dss_cm:0000:11"),
741
-	DT_CLK(NULL, "dss_48mhz_clk", "dss_cm:0000:9"),
742
-	DT_CLK(NULL, "dss_dss_clk", "dss_cm:0000:8"),
743
-	DT_CLK(NULL, "dss_hdmi_clk", "dss_cm:0000:10"),
744
-	DT_CLK(NULL, "dss_video1_clk", "dss_cm:0000:12"),
745
-	DT_CLK(NULL, "dss_video2_clk", "dss_cm:0000:13"),
746
-	DT_CLK(NULL, "gmac_rft_clk_mux", "l3init_cm:00b0:25"),
747
-	DT_CLK(NULL, "gpio1_dbclk", "wkupaon_cm:0018:8"),
748
-	DT_CLK(NULL, "gpio2_dbclk", "l4per_cm:0060:8"),
749
-	DT_CLK(NULL, "gpio3_dbclk", "l4per_cm:0068:8"),
750
-	DT_CLK(NULL, "gpio4_dbclk", "l4per_cm:0070:8"),
751
-	DT_CLK(NULL, "gpio5_dbclk", "l4per_cm:0078:8"),
752
-	DT_CLK(NULL, "gpio6_dbclk", "l4per_cm:0080:8"),
753
-	DT_CLK(NULL, "gpio7_dbclk", "l4per_cm:0110:8"),
754
-	DT_CLK(NULL, "gpio8_dbclk", "l4per_cm:0118:8"),
755
-	DT_CLK(NULL, "mcasp1_ahclkr_mux", "ipu_cm:0010:28"),
756
-	DT_CLK(NULL, "mcasp1_ahclkx_mux", "ipu_cm:0010:24"),
757
-	DT_CLK(NULL, "mcasp1_aux_gfclk_mux", "ipu_cm:0010:22"),
758
-	DT_CLK(NULL, "mcasp2_ahclkr_mux", "l4per_cm:0160:28"),
759
-	DT_CLK(NULL, "mcasp2_ahclkx_mux", "l4per_cm:0160:24"),
760
-	DT_CLK(NULL, "mcasp2_aux_gfclk_mux", "l4per_cm:0160:22"),
761
-	DT_CLK(NULL, "mcasp3_ahclkx_mux", "l4per_cm:0168:24"),
762
-	DT_CLK(NULL, "mcasp3_aux_gfclk_mux", "l4per_cm:0168:22"),
763
-	DT_CLK(NULL, "mcasp4_ahclkx_mux", "l4per_cm:0198:24"),
764
-	DT_CLK(NULL, "mcasp4_aux_gfclk_mux", "l4per_cm:0198:22"),
765
-	DT_CLK(NULL, "mcasp5_ahclkx_mux", "l4per_cm:0178:24"),
766
-	DT_CLK(NULL, "mcasp5_aux_gfclk_mux", "l4per_cm:0178:22"),
767
-	DT_CLK(NULL, "mcasp6_ahclkx_mux", "l4per_cm:0204:24"),
768
-	DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "l4per_cm:0204:22"),
769
-	DT_CLK(NULL, "mcasp7_ahclkx_mux", "l4per_cm:0208:24"),
770
-	DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "l4per_cm:0208:22"),
771
-	DT_CLK(NULL, "mcasp8_ahclkx_mux", "l4per_cm:0190:22"),
772
-	DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "l4per_cm:0190:24"),
773
-	DT_CLK(NULL, "mmc1_clk32k", "l3init_cm:0008:8"),
774
-	DT_CLK(NULL, "mmc1_fclk_div", "l3init_cm:0008:25"),
775
-	DT_CLK(NULL, "mmc1_fclk_mux", "l3init_cm:0008:24"),
776
-	DT_CLK(NULL, "mmc2_clk32k", "l3init_cm:0010:8"),
777
-	DT_CLK(NULL, "mmc2_fclk_div", "l3init_cm:0010:25"),
778
-	DT_CLK(NULL, "mmc2_fclk_mux", "l3init_cm:0010:24"),
779
-	DT_CLK(NULL, "mmc3_clk32k", "l4per_cm:0120:8"),
780
-	DT_CLK(NULL, "mmc3_gfclk_div", "l4per_cm:0120:25"),
781
-	DT_CLK(NULL, "mmc3_gfclk_mux", "l4per_cm:0120:24"),
782
-	DT_CLK(NULL, "mmc4_clk32k", "l4per_cm:0128:8"),
783
-	DT_CLK(NULL, "mmc4_gfclk_div", "l4per_cm:0128:25"),
784
-	DT_CLK(NULL, "mmc4_gfclk_mux", "l4per_cm:0128:24"),
785
-	DT_CLK(NULL, "optfclk_pciephy1_32khz", "l3init_cm:0090:8"),
786
-	DT_CLK(NULL, "optfclk_pciephy1_clk", "l3init_cm:0090:9"),
787
-	DT_CLK(NULL, "optfclk_pciephy1_div_clk", "l3init_cm:0090:10"),
788
-	DT_CLK(NULL, "optfclk_pciephy2_32khz", "l3init_cm:0098:8"),
789
-	DT_CLK(NULL, "optfclk_pciephy2_clk", "l3init_cm:0098:9"),
790
-	DT_CLK(NULL, "optfclk_pciephy2_div_clk", "l3init_cm:0098:10"),
791
-	DT_CLK(NULL, "qspi_gfclk_div", "l4per_cm:0138:25"),
792
-	DT_CLK(NULL, "qspi_gfclk_mux", "l4per_cm:0138:24"),
793
-	DT_CLK(NULL, "rmii_50mhz_clk_mux", "l3init_cm:00b0:24"),
794
-	DT_CLK(NULL, "sata_ref_clk", "l3init_cm:0068:8"),
795
-	DT_CLK(NULL, "timer10_gfclk_mux", "l4per_cm:0028:24"),
796
-	DT_CLK(NULL, "timer11_gfclk_mux", "l4per_cm:0030:24"),
797
-	DT_CLK(NULL, "timer13_gfclk_mux", "l4per_cm:00c8:24"),
798
-	DT_CLK(NULL, "timer14_gfclk_mux", "l4per_cm:00d0:24"),
799
-	DT_CLK(NULL, "timer15_gfclk_mux", "l4per_cm:00d8:24"),
800
-	DT_CLK(NULL, "timer16_gfclk_mux", "l4per_cm:0130:24"),
801
-	DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon_cm:0020:24"),
802
-	DT_CLK(NULL, "timer2_gfclk_mux", "l4per_cm:0038:24"),
803
-	DT_CLK(NULL, "timer3_gfclk_mux", "l4per_cm:0040:24"),
804
-	DT_CLK(NULL, "timer4_gfclk_mux", "l4per_cm:0048:24"),
805
-	DT_CLK(NULL, "timer5_gfclk_mux", "ipu_cm:0018:24"),
806
-	DT_CLK(NULL, "timer6_gfclk_mux", "ipu_cm:0020:24"),
807
-	DT_CLK(NULL, "timer7_gfclk_mux", "ipu_cm:0028:24"),
808
-	DT_CLK(NULL, "timer8_gfclk_mux", "ipu_cm:0030:24"),
809
-	DT_CLK(NULL, "timer9_gfclk_mux", "l4per_cm:0050:24"),
810
-	DT_CLK(NULL, "uart10_gfclk_mux", "wkupaon_cm:0060:24"),
811
-	DT_CLK(NULL, "uart1_gfclk_mux", "l4per_cm:0140:24"),
812
-	DT_CLK(NULL, "uart2_gfclk_mux", "l4per_cm:0148:24"),
813
-	DT_CLK(NULL, "uart3_gfclk_mux", "l4per_cm:0150:24"),
814
-	DT_CLK(NULL, "uart4_gfclk_mux", "l4per_cm:0158:24"),
815
-	DT_CLK(NULL, "uart5_gfclk_mux", "l4per_cm:0170:24"),
816
-	DT_CLK(NULL, "uart6_gfclk_mux", "ipu_cm:0040:24"),
817
-	DT_CLK(NULL, "uart7_gfclk_mux", "l4per_cm:01d0:24"),
818
-	DT_CLK(NULL, "uart8_gfclk_mux", "l4per_cm:01e0:24"),
819
-	DT_CLK(NULL, "uart9_gfclk_mux", "l4per_cm:01e8:24"),
820
-	DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l3init_cm:00d0:8"),
821
-	DT_CLK(NULL, "usb_otg_ss2_refclk960m", "l3init_cm:0020:8"),
848
+	DT_CLK(NULL, "atl_dpll_clk_mux", "atl-clkctrl:0000:24"),
849
+	DT_CLK(NULL, "atl_gfclk_mux", "atl-clkctrl:0000:26"),
850
+	DT_CLK(NULL, "dcan1_sys_clk_mux", "wkupaon-clkctrl:0068:24"),
851
+	DT_CLK(NULL, "dss_32khz_clk", "dss-clkctrl:0000:11"),
852
+	DT_CLK(NULL, "dss_48mhz_clk", "dss-clkctrl:0000:9"),
853
+	DT_CLK(NULL, "dss_dss_clk", "dss-clkctrl:0000:8"),
854
+	DT_CLK(NULL, "dss_hdmi_clk", "dss-clkctrl:0000:10"),
855
+	DT_CLK(NULL, "dss_video1_clk", "dss-clkctrl:0000:12"),
856
+	DT_CLK(NULL, "dss_video2_clk", "dss-clkctrl:0000:13"),
857
+	DT_CLK(NULL, "gmac_rft_clk_mux", "gmac-clkctrl:0000:25"),
858
+	DT_CLK(NULL, "gpio1_dbclk", "wkupaon-clkctrl:0018:8"),
859
+	DT_CLK(NULL, "gpio2_dbclk", "l4per-clkctrl:0038:8"),
860
+	DT_CLK(NULL, "gpio3_dbclk", "l4per-clkctrl:0040:8"),
861
+	DT_CLK(NULL, "gpio4_dbclk", "l4per-clkctrl:0048:8"),
862
+	DT_CLK(NULL, "gpio5_dbclk", "l4per-clkctrl:0050:8"),
863
+	DT_CLK(NULL, "gpio6_dbclk", "l4per-clkctrl:0058:8"),
864
+	DT_CLK(NULL, "gpio7_dbclk", "l4per-clkctrl:00e8:8"),
865
+	DT_CLK(NULL, "gpio8_dbclk", "l4per-clkctrl:00f0:8"),
866
+	DT_CLK(NULL, "ipu1_gfclk_mux", "ipu1-clkctrl:0000:24"),
867
+	DT_CLK(NULL, "mcasp1_ahclkr_mux", "ipu-clkctrl:0000:28"),
868
+	DT_CLK(NULL, "mcasp1_ahclkx_mux", "ipu-clkctrl:0000:24"),
869
+	DT_CLK(NULL, "mcasp1_aux_gfclk_mux", "ipu-clkctrl:0000:22"),
870
+	DT_CLK(NULL, "mcasp2_ahclkr_mux", "l4per2-clkctrl:0154:28"),
871
+	DT_CLK(NULL, "mcasp2_ahclkx_mux", "l4per2-clkctrl:0154:24"),
872
+	DT_CLK(NULL, "mcasp2_aux_gfclk_mux", "l4per2-clkctrl:0154:22"),
873
+	DT_CLK(NULL, "mcasp3_ahclkx_mux", "l4per2-clkctrl:015c:24"),
874
+	DT_CLK(NULL, "mcasp3_aux_gfclk_mux", "l4per2-clkctrl:015c:22"),
875
+	DT_CLK(NULL, "mcasp4_ahclkx_mux", "l4per2-clkctrl:018c:24"),
876
+	DT_CLK(NULL, "mcasp4_aux_gfclk_mux", "l4per2-clkctrl:018c:22"),
877
+	DT_CLK(NULL, "mcasp5_ahclkx_mux", "l4per2-clkctrl:016c:24"),
878
+	DT_CLK(NULL, "mcasp5_aux_gfclk_mux", "l4per2-clkctrl:016c:22"),
879
+	DT_CLK(NULL, "mcasp6_ahclkx_mux", "l4per2-clkctrl:01f8:24"),
880
+	DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "l4per2-clkctrl:01f8:22"),
881
+	DT_CLK(NULL, "mcasp7_ahclkx_mux", "l4per2-clkctrl:01fc:24"),
882
+	DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "l4per2-clkctrl:01fc:22"),
883
+	DT_CLK(NULL, "mcasp8_ahclkx_mux", "l4per2-clkctrl:0184:24"),
884
+	DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "l4per2-clkctrl:0184:22"),
885
+	DT_CLK(NULL, "mmc1_clk32k", "l3init-clkctrl:0008:8"),
886
+	DT_CLK(NULL, "mmc1_fclk_div", "l3init-clkctrl:0008:25"),
887
+	DT_CLK(NULL, "mmc1_fclk_mux", "l3init-clkctrl:0008:24"),
888
+	DT_CLK(NULL, "mmc2_clk32k", "l3init-clkctrl:0010:8"),
889
+	DT_CLK(NULL, "mmc2_fclk_div", "l3init-clkctrl:0010:25"),
890
+	DT_CLK(NULL, "mmc2_fclk_mux", "l3init-clkctrl:0010:24"),
891
+	DT_CLK(NULL, "mmc3_clk32k", "l4per-clkctrl:00f8:8"),
892
+	DT_CLK(NULL, "mmc3_gfclk_div", "l4per-clkctrl:00f8:25"),
893
+	DT_CLK(NULL, "mmc3_gfclk_mux", "l4per-clkctrl:00f8:24"),
894
+	DT_CLK(NULL, "mmc4_clk32k", "l4per-clkctrl:0100:8"),
895
+	DT_CLK(NULL, "mmc4_gfclk_div", "l4per-clkctrl:0100:25"),
896
+	DT_CLK(NULL, "mmc4_gfclk_mux", "l4per-clkctrl:0100:24"),
897
+	DT_CLK(NULL, "optfclk_pciephy1_32khz", "pcie-clkctrl:0000:8"),
898
+	DT_CLK(NULL, "optfclk_pciephy1_clk", "pcie-clkctrl:0000:9"),
899
+	DT_CLK(NULL, "optfclk_pciephy1_div_clk", "pcie-clkctrl:0000:10"),
900
+	DT_CLK(NULL, "optfclk_pciephy2_32khz", "pcie-clkctrl:0008:8"),
901
+	DT_CLK(NULL, "optfclk_pciephy2_clk", "pcie-clkctrl:0008:9"),
902
+	DT_CLK(NULL, "optfclk_pciephy2_div_clk", "pcie-clkctrl:0008:10"),
903
+	DT_CLK(NULL, "qspi_gfclk_div", "l4per2-clkctrl:012c:25"),
904
+	DT_CLK(NULL, "qspi_gfclk_mux", "l4per2-clkctrl:012c:24"),
905
+	DT_CLK(NULL, "rmii_50mhz_clk_mux", "gmac-clkctrl:0000:24"),
906
+	DT_CLK(NULL, "sata_ref_clk", "l3init-clkctrl:0068:8"),
907
+	DT_CLK(NULL, "timer10_gfclk_mux", "l4per-clkctrl:0000:24"),
908
+	DT_CLK(NULL, "timer11_gfclk_mux", "l4per-clkctrl:0008:24"),
909
+	DT_CLK(NULL, "timer13_gfclk_mux", "l4per3-clkctrl:00b4:24"),
910
+	DT_CLK(NULL, "timer14_gfclk_mux", "l4per3-clkctrl:00bc:24"),
911
+	DT_CLK(NULL, "timer15_gfclk_mux", "l4per3-clkctrl:00c4:24"),
912
+	DT_CLK(NULL, "timer16_gfclk_mux", "l4per3-clkctrl:011c:24"),
913
+	DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon-clkctrl:0020:24"),
914
+	DT_CLK(NULL, "timer2_gfclk_mux", "l4per-clkctrl:0010:24"),
915
+	DT_CLK(NULL, "timer3_gfclk_mux", "l4per-clkctrl:0018:24"),
916
+	DT_CLK(NULL, "timer4_gfclk_mux", "l4per-clkctrl:0020:24"),
917
+	DT_CLK(NULL, "timer5_gfclk_mux", "ipu-clkctrl:0008:24"),
918
+	DT_CLK(NULL, "timer6_gfclk_mux", "ipu-clkctrl:0010:24"),
919
+	DT_CLK(NULL, "timer7_gfclk_mux", "ipu-clkctrl:0018:24"),
920
+	DT_CLK(NULL, "timer8_gfclk_mux", "ipu-clkctrl:0020:24"),
921
+	DT_CLK(NULL, "timer9_gfclk_mux", "l4per-clkctrl:0028:24"),
922
+	DT_CLK(NULL, "uart10_gfclk_mux", "wkupaon-clkctrl:0060:24"),
923
+	DT_CLK(NULL, "uart1_gfclk_mux", "l4per-clkctrl:0118:24"),
924
+	DT_CLK(NULL, "uart2_gfclk_mux", "l4per-clkctrl:0120:24"),
925
+	DT_CLK(NULL, "uart3_gfclk_mux", "l4per-clkctrl:0128:24"),
926
+	DT_CLK(NULL, "uart4_gfclk_mux", "l4per-clkctrl:0130:24"),
927
+	DT_CLK(NULL, "uart5_gfclk_mux", "l4per-clkctrl:0148:24"),
928
+	DT_CLK(NULL, "uart6_gfclk_mux", "ipu-clkctrl:0030:24"),
929
+	DT_CLK(NULL, "uart7_gfclk_mux", "l4per2-clkctrl:01c4:24"),
930
+	DT_CLK(NULL, "uart8_gfclk_mux", "l4per2-clkctrl:01d4:24"),
931
+	DT_CLK(NULL, "uart9_gfclk_mux", "l4per2-clkctrl:01dc:24"),
932
+	DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l3init-clkctrl:00d0:8"),
933
+	DT_CLK(NULL, "usb_otg_ss2_refclk960m", "l3init-clkctrl:0020:8"),
822934 	{ .node_name = NULL },
823935 };
824936 
....@@ -827,7 +939,10 @@
827939 	int rc;
828940 	struct clk *dpll_ck, *hdcp_ck;
829941 
830
-	ti_dt_clocks_register(dra7xx_clks);
942
+	if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
943
+		ti_dt_clocks_register(dra7xx_compat_clks);
944
+	else
945
+		ti_dt_clocks_register(dra7xx_clks);
831946 
832947 	omap2_clk_disable_autoidle_all();
833948