disable pwm7

hc

2024-05-10 23fa18eaa71266feff7ba8d83022d9e1cc83c65a

 kernel/drivers/clk/qcom/gcc-ipq806x.c
..
..
@@ -1,14 +1,6 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Copyright (c) 2014, The Linux Foundation. All rights reserved.
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- *
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- * This software is licensed under the terms of the GNU General Public
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- * License version 2, as published by the Free Software Foundation, and
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- * may be copied, distributed, and modified under those terms.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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  */
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 #include <linux/kernel.h>
..
..
@@ -30,6 +22,7 @@
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 #include "clk-pll.h"
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 #include "clk-rcg.h"
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 #include "clk-branch.h"
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+#include "clk-hfpll.h"
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 #include "reset.h"
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 static struct clk_pll pll0 = {
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@@ -111,6 +104,84 @@
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 		.num_parents = 1,
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 		.ops = &clk_pll_vote_ops,
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 	},
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+};
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+
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+static struct hfpll_data hfpll0_data = {
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+	.mode_reg = 0x3200,
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+	.l_reg = 0x3208,
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+	.m_reg = 0x320c,
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+	.n_reg = 0x3210,
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+	.config_reg = 0x3204,
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+	.status_reg = 0x321c,
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+	.config_val = 0x7845c665,
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+	.droop_reg = 0x3214,
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+	.droop_val = 0x0108c000,
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+	.min_rate = 600000000UL,
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+	.max_rate = 1800000000UL,
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+};
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+
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+static struct clk_hfpll hfpll0 = {
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+	.d = &hfpll0_data,
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+	.clkr.hw.init = &(struct clk_init_data){
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+		.parent_names = (const char *[]){ "pxo" },
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+		.num_parents = 1,
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+		.name = "hfpll0",
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+		.ops = &clk_ops_hfpll,
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+		.flags = CLK_IGNORE_UNUSED,
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+	},
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+	.lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock),
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+};
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+
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+static struct hfpll_data hfpll1_data = {
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+	.mode_reg = 0x3240,
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+	.l_reg = 0x3248,
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+	.m_reg = 0x324c,
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+	.n_reg = 0x3250,
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+	.config_reg = 0x3244,
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+	.status_reg = 0x325c,
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+	.config_val = 0x7845c665,
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+	.droop_reg = 0x3314,
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+	.droop_val = 0x0108c000,
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+	.min_rate = 600000000UL,
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+	.max_rate = 1800000000UL,
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+};
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+
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+static struct clk_hfpll hfpll1 = {
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+	.d = &hfpll1_data,
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+	.clkr.hw.init = &(struct clk_init_data){
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+		.parent_names = (const char *[]){ "pxo" },
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+		.num_parents = 1,
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+		.name = "hfpll1",
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+		.ops = &clk_ops_hfpll,
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+		.flags = CLK_IGNORE_UNUSED,
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+	},
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+	.lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock),
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+};
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+
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+static struct hfpll_data hfpll_l2_data = {
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+	.mode_reg = 0x3300,
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+	.l_reg = 0x3308,
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+	.m_reg = 0x330c,
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+	.n_reg = 0x3310,
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+	.config_reg = 0x3304,
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+	.status_reg = 0x331c,
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+	.config_val = 0x7845c665,
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+	.droop_reg = 0x3314,
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+	.droop_val = 0x0108c000,
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+	.min_rate = 600000000UL,
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+	.max_rate = 1800000000UL,
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+};
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+
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+static struct clk_hfpll hfpll_l2 = {
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+	.d = &hfpll_l2_data,
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+	.clkr.hw.init = &(struct clk_init_data){
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+		.parent_names = (const char *[]){ "pxo" },
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+		.num_parents = 1,
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+		.name = "hfpll_l2",
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+		.ops = &clk_ops_hfpll,
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+		.flags = CLK_IGNORE_UNUSED,
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+	},
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+	.lock = __SPIN_LOCK_UNLOCKED(hfpll_l2.lock),
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 };
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 static struct clk_pll pll14 = {
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@@ -1153,6 +1224,8 @@
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 		.parent_map = gcc_pxo_pll8_map,
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 	},
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 	.clkr = {
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+		.enable_reg = 0x2e80,
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+		.enable_mask = BIT(11),
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 		.hw.init = &(struct clk_init_data){
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 			.name = "prng_src",
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 			.parent_names = gcc_pxo_pll8,
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@@ -2797,6 +2870,9 @@
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 	[UBI32_CORE2_CLK_SRC] = &ubi32_core2_src_clk.clkr,
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 	[NSSTCM_CLK_SRC] = &nss_tcm_src.clkr,
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 	[NSSTCM_CLK] = &nss_tcm_clk.clkr,
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+	[PLL9] = &hfpll0.clkr,
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+	[PLL10] = &hfpll1.clkr,
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+	[PLL12] = &hfpll_l2.clkr,
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 };
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 static const struct qcom_reset_map gcc_ipq806x_resets[] = {
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@@ -3013,7 +3089,7 @@
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 	regmap_write(regmap, 0x3cf8, 8);
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 	regmap_write(regmap, 0x3d18, 8);
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-	return 0;
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+	return of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
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 }
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 static struct platform_driver gcc_ipq806x_driver = {