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2024-05-10 23fa18eaa71266feff7ba8d83022d9e1cc83c65a 
 kernel/drivers/clk/qcom/clk-smd-rpm.c
....@@ -1,15 +1,7 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * Copyright (c) 2016, Linaro Limited
34  * Copyright (c) 2014, The Linux Foundation. All rights reserved.
4
- *
5
- * This software is licensed under the terms of the GNU General Public
6
- * License version 2, as published by the Free Software Foundation, and
7
- * may be copied, distributed, and modified under those terms.
8
- *
9
- * This program is distributed in the hope that it will be useful,
10
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
11
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12
- * GNU General Public License for more details.
135  */
146 
157 #include <linux/clk-provider.h>
....@@ -460,6 +452,55 @@
460452 	.num_clks = ARRAY_SIZE(msm8916_clks),
461453 };
462454 
455
+/* msm8936 */
456
+DEFINE_CLK_SMD_RPM(msm8936, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
457
+DEFINE_CLK_SMD_RPM(msm8936, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
458
+DEFINE_CLK_SMD_RPM(msm8936, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
459
+DEFINE_CLK_SMD_RPM(msm8936, sysmmnoc_clk, sysmmnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
460
+DEFINE_CLK_SMD_RPM_QDSS(msm8936, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1);
461
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8936, bb_clk1, bb_clk1_a, 1);
462
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8936, bb_clk2, bb_clk2_a, 2);
463
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8936, rf_clk1, rf_clk1_a, 4);
464
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8936, rf_clk2, rf_clk2_a, 5);
465
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8936, bb_clk1_pin, bb_clk1_a_pin, 1);
466
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8936, bb_clk2_pin, bb_clk2_a_pin, 2);
467
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8936, rf_clk1_pin, rf_clk1_a_pin, 4);
468
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8936, rf_clk2_pin, rf_clk2_a_pin, 5);
469
+
470
+static struct clk_smd_rpm *msm8936_clks[] = {
471
+	[RPM_SMD_PCNOC_CLK]		= &msm8936_pcnoc_clk,
472
+	[RPM_SMD_PCNOC_A_CLK]		= &msm8936_pcnoc_a_clk,
473
+	[RPM_SMD_SNOC_CLK]		= &msm8936_snoc_clk,
474
+	[RPM_SMD_SNOC_A_CLK]		= &msm8936_snoc_a_clk,
475
+	[RPM_SMD_BIMC_CLK]		= &msm8936_bimc_clk,
476
+	[RPM_SMD_BIMC_A_CLK]		= &msm8936_bimc_a_clk,
477
+	[RPM_SMD_SYSMMNOC_CLK]		= &msm8936_sysmmnoc_clk,
478
+	[RPM_SMD_SYSMMNOC_A_CLK]	= &msm8936_sysmmnoc_a_clk,
479
+	[RPM_SMD_QDSS_CLK]		= &msm8936_qdss_clk,
480
+	[RPM_SMD_QDSS_A_CLK]		= &msm8936_qdss_a_clk,
481
+	[RPM_SMD_BB_CLK1]		= &msm8936_bb_clk1,
482
+	[RPM_SMD_BB_CLK1_A]		= &msm8936_bb_clk1_a,
483
+	[RPM_SMD_BB_CLK2]		= &msm8936_bb_clk2,
484
+	[RPM_SMD_BB_CLK2_A]		= &msm8936_bb_clk2_a,
485
+	[RPM_SMD_RF_CLK1]		= &msm8936_rf_clk1,
486
+	[RPM_SMD_RF_CLK1_A]		= &msm8936_rf_clk1_a,
487
+	[RPM_SMD_RF_CLK2]		= &msm8936_rf_clk2,
488
+	[RPM_SMD_RF_CLK2_A]		= &msm8936_rf_clk2_a,
489
+	[RPM_SMD_BB_CLK1_PIN]		= &msm8936_bb_clk1_pin,
490
+	[RPM_SMD_BB_CLK1_A_PIN]		= &msm8936_bb_clk1_a_pin,
491
+	[RPM_SMD_BB_CLK2_PIN]		= &msm8936_bb_clk2_pin,
492
+	[RPM_SMD_BB_CLK2_A_PIN]		= &msm8936_bb_clk2_a_pin,
493
+	[RPM_SMD_RF_CLK1_PIN]		= &msm8936_rf_clk1_pin,
494
+	[RPM_SMD_RF_CLK1_A_PIN]		= &msm8936_rf_clk1_a_pin,
495
+	[RPM_SMD_RF_CLK2_PIN]		= &msm8936_rf_clk2_pin,
496
+	[RPM_SMD_RF_CLK2_A_PIN]		= &msm8936_rf_clk2_a_pin,
497
+};
498
+
499
+static const struct rpm_smd_clk_desc rpm_clk_msm8936 = {
500
+		.clks = msm8936_clks,
501
+		.num_clks = ARRAY_SIZE(msm8936_clks),
502
+};
503
+
463504 /* msm8974 */
464505 DEFINE_CLK_SMD_RPM(msm8974, pnoc_clk, pnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
465506 DEFINE_CLK_SMD_RPM(msm8974, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
....@@ -493,6 +534,8 @@
493534 	[RPM_SMD_MMSSNOC_AHB_CLK]	= &msm8974_mmssnoc_ahb_clk,
494535 	[RPM_SMD_MMSSNOC_AHB_A_CLK]	= &msm8974_mmssnoc_ahb_a_clk,
495536 	[RPM_SMD_BIMC_CLK]		= &msm8974_bimc_clk,
537
+	[RPM_SMD_GFX3D_CLK_SRC]		= &msm8974_gfx3d_clk_src,
538
+	[RPM_SMD_GFX3D_A_CLK_SRC]	= &msm8974_gfx3d_a_clk_src,
496539 	[RPM_SMD_BIMC_A_CLK]		= &msm8974_bimc_a_clk,
497540 	[RPM_SMD_OCMEMGX_CLK]		= &msm8974_ocmemgx_clk,
498541 	[RPM_SMD_OCMEMGX_A_CLK]		= &msm8974_ocmemgx_a_clk,
....@@ -529,6 +572,224 @@
529572 static const struct rpm_smd_clk_desc rpm_clk_msm8974 = {
530573 	.clks = msm8974_clks,
531574 	.num_clks = ARRAY_SIZE(msm8974_clks),
575
+};
576
+
577
+
578
+/* msm8976 */
579
+DEFINE_CLK_SMD_RPM(msm8976, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
580
+DEFINE_CLK_SMD_RPM(msm8976, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
581
+DEFINE_CLK_SMD_RPM(msm8976, mmssnoc_ahb_clk, mmssnoc_ahb_a_clk,
582
+		   QCOM_SMD_RPM_BUS_CLK, 2);
583
+DEFINE_CLK_SMD_RPM(msm8976, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
584
+DEFINE_CLK_SMD_RPM(msm8976, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0);
585
+DEFINE_CLK_SMD_RPM_QDSS(msm8976, qdss_clk, qdss_a_clk,
586
+			QCOM_SMD_RPM_MISC_CLK, 1);
587
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8976, bb_clk1, bb_clk1_a, 1);
588
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8976, bb_clk2, bb_clk2_a, 2);
589
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8976, rf_clk2, rf_clk2_a, 5);
590
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8976, div_clk2, div_clk2_a, 12);
591
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8976, bb_clk1_pin, bb_clk1_a_pin, 1);
592
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8976, bb_clk2_pin, bb_clk2_a_pin, 2);
593
+
594
+static struct clk_smd_rpm *msm8976_clks[] = {
595
+	[RPM_SMD_PCNOC_CLK] = &msm8976_pcnoc_clk,
596
+	[RPM_SMD_PCNOC_A_CLK] = &msm8976_pcnoc_a_clk,
597
+	[RPM_SMD_SNOC_CLK] = &msm8976_snoc_clk,
598
+	[RPM_SMD_SNOC_A_CLK] = &msm8976_snoc_a_clk,
599
+	[RPM_SMD_BIMC_CLK] = &msm8976_bimc_clk,
600
+	[RPM_SMD_BIMC_A_CLK] = &msm8976_bimc_a_clk,
601
+	[RPM_SMD_QDSS_CLK] = &msm8976_qdss_clk,
602
+	[RPM_SMD_QDSS_A_CLK] = &msm8976_qdss_a_clk,
603
+	[RPM_SMD_BB_CLK1] = &msm8976_bb_clk1,
604
+	[RPM_SMD_BB_CLK1_A] = &msm8976_bb_clk1_a,
605
+	[RPM_SMD_BB_CLK2] = &msm8976_bb_clk2,
606
+	[RPM_SMD_BB_CLK2_A] = &msm8976_bb_clk2_a,
607
+	[RPM_SMD_RF_CLK2] = &msm8976_rf_clk2,
608
+	[RPM_SMD_RF_CLK2_A] = &msm8976_rf_clk2_a,
609
+	[RPM_SMD_BB_CLK1_PIN] = &msm8976_bb_clk1_pin,
610
+	[RPM_SMD_BB_CLK1_A_PIN] = &msm8976_bb_clk1_a_pin,
611
+	[RPM_SMD_BB_CLK2_PIN] = &msm8976_bb_clk2_pin,
612
+	[RPM_SMD_BB_CLK2_A_PIN] = &msm8976_bb_clk2_a_pin,
613
+	[RPM_SMD_MMSSNOC_AHB_CLK] = &msm8976_mmssnoc_ahb_clk,
614
+	[RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8976_mmssnoc_ahb_a_clk,
615
+	[RPM_SMD_DIV_CLK2] = &msm8976_div_clk2,
616
+	[RPM_SMD_DIV_A_CLK2] = &msm8976_div_clk2_a,
617
+	[RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
618
+	[RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
619
+};
620
+
621
+static const struct rpm_smd_clk_desc rpm_clk_msm8976 = {
622
+	.clks = msm8976_clks,
623
+	.num_clks = ARRAY_SIZE(msm8976_clks),
624
+};
625
+
626
+/* msm8992 */
627
+DEFINE_CLK_SMD_RPM(msm8992, pnoc_clk, pnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
628
+DEFINE_CLK_SMD_RPM(msm8992, ocmemgx_clk, ocmemgx_a_clk, QCOM_SMD_RPM_MEM_CLK, 2);
629
+DEFINE_CLK_SMD_RPM(msm8992, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
630
+DEFINE_CLK_SMD_RPM(msm8992, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
631
+DEFINE_CLK_SMD_RPM(msm8992, gfx3d_clk_src, gfx3d_a_clk_src, QCOM_SMD_RPM_MEM_CLK, 1);
632
+DEFINE_CLK_SMD_RPM(msm8992, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
633
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, bb_clk1, bb_clk1_a, 1);
634
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8992, bb_clk1_pin, bb_clk1_a_pin, 1);
635
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, bb_clk2, bb_clk2_a, 2);
636
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8992, bb_clk2_pin, bb_clk2_a_pin, 2);
637
+
638
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, div_clk1, div_clk1_a, 11);
639
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, div_clk2, div_clk2_a, 12);
640
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, div_clk3, div_clk3_a, 13);
641
+DEFINE_CLK_SMD_RPM(msm8992, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0);
642
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, ln_bb_clk, ln_bb_a_clk, 8);
643
+DEFINE_CLK_SMD_RPM(msm8992, mmssnoc_ahb_clk, mmssnoc_ahb_a_clk,
644
+		   QCOM_SMD_RPM_BUS_CLK, 3);
645
+DEFINE_CLK_SMD_RPM_QDSS(msm8992, qdss_clk, qdss_a_clk,
646
+			QCOM_SMD_RPM_MISC_CLK, 1);
647
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, rf_clk1, rf_clk1_a, 4);
648
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, rf_clk2, rf_clk2_a, 5);
649
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8992, rf_clk1_pin, rf_clk1_a_pin, 4);
650
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8992, rf_clk2_pin, rf_clk2_a_pin, 5);
651
+
652
+DEFINE_CLK_SMD_RPM(msm8992, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);
653
+DEFINE_CLK_SMD_RPM(msm8992, ce2_clk, ce2_a_clk, QCOM_SMD_RPM_CE_CLK, 1);
654
+
655
+static struct clk_smd_rpm *msm8992_clks[] = {
656
+	[RPM_SMD_PNOC_CLK] = &msm8992_pnoc_clk,
657
+	[RPM_SMD_PNOC_A_CLK] = &msm8992_pnoc_a_clk,
658
+	[RPM_SMD_OCMEMGX_CLK] = &msm8992_ocmemgx_clk,
659
+	[RPM_SMD_OCMEMGX_A_CLK] = &msm8992_ocmemgx_a_clk,
660
+	[RPM_SMD_BIMC_CLK] = &msm8992_bimc_clk,
661
+	[RPM_SMD_BIMC_A_CLK] = &msm8992_bimc_a_clk,
662
+	[RPM_SMD_CNOC_CLK] = &msm8992_cnoc_clk,
663
+	[RPM_SMD_CNOC_A_CLK] = &msm8992_cnoc_a_clk,
664
+	[RPM_SMD_GFX3D_CLK_SRC] = &msm8992_gfx3d_clk_src,
665
+	[RPM_SMD_GFX3D_A_CLK_SRC] = &msm8992_gfx3d_a_clk_src,
666
+	[RPM_SMD_SNOC_CLK] = &msm8992_snoc_clk,
667
+	[RPM_SMD_SNOC_A_CLK] = &msm8992_snoc_a_clk,
668
+	[RPM_SMD_BB_CLK1] = &msm8992_bb_clk1,
669
+	[RPM_SMD_BB_CLK1_A] = &msm8992_bb_clk1_a,
670
+	[RPM_SMD_BB_CLK1_PIN] = &msm8992_bb_clk1_pin,
671
+	[RPM_SMD_BB_CLK1_A_PIN] = &msm8992_bb_clk1_a_pin,
672
+	[RPM_SMD_BB_CLK2] = &msm8992_bb_clk2,
673
+	[RPM_SMD_BB_CLK2_A] = &msm8992_bb_clk2_a,
674
+	[RPM_SMD_BB_CLK2_PIN] = &msm8992_bb_clk2_pin,
675
+	[RPM_SMD_BB_CLK2_A_PIN] = &msm8992_bb_clk2_a_pin,
676
+	[RPM_SMD_DIV_CLK1] = &msm8992_div_clk1,
677
+	[RPM_SMD_DIV_A_CLK1] = &msm8992_div_clk1_a,
678
+	[RPM_SMD_DIV_CLK2] = &msm8992_div_clk2,
679
+	[RPM_SMD_DIV_A_CLK2] = &msm8992_div_clk2_a,
680
+	[RPM_SMD_DIV_CLK3] = &msm8992_div_clk3,
681
+	[RPM_SMD_DIV_A_CLK3] = &msm8992_div_clk3_a,
682
+	[RPM_SMD_IPA_CLK] = &msm8992_ipa_clk,
683
+	[RPM_SMD_IPA_A_CLK] = &msm8992_ipa_a_clk,
684
+	[RPM_SMD_LN_BB_CLK] = &msm8992_ln_bb_clk,
685
+	[RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk,
686
+	[RPM_SMD_MMSSNOC_AHB_CLK] = &msm8992_mmssnoc_ahb_clk,
687
+	[RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8992_mmssnoc_ahb_a_clk,
688
+	[RPM_SMD_QDSS_CLK] = &msm8992_qdss_clk,
689
+	[RPM_SMD_QDSS_A_CLK] = &msm8992_qdss_a_clk,
690
+	[RPM_SMD_RF_CLK1] = &msm8992_rf_clk1,
691
+	[RPM_SMD_RF_CLK1_A] = &msm8992_rf_clk1_a,
692
+	[RPM_SMD_RF_CLK2] = &msm8992_rf_clk2,
693
+	[RPM_SMD_RF_CLK2_A] = &msm8992_rf_clk2_a,
694
+	[RPM_SMD_RF_CLK1_PIN] = &msm8992_rf_clk1_pin,
695
+	[RPM_SMD_RF_CLK1_A_PIN] = &msm8992_rf_clk1_a_pin,
696
+	[RPM_SMD_RF_CLK2_PIN] = &msm8992_rf_clk2_pin,
697
+	[RPM_SMD_RF_CLK2_A_PIN] = &msm8992_rf_clk2_a_pin,
698
+	[RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
699
+	[RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
700
+	[RPM_SMD_CE2_CLK] = &msm8992_ce2_clk,
701
+	[RPM_SMD_CE2_A_CLK] = &msm8992_ce2_a_clk,
702
+};
703
+
704
+static const struct rpm_smd_clk_desc rpm_clk_msm8992 = {
705
+	.clks = msm8992_clks,
706
+	.num_clks = ARRAY_SIZE(msm8992_clks),
707
+};
708
+
709
+/* msm8994 */
710
+DEFINE_CLK_SMD_RPM(msm8994, pnoc_clk, pnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
711
+DEFINE_CLK_SMD_RPM(msm8994, ocmemgx_clk, ocmemgx_a_clk, QCOM_SMD_RPM_MEM_CLK, 2);
712
+DEFINE_CLK_SMD_RPM(msm8994, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
713
+DEFINE_CLK_SMD_RPM(msm8994, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
714
+DEFINE_CLK_SMD_RPM(msm8994, gfx3d_clk_src, gfx3d_a_clk_src, QCOM_SMD_RPM_MEM_CLK, 1);
715
+DEFINE_CLK_SMD_RPM(msm8994, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
716
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, bb_clk1, bb_clk1_a, 1);
717
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8994, bb_clk1_pin, bb_clk1_a_pin, 1);
718
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, bb_clk2, bb_clk2_a, 2);
719
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8994, bb_clk2_pin, bb_clk2_a_pin, 2);
720
+
721
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, div_clk1, div_clk1_a, 11);
722
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, div_clk2, div_clk2_a, 12);
723
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, div_clk3, div_clk3_a, 13);
724
+DEFINE_CLK_SMD_RPM(msm8994, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0);
725
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, ln_bb_clk, ln_bb_a_clk, 8);
726
+DEFINE_CLK_SMD_RPM(msm8994, mmssnoc_ahb_clk, mmssnoc_ahb_a_clk,
727
+		   QCOM_SMD_RPM_BUS_CLK, 3);
728
+DEFINE_CLK_SMD_RPM_QDSS(msm8994, qdss_clk, qdss_a_clk,
729
+			QCOM_SMD_RPM_MISC_CLK, 1);
730
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, rf_clk1, rf_clk1_a, 4);
731
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, rf_clk2, rf_clk2_a, 5);
732
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8994, rf_clk1_pin, rf_clk1_a_pin, 4);
733
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8994, rf_clk2_pin, rf_clk2_a_pin, 5);
734
+
735
+DEFINE_CLK_SMD_RPM(msm8994, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);
736
+DEFINE_CLK_SMD_RPM(msm8994, ce2_clk, ce2_a_clk, QCOM_SMD_RPM_CE_CLK, 1);
737
+DEFINE_CLK_SMD_RPM(msm8994, ce3_clk, ce3_a_clk, QCOM_SMD_RPM_CE_CLK, 2);
738
+
739
+static struct clk_smd_rpm *msm8994_clks[] = {
740
+	[RPM_SMD_PNOC_CLK] = &msm8994_pnoc_clk,
741
+	[RPM_SMD_PNOC_A_CLK] = &msm8994_pnoc_a_clk,
742
+	[RPM_SMD_OCMEMGX_CLK] = &msm8994_ocmemgx_clk,
743
+	[RPM_SMD_OCMEMGX_A_CLK] = &msm8994_ocmemgx_a_clk,
744
+	[RPM_SMD_BIMC_CLK] = &msm8994_bimc_clk,
745
+	[RPM_SMD_BIMC_A_CLK] = &msm8994_bimc_a_clk,
746
+	[RPM_SMD_CNOC_CLK] = &msm8994_cnoc_clk,
747
+	[RPM_SMD_CNOC_A_CLK] = &msm8994_cnoc_a_clk,
748
+	[RPM_SMD_GFX3D_CLK_SRC] = &msm8994_gfx3d_clk_src,
749
+	[RPM_SMD_GFX3D_A_CLK_SRC] = &msm8994_gfx3d_a_clk_src,
750
+	[RPM_SMD_SNOC_CLK] = &msm8994_snoc_clk,
751
+	[RPM_SMD_SNOC_A_CLK] = &msm8994_snoc_a_clk,
752
+	[RPM_SMD_BB_CLK1] = &msm8994_bb_clk1,
753
+	[RPM_SMD_BB_CLK1_A] = &msm8994_bb_clk1_a,
754
+	[RPM_SMD_BB_CLK1_PIN] = &msm8994_bb_clk1_pin,
755
+	[RPM_SMD_BB_CLK1_A_PIN] = &msm8994_bb_clk1_a_pin,
756
+	[RPM_SMD_BB_CLK2] = &msm8994_bb_clk2,
757
+	[RPM_SMD_BB_CLK2_A] = &msm8994_bb_clk2_a,
758
+	[RPM_SMD_BB_CLK2_PIN] = &msm8994_bb_clk2_pin,
759
+	[RPM_SMD_BB_CLK2_A_PIN] = &msm8994_bb_clk2_a_pin,
760
+	[RPM_SMD_DIV_CLK1] = &msm8994_div_clk1,
761
+	[RPM_SMD_DIV_A_CLK1] = &msm8994_div_clk1_a,
762
+	[RPM_SMD_DIV_CLK2] = &msm8994_div_clk2,
763
+	[RPM_SMD_DIV_A_CLK2] = &msm8994_div_clk2_a,
764
+	[RPM_SMD_DIV_CLK3] = &msm8994_div_clk3,
765
+	[RPM_SMD_DIV_A_CLK3] = &msm8994_div_clk3_a,
766
+	[RPM_SMD_IPA_CLK] = &msm8994_ipa_clk,
767
+	[RPM_SMD_IPA_A_CLK] = &msm8994_ipa_a_clk,
768
+	[RPM_SMD_LN_BB_CLK] = &msm8994_ln_bb_clk,
769
+	[RPM_SMD_LN_BB_A_CLK] = &msm8994_ln_bb_a_clk,
770
+	[RPM_SMD_MMSSNOC_AHB_CLK] = &msm8994_mmssnoc_ahb_clk,
771
+	[RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8994_mmssnoc_ahb_a_clk,
772
+	[RPM_SMD_QDSS_CLK] = &msm8994_qdss_clk,
773
+	[RPM_SMD_QDSS_A_CLK] = &msm8994_qdss_a_clk,
774
+	[RPM_SMD_RF_CLK1] = &msm8994_rf_clk1,
775
+	[RPM_SMD_RF_CLK1_A] = &msm8994_rf_clk1_a,
776
+	[RPM_SMD_RF_CLK2] = &msm8994_rf_clk2,
777
+	[RPM_SMD_RF_CLK2_A] = &msm8994_rf_clk2_a,
778
+	[RPM_SMD_RF_CLK1_PIN] = &msm8994_rf_clk1_pin,
779
+	[RPM_SMD_RF_CLK1_A_PIN] = &msm8994_rf_clk1_a_pin,
780
+	[RPM_SMD_RF_CLK2_PIN] = &msm8994_rf_clk2_pin,
781
+	[RPM_SMD_RF_CLK2_A_PIN] = &msm8994_rf_clk2_a_pin,
782
+	[RPM_SMD_CE1_CLK] = &msm8994_ce1_clk,
783
+	[RPM_SMD_CE1_A_CLK] = &msm8994_ce1_a_clk,
784
+	[RPM_SMD_CE2_CLK] = &msm8994_ce2_clk,
785
+	[RPM_SMD_CE2_A_CLK] = &msm8994_ce2_a_clk,
786
+	[RPM_SMD_CE3_CLK] = &msm8994_ce3_clk,
787
+	[RPM_SMD_CE3_A_CLK] = &msm8994_ce3_a_clk,
788
+};
789
+
790
+static const struct rpm_smd_clk_desc rpm_clk_msm8994 = {
791
+	.clks = msm8994_clks,
792
+	.num_clks = ARRAY_SIZE(msm8994_clks),
532793 };
533794 
534795 /* msm8996 */
....@@ -611,10 +872,204 @@
611872 	.num_clks = ARRAY_SIZE(msm8996_clks),
612873 };
613874 
875
+/* QCS404 */
876
+DEFINE_CLK_SMD_RPM_QDSS(qcs404, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1);
877
+
878
+DEFINE_CLK_SMD_RPM(qcs404, pnoc_clk, pnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
879
+DEFINE_CLK_SMD_RPM(qcs404, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
880
+
881
+DEFINE_CLK_SMD_RPM(qcs404, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
882
+DEFINE_CLK_SMD_RPM(qcs404, bimc_gpu_clk, bimc_gpu_a_clk, QCOM_SMD_RPM_MEM_CLK, 2);
883
+
884
+DEFINE_CLK_SMD_RPM(qcs404, qpic_clk, qpic_a_clk, QCOM_SMD_RPM_QPIC_CLK, 0);
885
+DEFINE_CLK_SMD_RPM(qcs404, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);
886
+
887
+DEFINE_CLK_SMD_RPM_XO_BUFFER(qcs404, rf_clk1, rf_clk1_a, 4);
888
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs404, rf_clk1_pin, rf_clk1_a_pin, 4);
889
+
890
+DEFINE_CLK_SMD_RPM_XO_BUFFER(qcs404, ln_bb_clk, ln_bb_a_clk, 8);
891
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs404, ln_bb_clk_pin, ln_bb_clk_a_pin, 8);
892
+
893
+static struct clk_smd_rpm *qcs404_clks[] = {
894
+	[RPM_SMD_QDSS_CLK] = &qcs404_qdss_clk,
895
+	[RPM_SMD_QDSS_A_CLK] = &qcs404_qdss_a_clk,
896
+	[RPM_SMD_PNOC_CLK] = &qcs404_pnoc_clk,
897
+	[RPM_SMD_PNOC_A_CLK] = &qcs404_pnoc_a_clk,
898
+	[RPM_SMD_SNOC_CLK] = &qcs404_snoc_clk,
899
+	[RPM_SMD_SNOC_A_CLK] = &qcs404_snoc_a_clk,
900
+	[RPM_SMD_BIMC_CLK] = &qcs404_bimc_clk,
901
+	[RPM_SMD_BIMC_A_CLK] = &qcs404_bimc_a_clk,
902
+	[RPM_SMD_BIMC_GPU_CLK] = &qcs404_bimc_gpu_clk,
903
+	[RPM_SMD_BIMC_GPU_A_CLK] = &qcs404_bimc_gpu_a_clk,
904
+	[RPM_SMD_QPIC_CLK] = &qcs404_qpic_clk,
905
+	[RPM_SMD_QPIC_CLK_A] = &qcs404_qpic_a_clk,
906
+	[RPM_SMD_CE1_CLK] = &qcs404_ce1_clk,
907
+	[RPM_SMD_CE1_A_CLK] = &qcs404_ce1_a_clk,
908
+	[RPM_SMD_RF_CLK1] = &qcs404_rf_clk1,
909
+	[RPM_SMD_RF_CLK1_A] = &qcs404_rf_clk1_a,
910
+	[RPM_SMD_LN_BB_CLK] = &qcs404_ln_bb_clk,
911
+	[RPM_SMD_LN_BB_A_CLK] = &qcs404_ln_bb_a_clk,
912
+};
913
+
914
+static const struct rpm_smd_clk_desc rpm_clk_qcs404 = {
915
+	.clks = qcs404_clks,
916
+	.num_clks = ARRAY_SIZE(qcs404_clks),
917
+};
918
+
919
+/* msm8998 */
920
+DEFINE_CLK_SMD_RPM(msm8998, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
921
+DEFINE_CLK_SMD_RPM(msm8998, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
922
+DEFINE_CLK_SMD_RPM(msm8998, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
923
+DEFINE_CLK_SMD_RPM(msm8998, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
924
+DEFINE_CLK_SMD_RPM(msm8998, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);
925
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, div_clk1, div_clk1_a, 0xb);
926
+DEFINE_CLK_SMD_RPM(msm8998, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0);
927
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, ln_bb_clk1, ln_bb_clk1_a, 1);
928
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, ln_bb_clk2, ln_bb_clk2_a, 2);
929
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk3_pin, ln_bb_clk3_a_pin,
930
+				     3);
931
+DEFINE_CLK_SMD_RPM(msm8998, mmssnoc_axi_rpm_clk, mmssnoc_axi_rpm_a_clk,
932
+		   QCOM_SMD_RPM_MMAXI_CLK, 0);
933
+DEFINE_CLK_SMD_RPM(msm8998, aggre1_noc_clk, aggre1_noc_a_clk,
934
+		   QCOM_SMD_RPM_AGGR_CLK, 1);
935
+DEFINE_CLK_SMD_RPM(msm8998, aggre2_noc_clk, aggre2_noc_a_clk,
936
+		   QCOM_SMD_RPM_AGGR_CLK, 2);
937
+DEFINE_CLK_SMD_RPM_QDSS(msm8998, qdss_clk, qdss_a_clk,
938
+			QCOM_SMD_RPM_MISC_CLK, 1);
939
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, rf_clk1, rf_clk1_a, 4);
940
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, rf_clk2_pin, rf_clk2_a_pin, 5);
941
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, rf_clk3, rf_clk3_a, 6);
942
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, rf_clk3_pin, rf_clk3_a_pin, 6);
943
+static struct clk_smd_rpm *msm8998_clks[] = {
944
+	[RPM_SMD_BIMC_CLK] = &msm8998_bimc_clk,
945
+	[RPM_SMD_BIMC_A_CLK] = &msm8998_bimc_a_clk,
946
+	[RPM_SMD_PCNOC_CLK] = &msm8998_pcnoc_clk,
947
+	[RPM_SMD_PCNOC_A_CLK] = &msm8998_pcnoc_a_clk,
948
+	[RPM_SMD_SNOC_CLK] = &msm8998_snoc_clk,
949
+	[RPM_SMD_SNOC_A_CLK] = &msm8998_snoc_a_clk,
950
+	[RPM_SMD_CNOC_CLK] = &msm8998_cnoc_clk,
951
+	[RPM_SMD_CNOC_A_CLK] = &msm8998_cnoc_a_clk,
952
+	[RPM_SMD_CE1_CLK] = &msm8998_ce1_clk,
953
+	[RPM_SMD_CE1_A_CLK] = &msm8998_ce1_a_clk,
954
+	[RPM_SMD_DIV_CLK1] = &msm8998_div_clk1,
955
+	[RPM_SMD_DIV_A_CLK1] = &msm8998_div_clk1_a,
956
+	[RPM_SMD_IPA_CLK] = &msm8998_ipa_clk,
957
+	[RPM_SMD_IPA_A_CLK] = &msm8998_ipa_a_clk,
958
+	[RPM_SMD_LN_BB_CLK1] = &msm8998_ln_bb_clk1,
959
+	[RPM_SMD_LN_BB_CLK1_A] = &msm8998_ln_bb_clk1_a,
960
+	[RPM_SMD_LN_BB_CLK2] = &msm8998_ln_bb_clk2,
961
+	[RPM_SMD_LN_BB_CLK2_A] = &msm8998_ln_bb_clk2_a,
962
+	[RPM_SMD_LN_BB_CLK3_PIN] = &msm8998_ln_bb_clk3_pin,
963
+	[RPM_SMD_LN_BB_CLK3_A_PIN] = &msm8998_ln_bb_clk3_a_pin,
964
+	[RPM_SMD_MMAXI_CLK] = &msm8998_mmssnoc_axi_rpm_clk,
965
+	[RPM_SMD_MMAXI_A_CLK] = &msm8998_mmssnoc_axi_rpm_a_clk,
966
+	[RPM_SMD_AGGR1_NOC_CLK] = &msm8998_aggre1_noc_clk,
967
+	[RPM_SMD_AGGR1_NOC_A_CLK] = &msm8998_aggre1_noc_a_clk,
968
+	[RPM_SMD_AGGR2_NOC_CLK] = &msm8998_aggre2_noc_clk,
969
+	[RPM_SMD_AGGR2_NOC_A_CLK] = &msm8998_aggre2_noc_a_clk,
970
+	[RPM_SMD_QDSS_CLK] = &msm8998_qdss_clk,
971
+	[RPM_SMD_QDSS_A_CLK] = &msm8998_qdss_a_clk,
972
+	[RPM_SMD_RF_CLK1] = &msm8998_rf_clk1,
973
+	[RPM_SMD_RF_CLK1_A] = &msm8998_rf_clk1_a,
974
+	[RPM_SMD_RF_CLK2_PIN] = &msm8998_rf_clk2_pin,
975
+	[RPM_SMD_RF_CLK2_A_PIN] = &msm8998_rf_clk2_a_pin,
976
+	[RPM_SMD_RF_CLK3] = &msm8998_rf_clk3,
977
+	[RPM_SMD_RF_CLK3_A] = &msm8998_rf_clk3_a,
978
+	[RPM_SMD_RF_CLK3_PIN] = &msm8998_rf_clk3_pin,
979
+	[RPM_SMD_RF_CLK3_A_PIN] = &msm8998_rf_clk3_a_pin,
980
+};
981
+
982
+static const struct rpm_smd_clk_desc rpm_clk_msm8998 = {
983
+	.clks = msm8998_clks,
984
+	.num_clks = ARRAY_SIZE(msm8998_clks),
985
+};
986
+
987
+/* sdm660 */
988
+DEFINE_CLK_SMD_RPM_BRANCH(sdm660, bi_tcxo, bi_tcxo_a, QCOM_SMD_RPM_MISC_CLK, 0,
989
+								19200000);
990
+DEFINE_CLK_SMD_RPM(sdm660, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
991
+DEFINE_CLK_SMD_RPM(sdm660, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
992
+DEFINE_CLK_SMD_RPM(sdm660, cnoc_periph_clk, cnoc_periph_a_clk,
993
+						QCOM_SMD_RPM_BUS_CLK, 0);
994
+DEFINE_CLK_SMD_RPM(sdm660, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
995
+DEFINE_CLK_SMD_RPM(sdm660, mmssnoc_axi_clk, mmssnoc_axi_a_clk,
996
+						   QCOM_SMD_RPM_MMAXI_CLK, 0);
997
+DEFINE_CLK_SMD_RPM(sdm660, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0);
998
+DEFINE_CLK_SMD_RPM(sdm660, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);
999
+DEFINE_CLK_SMD_RPM(sdm660, aggre2_noc_clk, aggre2_noc_a_clk,
1000
+						QCOM_SMD_RPM_AGGR_CLK, 2);
1001
+DEFINE_CLK_SMD_RPM_QDSS(sdm660, qdss_clk, qdss_a_clk,
1002
+						QCOM_SMD_RPM_MISC_CLK, 1);
1003
+DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, rf_clk1, rf_clk1_a, 4);
1004
+DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, div_clk1, div_clk1_a, 11);
1005
+DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk1, ln_bb_clk1_a, 1);
1006
+DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk2, ln_bb_clk2_a, 2);
1007
+DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk3, ln_bb_clk3_a, 3);
1008
+
1009
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, rf_clk1_pin, rf_clk1_a_pin, 4);
1010
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk1_pin,
1011
+							ln_bb_clk1_pin_a, 1);
1012
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk2_pin,
1013
+							ln_bb_clk2_pin_a, 2);
1014
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk3_pin,
1015
+							ln_bb_clk3_pin_a, 3);
1016
+static struct clk_smd_rpm *sdm660_clks[] = {
1017
+	[RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo,
1018
+	[RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a,
1019
+	[RPM_SMD_SNOC_CLK] = &sdm660_snoc_clk,
1020
+	[RPM_SMD_SNOC_A_CLK] = &sdm660_snoc_a_clk,
1021
+	[RPM_SMD_CNOC_CLK] = &sdm660_cnoc_clk,
1022
+	[RPM_SMD_CNOC_A_CLK] = &sdm660_cnoc_a_clk,
1023
+	[RPM_SMD_CNOC_PERIPH_CLK] = &sdm660_cnoc_periph_clk,
1024
+	[RPM_SMD_CNOC_PERIPH_A_CLK] = &sdm660_cnoc_periph_a_clk,
1025
+	[RPM_SMD_BIMC_CLK] = &sdm660_bimc_clk,
1026
+	[RPM_SMD_BIMC_A_CLK] = &sdm660_bimc_a_clk,
1027
+	[RPM_SMD_MMSSNOC_AXI_CLK] = &sdm660_mmssnoc_axi_clk,
1028
+	[RPM_SMD_MMSSNOC_AXI_CLK_A] = &sdm660_mmssnoc_axi_a_clk,
1029
+	[RPM_SMD_IPA_CLK] = &sdm660_ipa_clk,
1030
+	[RPM_SMD_IPA_A_CLK] = &sdm660_ipa_a_clk,
1031
+	[RPM_SMD_CE1_CLK] = &sdm660_ce1_clk,
1032
+	[RPM_SMD_CE1_A_CLK] = &sdm660_ce1_a_clk,
1033
+	[RPM_SMD_AGGR2_NOC_CLK] = &sdm660_aggre2_noc_clk,
1034
+	[RPM_SMD_AGGR2_NOC_A_CLK] = &sdm660_aggre2_noc_a_clk,
1035
+	[RPM_SMD_QDSS_CLK] = &sdm660_qdss_clk,
1036
+	[RPM_SMD_QDSS_A_CLK] = &sdm660_qdss_a_clk,
1037
+	[RPM_SMD_RF_CLK1] = &sdm660_rf_clk1,
1038
+	[RPM_SMD_RF_CLK1_A] = &sdm660_rf_clk1_a,
1039
+	[RPM_SMD_DIV_CLK1] = &sdm660_div_clk1,
1040
+	[RPM_SMD_DIV_A_CLK1] = &sdm660_div_clk1_a,
1041
+	[RPM_SMD_LN_BB_CLK] = &sdm660_ln_bb_clk1,
1042
+	[RPM_SMD_LN_BB_A_CLK] = &sdm660_ln_bb_clk1_a,
1043
+	[RPM_SMD_LN_BB_CLK2] = &sdm660_ln_bb_clk2,
1044
+	[RPM_SMD_LN_BB_CLK2_A] = &sdm660_ln_bb_clk2_a,
1045
+	[RPM_SMD_LN_BB_CLK3] = &sdm660_ln_bb_clk3,
1046
+	[RPM_SMD_LN_BB_CLK3_A] = &sdm660_ln_bb_clk3_a,
1047
+	[RPM_SMD_RF_CLK1_PIN] = &sdm660_rf_clk1_pin,
1048
+	[RPM_SMD_RF_CLK1_A_PIN] = &sdm660_rf_clk1_a_pin,
1049
+	[RPM_SMD_LN_BB_CLK1_PIN] = &sdm660_ln_bb_clk1_pin,
1050
+	[RPM_SMD_LN_BB_CLK1_A_PIN] = &sdm660_ln_bb_clk1_pin_a,
1051
+	[RPM_SMD_LN_BB_CLK2_PIN] = &sdm660_ln_bb_clk2_pin,
1052
+	[RPM_SMD_LN_BB_CLK2_A_PIN] = &sdm660_ln_bb_clk2_pin_a,
1053
+	[RPM_SMD_LN_BB_CLK3_PIN] = &sdm660_ln_bb_clk3_pin,
1054
+	[RPM_SMD_LN_BB_CLK3_A_PIN] = &sdm660_ln_bb_clk3_pin_a,
1055
+};
1056
+
1057
+static const struct rpm_smd_clk_desc rpm_clk_sdm660 = {
1058
+	.clks = sdm660_clks,
1059
+	.num_clks = ARRAY_SIZE(sdm660_clks),
1060
+};
1061
+
6141062 static const struct of_device_id rpm_smd_clk_match_table[] = {
6151063 	{ .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 },
1064
+	{ .compatible = "qcom,rpmcc-msm8936", .data = &rpm_clk_msm8936 },
6161065 	{ .compatible = "qcom,rpmcc-msm8974", .data = &rpm_clk_msm8974 },
1066
+	{ .compatible = "qcom,rpmcc-msm8976", .data = &rpm_clk_msm8976 },
1067
+	{ .compatible = "qcom,rpmcc-msm8992", .data = &rpm_clk_msm8992 },
1068
+	{ .compatible = "qcom,rpmcc-msm8994", .data = &rpm_clk_msm8994 },
6171069 	{ .compatible = "qcom,rpmcc-msm8996", .data = &rpm_clk_msm8996 },
1070
+	{ .compatible = "qcom,rpmcc-msm8998", .data = &rpm_clk_msm8998 },
1071
+	{ .compatible = "qcom,rpmcc-qcs404",  .data = &rpm_clk_qcs404  },
1072
+	{ .compatible = "qcom,rpmcc-sdm660",  .data = &rpm_clk_sdm660  },
6181073 	{ }
6191074 };
6201075 MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table);